JP2882349B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device, and more particularly to a semiconductor device having improved noise characteristics.

[0002]

2. Description of the Related Art Referring to FIG. 6, which is a block diagram showing the configuration of a conventional semiconductor device of this type, a CPU 1 for controlling an internal circuit and an output latch for temporarily holding a signal output from the CPU 1 to the outside. 2, an oscillator 3 comprising a crystal oscillator or a ceramic oscillator and a capacitor and generating a reference frequency of a clock signal supplied to an internal circuit including the CPU 1, and an output latch 2 serving as an interface between the output latch 2 and an external circuit. To the outside, the high level of the power supply potential VDD level or the ground potential VSS
Output buffer 4 that outputs a low-level voltage value
And an output terminal 5 connected to the output buffer.

Here, a CPU 1, an output latch 2, and an oscillator 3
And the output buffer 4 are supplied with the same power supply potential VDD and ground potential VSS. Therefore, the high-level signal voltage value output from output terminal 5 is equal to power supply potential VD
A voltage level substantially equal to D is output.

[0004] Referring to FIG. 2 which compares the noise characteristics superimposed on the power supply line between the conventional example and the present invention, the output terminal 5 is shown.
A harmonic component of noise generated in the CPU 1 or the oscillator 3 is superimposed on the signal output from the power supply potential VDD supply line 6.

[0005]

In the above-described conventional semiconductor device, the internal CPU 1, the output latch 2, the oscillator 3, and the output buffer 4 are connected by the same power supply VDD supply line 6 and the ground potential VSS. Therefore, the internal CPU 1,
Alternatively, there is a drawback that a harmonic component of noise generated in the oscillator 3 is output from the output terminal 5 to an external circuit through the supply line 6 of the power supply VDD which is connected in common.

Therefore, an external circuit connected to the external terminal 5 may malfunction.

An object of the present invention has been made in view of the above-mentioned drawbacks, and has as its object to reduce harmonic components of noise generated in an internal CPU or an oscillator which is output to an external circuit via an external terminal.

[0008]

It features of the semiconductor device of the present invention In order to achieve the above object, according an oscillator for generating a reference frequency, and an internal circuit including at least an internal CPU that operates at an internal clock generated from the reference frequency, this internal Yes and an output buffer for outputting the circuit and the external circuit between in tough Ace and becomes low-level signal of the output signal to the power supply potential level outside the high level or the ground potential level of the internal circuit of the
The oscillator and the internal C
Boost the low power supply potential supplied to internal circuits including PU
By supplying it as a power supply potential of the output buffer,
Clock noise generated from the internal operation clock.
An internal circuit output signal harmonic components of are suppressed to a low level
The output buffer by inputting the output buffer as
Clock that increases the level difference from the output signal of the
It is to have a Kkunoizu suppression means.

[0009]

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a main part of an embodiment of the semiconductor device of the present invention. Referring to FIG. 1, this semiconductor device includes a CPU 1 for controlling an internal circuit, an output latch 2 for temporarily holding a signal 101 output from the CPU 1 to the outside, a crystal resonator or a ceramic resonator, and a capacitor. An oscillator 3 configured to generate a reference frequency of a clock signal to be supplied to an internal circuit including the CPU 1 and an interface between the output latch 2 and an external circuit, and a signal 102 output from the output latch 2 are externally supplied to a power supply potential VDD2 An output buffer 4 that outputs a low-level voltage value of the high level or the ground potential VSS level, a boost regulator 6 that generates a power supply potential VDD2 supplied to the output buffer 4 from an internal power supply potential VDD1, and an output buffer. And an output terminal 5. Source potential VDD1 is supplied, and a low voltage operation.

That is, the difference from the conventional example is that the power supply potential VDD1 supplied to the internal circuit and the power supply potential VDD2 supplied to the output buffer 4 are divided and supplied by the boosting regulator 6.

As can be understood from the above-described configuration, by providing a boost regulator 6 for supplying a power supply potential VDD2 dedicated to the output buffer 4 separately from the power supply potential VDD1 supplied to the internal circuit, the internal CPU 1 The latch 2 and the oscillator 3 are operated at a low voltage, and the output buffer 4 is operated at a normal operating voltage, for example, 5 V through a booster regulator 6.

The boost regulator 6 applied here may be a generally used circuit, and it is sufficient that a voltage difference between the internal circuit and the output buffer can be generated to reduce a noise component. For example, referring to FIG. 3 showing an example of a booster circuit of a known technique, this booster circuit includes a high-speed level fluctuation compensation circuit 31 and a low-speed level fluctuation compensation circuit 3.
2 circuits are connected in parallel.
The boosted VDH is output from the parallel connection point C of the two circuits. At the time of deactivation during standby, the low-speed level compensation circuit 32
Only works. The level of the boosted power supply potential VDH is secured by a pulse constantly applied from the ring oscillator OSC.

When activated, the pump circuits in the high-speed level fluctuation compensating circuit 31 are driven by the clocks φ1, φ2, φH. Therefore, charge is injected into the load every cycle to compensate for the charge consumed by the load.

By the above-described two systems of the power supply potential,
The fact that the internal circuit operates at low voltage means that the internal CP
The output level value of the harmonic component of the noise component generated by U1, the output latch 2, the oscillator 3, and the like also becomes low, and the level difference from the output level value output from the output buffer 4 becomes relatively large.

Referring again to FIG. 2, the horizontal axis indicates the reference frequency f in MHz, the vertical axis indicates the amount of noise generated in the internal circuit in decibels dB, and the noise characteristic in the conventional example is represented by a curve 7. The noise characteristic in the present embodiment is shown by a curve 8.

From this figure, it can be seen that the noise level of the curve 8 in the present embodiment is reduced as compared with the curve 7 of the conventional example.

Referring to FIG. 4, which is a block diagram showing a main part of a modification of the first embodiment, this semiconductor device comprises:
A CPU 1 for controlling an internal circuit, an output latch 2 for temporarily holding a signal output from the CPU 1 to the outside, and a clock signal supplied to an internal circuit including the CPU 1 which includes a crystal oscillator or a ceramic oscillator and a capacitor , A peripheral function 9 for counting the operation time of the CPU 1, an OR signal ORing an output signal 106 of the output of the peripheral function 9 and an output signal 105 of the output latch 2, and an OR 10 An output buffer 4 which interfaces with the output signal 107 of the external circuit and the signal output from the OR 10 to output a high-level voltage of the power supply potential VDD2 or a low-level voltage of the ground potential VSS to the outside, and the output buffer 4 Regulator that generates the power supply potential VDD2 supplied to the power supply from the internal power supply potential VDD1 6 and an output terminal 5 connected to the output buffer 4. Each component other than the output buffer 4 is supplied with the low power supply potential VDD1, and these components operate at a low voltage. I have.

This circuit differs from the first embodiment in the function of the output terminal 5b. That is, while the output terminal 5a of the first embodiment has a normal output buffer function, this output terminal 5b is used when one of the peripheral functions 9 is selected and output to the outside. One terminal is commonly used as an output terminal for a plurality of output signals, and an increase in the number of terminals is reduced.

For example, when the output signal 105 of the output latch 2 is set to the low level, the output signal 106 of the peripheral function is output.
Is output to the output terminal via the output buffer 4 and the output latch 2 is set in a state where the output of the peripheral function 9 is set to low level.
Is output to the output terminal 5b via the output buffer 4 in the same manner.

Also in this example, the internal CPU 1, the output latch 2, the oscillator 3, and the peripheral function 9 can be operated at a low voltage, so that the output from the output terminal 5b is performed as in the first embodiment. The noise component is reduced as shown by a curve 8 in FIG.

The noise component which can be reduced in the first embodiment and its modification is the power supply potential VDD1.
Is a transmission noise superimposed on the supply line of the CPU 1 from the CPU 1. Referring to FIG.
The waveform 11 of the operation lock of U1 is a voltage value V, the horizontal axis is time t, the vertical axis is a function g (t) of time, and the width of a square wave is T,
When this square wave is subjected to Fourier transform, g (t) = [2V (cost- (1/3) cos3t +
(1/5) cos5t- (1/7) cos7t + ...
...)] / T.

In general, the Fourier transform value is proportional to the transmission noise, and is therefore proportional to the voltage V of the waveform 11 in the above equation.

For example, if the operation is performed with the voltage value reduced to 1/2 of the conventional value, the noise level is reduced to 1/2 the conventional value.

[0025]

As described above, the semiconductor device of the present invention has an internal circuit including at least an oscillator for generating a reference frequency, an internal CPU operating with an internal operation clock generated from the reference frequency, and an internal circuit. And an output buffer serving as an interface between external circuits and outputting an output signal of the internal circuit to the outside at a high level of the first power supply potential level or a low level of the ground potential level, and a first buffer supplied only to this output buffer. And a regulator means for generating one power supply potential from the other of the power supply potential and the second power supply potential which is lower than the first power supply potential and supplied to the internal circuit including the CPU. And operates the internal circuit at a low voltage to suppress the level of a noise component generated from the internal operation clock, and Since the output to the output terminal Te, can reduce the noise output to an external circuit, which contributes to the improvement of the reliability of the semiconductor device.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a characteristic diagram comparing noise component reduction characteristics of the present invention and a conventional example.

FIG. 3 is a block diagram illustrating an example of a booster circuit.

FIG. 4 is a block diagram showing a modification of the first embodiment of the present invention.

FIG. 5 is an operation clock waveform diagram of the CPU 1;

FIG. 6 is a block diagram of an example of a conventional semiconductor device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Internal CPU 2 Output latch 3 Oscillator 4 Output buffer 5 Output terminal 6 Boost regulator (Step-down regulator) 9 Peripheral circuit 10 OR 21 Current mirror differential amplifier 22 pMOS transistor 31 High-speed level fluctuation compensation circuit 32 For low-speed level fluctuation compensation

Claims (1)

(57) [Claims] An oscillator for generating a 1. A reference frequency, and an internal circuit including at least an internal CPU that operates at an internal clock generated from said group <br/> quasi frequency, contact the internal circuit
In a semiconductor device having an output buffer for outputting the in-tough Ace and becomes low-level signal of the internal circuit output signal power potential level to the outside of the high level or the ground potential level between the external circuit and the oscillator and before
The low power supply potential supplied to the internal circuits including the internal CPU
Boost the voltage and supply it as the power supply potential of the output buffer.
As a result, an internal circuit output in which harmonic components of clock noise generated from the internal operation clock are suppressed to a low level.
Input to the output buffer as a force signal
Increase the level difference from the output signal of the
And a clock noise suppressing unit .