JP3139879B2 - Power supply voltage conversion circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power supply voltage conversion circuit which is built in a semiconductor integrated circuit such as a one-chip microcomputer and converts a power supply voltage to a predetermined voltage.

[0002]

2. Description of the Related Art One of MOS transistors
Semiconductor integrated circuits such as chip microcomputers include:
Operational consumption current Idd Idd = fcv (where f: operating frequency, c: internal capacitance, v: power supply voltage) flows. In order to reduce the operation current consumption, a design is often performed in which the power supply voltage is kept low within a range where the operation frequency characteristics can be satisfied. In addition, even in the same integrated circuit, in a circuit with a relatively high frequency represented by a crystal oscillation circuit or the like, the operating frequency characteristics and the low current consumption are reduced by a measure of separating a power supply and partially supplying a low power supply voltage. I try to balance them. Further, in an integrated circuit having a built-in liquid crystal driving circuit for driving a liquid crystal display, the driving voltage is determined by the characteristics of the liquid crystal display element, the capacity of the liquid crystal display, and the like. Higher voltages may be required. However, in many one-chip microcomputers, the number of set components is reduced for the purpose of reducing the manufacturing cost, so that the power supply voltage supplied from outside the integrated circuit is often limited to one type. As described above, when a plurality of power supply voltages are required inside the integrated circuit, a voltage boosting circuit (hereinafter, referred to as a boosting circuit) or a voltage dropping circuit (hereinafter, a step-down circuit) is based on a single power supply externally applied. Is converted to a desired voltage.

Here, the operating principle and characteristics of the booster circuit and the step-down circuit will be briefly described. FIG. 3 shows an example of a step-down circuit using a capacitor coupling. In the figure, C11 is a step-down capacitor, the capacitance C ₁ C12 is a storage capacitor of capacitance C ₂ for smoothing and holding a voltage stepped down. Now, as an initial state, the step-down clock signal CK
When 1 is "1", the transistors N11 and P13 are on and the transistors P12 and P14 are off. At this time, the electrode A1 of the capacitor C11 is connected to the ground level (GN
D) is applied, the electrodes B1 and down output V ₁ of the capacitor C11 shall be arbitrary potential V _S10 is held. Next, when the step-down clock signal CK1 becomes "0", the transistors P12 and P14 are turned on, the transistors N11 and P13 are turned off, and the electrode B1 of the capacitor C11 is turned off.
Is applied with a VDD level. At this time, the capacitor C
11 and the voltage V _S11 of the step-down output V ₁ are in the state of the clock CK1 = “1” and the clock CK1 = “0”
Since the charge is stored in the state of (V DD -V _S10 ) · C ₁ + V _S10 · C ₂ = V _S11 (C ₁ + C ₂ ), V _S11 = {(VDD−V _S10 ) · C ₁ + V _S10 C ₂ } / (C ₁ + C ₂ ) (1.1)

Next, the step-down clock signal CK1 becomes "1".
, The transistors N11 and P13 are turned on again, the transistors P12 and P14 are turned off, and the capacitor C
A ground level is applied to the eleventh electrode A1. At this time, the electrodes B1 and down output V ₁ of the voltage of the capacitor C11, V _S12 is the charge state of the clock signal CK1 = "0" state and the clock signal CK1 = "1" is stored, (VDD-V _{S11) · C 1 + V S11} · C 2 = V S12 (C 1 + C 2) _{Therefore, V S12 = {(VDD-} V S11) · C 1 + V S11 · C 2} / (C 1 + C 2) ... (1 .2) Continuing gave step-down clock signal CK1, the formula (1.1) (1.2) than the potential of V _{1 was, V S1n + 1 = {(} VDD-V S1n) · C 1 + V S1n · C 2} / (C ₁ + C ₂ ) = (C ₂ −C ₁ ) V _S1n / (C ₁ + C ₂ ) + C ₁ · VDD / (C ₁ + C ₂ ) In _{general, a n + 1 = pa n} + q (n = 1,2,
The expression represented by (3,...) Is a limit value when | p | <1 is satisfied.

[0005]

(Equation 1) Because

[0006]

(Equation 2) And converges to VDD / 2.

Next, when a load current I _V1 flows through the output terminal V ₁ of the step-down circuit shown in FIG. 3, the voltage drop at the output terminal V ₁ and the input frequency f _CK1 of the step-down clock signal CK ₁
Will be described. Flows a constant load current to the output terminal V _1, the output waveform of the output terminal V ₁ was a saw-tooth wave as shown in FIG. The maximum value of the potential of this sawtooth wave is VH1,
Assuming that the minimum value is VH2 and the period of the clock signal CK1 is "1" and the period of "0" are equal, the following condition is satisfied.

(1) The amount of charge flowing out during the period when the transistors P12 and P14 are on (or the transistors N11 and P13 are on) and 1 / 2f of the step-down clock signal CK1
Since the amount of charge consumed is equal in period _{CK1, (C 1 + C 2} ) (VH1-VH2) = I V1 / 2f CK1 ... (1.3) is derived.

(2) 1/2 of the step-down clock signal CK1
In the period of f _CK1, the amount of charge charged in the capacitor C11 is equal to the amount of charge consumed in the period of ｆ f _CK1 of the step-down clock signal CK1, so that 2 (VDD / 2−VH2) · C ₁ = I _V1 / 2f _CK1 (1.4) is derived. Therefore, from equation (1.4), VH2 = {VDD- _IV1 / (2f _CK1 · C ₁ )} / 2 (1.5) When equation (1.5) is substituted into equation (1.3), VH1 = a _{[VDD + (C 1 -C 2} ) / {C 1 · (C 1 + C 2)} · I V1 / 2f CK1] / 2. Therefore, the magnitude of the sawtooth wave represented by the maximum value (VH1) and the minimum value (VH2) is VH1−VH2 = I _V1 / {(C ₁ + C ₂ ) · 2f _CK1 }, and the output voltage at no load (VDD / 2)-minimum value (V
H2). The maximum voltage drop amount is VDD / 2−VH2 = I _V1 / (4C ₁ · f _CK1 ). From this result, it is found that the magnitude of the sawtooth wave and the maximum voltage drop amount are both proportional to the load current I _V1 and inversely proportional to the input frequency f _CK1 of the step-down clock signal CK1.

FIG. 4 shows an example of a booster circuit using a capacitor coupling. Step-up capacitor in the figure C21 is capacitance C _3, C22 is a storage capacitor of capacitance C ₄ for smoothing and holding the voltage boosted. Now, when the boosting clock signal CK2 is "1" as an initial state, the transistors N21 and P23 are turned on, the transistors P22 and P24 are turned off, the ground level is applied to the electrode A2 of the capacitor C21, and V is applied to the electrode B2. It is assumed that a voltage of ₁ , for example, V _V1 level is applied, and the boosted output V ₂ holds an arbitrary potential V _S20 . Next, when the boosting clock signal CK2 becomes “0”, the transistor P
22 and P24 are turned on, the transistors N21 and P23 are turned off, and the VDD level is applied to the electrode A2 of the capacitor C21. At this time, the voltage V _S21 electrode B2 and boost the output V ₂ of the capacitor C21 is the clock signal CK2 =
Since the electric charge is stored in the state of “1” and the state of CK2 = “0”, (VDD + V _V1 ) C ₃ + V _S20 · C ₄ = V _S21 (C ₃ + C ₄ ) Therefore, V _S21 = ｛(VDD + V _V1 ) C ₃ + V _S20 · C ₄ ｝ / (C ₃ + C ₄ ) (1.6) Next, when the boosting clock signal CK2 becomes “1”, the transistors N21 and P23 are turned on again, and the transistor P
22 and P24 are turned off, and the electrode A of the capacitor C21 is turned off.
2 is applied with the ground level, and V _B1 is applied to the electrode B2. At this time, when there is no load current, the boosted output V ₂ holds the previous state, that is, the voltage V _S21 .
When the boosting clock signal CK2 is continuously applied, the equation (1.6) is obtained.
More potential of V _{1 was, V S2n + 1 = {(} VDD + V V1) C 3 + V S2n · C 4} / (C 3 + C 4) = C 4 · V S2n / (C 3 + C 4) + C 3 (VDD + V V1 ) / (C ₃ + C ₄ ) Therefore, like the step-down circuit,

[0011]

(Equation 3) And converges to the voltage of VDD + V _V1 .

Next, the output V ₂ of the booster circuit shown in FIG.
For the relationship between the input frequency f _CK2 of the voltage drop and boost clock signal CK2 of V ₂ in the case where I _V2 becomes the load current flows will be described. It flows a constant load current V _2, V
The waveform ₂ is a sawtooth waveform as shown in FIG. The maximum value of the voltage of the sawtooth waveform is V _D1 , the intermediate change point is V _D2 , the minimum value is V _D3 , and the clock signal CK2 has a period of “1” and a period of “0”.
Are equal, the following condition is satisfied.

(1) (C ₂₁ supply charge) + (C ₂₂ immediately before transistor P ₂₄ is turned on) and (C ₂₁ immediately after transistor P ₂₄ is turned on) + (C ₂₂ held charge) Since they are equal, C ₃ (VDD + V _V1 ) + C ₄ V _D3 = (C ₃ + C ₄ ) V _D1 (1.7) (2) The charge amount flowing out during the period when P22 and P24 are on and P22 and P24 are (C ₃ + C ₄ ) (V _D1 −V _D2 ) = C ₄ (V _D2 −V _D3 ) (1.8) (3) The boosting clock signal CK 2 a charge amount stored in the C ₃ in the period of 1 / f _CK2, since the amount of charge consumed is equal in period _{1 / f CK2, (VDD +} V V1 -V D2) C 3 = I V2 / f CK2 ... ( 1.9) is derived. Therefore, from equation (1.9), V _D2 = (VDD + V _V1 ) −I _V2 / (C ₃ · f _CK2 ) Also, from equations (1.8) and (1.9), (C ₃ + C ₄ ) V _{D1 + C 4 · V D3 =} (C 3 + 2C 4) (VDD + V V1) -I V2 (C 3 + 2C 4) / (C 3 · f CK2) ... (2.0) C 4 · than formula (1.7) V _D3 = (C ₃ + C ₄ ) V _D1 −C ₃ (VDD + V _V1 ) By substituting this into the equation (2.0), V _D1 = (VDD + V _V1 ) − (C ₃ + 2C ₄ ) I _V2 / ｛2C ₃ (C ₃ + C ₄ ) f _{CK2 す る と} By substituting this into equation (1.7), V _D3 = (VDD + V _V1 ) − (C ₃ + 2C ₄ ) I _V2 / (2C ₃ · C ₄ · f _CK2 ) . Therefore, the magnitude of the sawtooth wave represented by the maximum value (V _D1 ) _−the minimum value (V _D3 ) is V _D1 −V _D3 = (C ₃ +2)
C ₄ ) I _V2 / {2C ₄ (C ₃ −C ₄ ) f _CK2 }, and the maximum voltage drop expressed by the output voltage (VDD−V _V1 ) −minimum value (V _D3 ) at no load is _{(VDD + V V1) -V D3} = (C 3 + 2C 4) becomes _{I V2 / (2C 3 · C} 4 · f CK2). From this result, it can be seen that the magnitude of the sawtooth wave and the maximum voltage drop are both proportional to the load current I _V2 and inversely proportional to the input frequency f _CK2 of the boosting clock signal CK2.

As described above, the output voltage of the booster circuit or the step-down circuit is designed so that a desired potential is output when there is no load, that is, when the output current is zero. When the load current is increased from this state, the output voltage drops from a desired value, and at the same time, power supply noise indicated by the sawtooth wave is generated.

FIG. 2 shows a conventional power supply voltage conversion circuit having a booster circuit and a step-down circuit and capable of supplying a plurality of power supply voltages from a single power supply voltage. In FIG. 2, a power supply potential VDD and a ground potential GND are the only power supplies supplied from outside the integrated circuit.
It is assumed that 3.0 V and a ground potential of, for example, 0 V are supplied.

In FIG. 1, a clock oscillator G10 outputs a step-down clock signal CK1 and a step-up clock signal CK2. The step-down clock signal CK1 and the step-up clock signal CK2 have fixed frequencies f _CK1 and f _CK2 and are input to the step-down circuit S11 and the step-up circuit S21, respectively. The step-down circuit S11 includes a step-down capacitor C11.
Is connected. The step-down circuit S11 drops the voltage from the power supply potential VDD by the coupling operation of the step-down capacitor C11 with reference to the ground potential, and
Outputs ₁ . In this case, the step-down voltage V ₁ is, for example, 1.5 V
It is. The boosting circuit S21 has a boosting capacitor C
21 are connected. The booster circuit S21 from the step-down voltage V ₁ and the power supply potential VDD is outputted from the step-down circuit S11 with reference to the ground potential, and outputs the boosted voltage V ₂ performs voltage boosted by coupling operation of the step-up capacitor C21. In this case, the boosted voltage V ₂ is, for example, 4.5 V. A smoothing capacitor C is connected to an output terminal of the step-down circuit S11.
12 is connected to the output terminal of the booster circuit S21 is connected to a smoothing capacitor C22, the step-down voltage V _1, the boosted voltage V ₂ is is held is smoothed respectively by the smoothing capacitor C12, C22, crystal oscillator Circuit R
11, and supplied to the liquid crystal drive circuit R21. Details of the step-down circuit S11 and the step-up circuit S21 are as shown in FIGS.

In FIG. 2, the step-down voltage V ₁ is consumed by the crystal oscillation circuit R11 and the step-up circuit S21, and the step-up voltage V ₂
Is consumed by the liquid crystal drive circuit R21. These circuits R1
1, the step-down voltage V ₁ and the step-up voltage V ₂ decrease due to the load current flowing through R21, and power supply noise occurs. The magnitude depends on the magnitude of the load current as described above. In designing the product, the capacity of the boosting capacitor C21, the capacity of the step-down capacitor C11 and the voltage of the boosting clock signal CK2,
It is necessary to set the frequency of the step-down clock signal CK1.

However, the step-up or step-down capacitor is
When installed outside an integrated circuit, smaller capacitance must be used for miniaturization, and inexpensive components are often selected to reduce set cost, which limits the available capacitance. You. Even in the case of being installed inside an integrated circuit, it is necessary to reduce the pattern area and to design the capacitor with a small capacitance in order to reduce the chip size and the manufacturing cost of the integrated circuit. is there. Under these constraints, in order to suppress the voltage drop of the booster circuit or the step-down circuit with respect to the load current within the specification range, the frequency of the step-up or step-down clock signal should be appropriately set according to the capacity of the available capacitor. Good.

[0019]

By the way, in the above-mentioned conventional semiconductor integrated circuit, as described above, the frequency suitable for the clock signal for step-up or step-down is determined by the magnitude of the load current. That is, in any operating state, the frequency of the clock signal for step-up or step-down is determined in the operating state where the load current is maximized so as to satisfy the specification for the minimum power supply noise. In this case, even if the integrated circuit has a relatively small load current in an average operation state, if the maximum value of the load current is large, it is necessary to continue to supply a very high frequency step-up or step-down clock signal. However, when the operating frequency of the booster circuit or the step-down circuit is high, the charge / discharge current to the parasitic capacitance at the connection terminal of the boosting capacitor or the gate electrode of the transistor increases, and the operation current consumption increases. The charge / discharge current I is 0.025 m from I = f · C · V when the clock frequency f is 1 MHz, the parasitic capacitance C is 5 PF, and the power supply voltage V is 5 V.
A.

In recent years, the operating current consumption of low power consumption LSIs typified by LSIs for watches and calculators is generally on the order of several μA, and this charging / discharging current cannot be ignored from the viewpoint of the current consumption of the entire integrated circuit. .

When the clock frequency is high, malfunction or latch-up is likely to occur due to power supply noise due to switching of a clock buffer in the integrated circuit, parasitic capacitance between wirings inside the integrated circuit, and the like. This undesirably results in loss of the reliability of the integrated circuit.

As shown in FIG. 2, the step-down circuit S11
And a booster circuit S21 connected in series, and a step-down circuit S11
For such use constitutes the output power V ₁ as a power source for the next stage of the booster circuit S21, i.e., 3V, make 1.5V from 0V, than the 1.5V 3V + 1.5V =
In the case of generating 4.5 V, the next stage booster circuit S21
When the load current I _V2 is increased, so that the load current I _V1 of the pre-stage of the step-down circuit S11 is also increased under the influence. Therefore, the output voltage V ₁ of the step-down circuit S11 is reduced, it will emit the power supply noise. That is, the variation of the load current I _V2, the output voltage V ₁ of the step-down circuit S11 is varies. This is, for example, a circuit supplied with V ₁ as a power supply,
In this case, the power supply of the crystal oscillation circuit R11 has the desired voltage 1.
It means that the voltage drops from 5V and noise is mixed. Many one-chip microcomputers use a system that supplies a voltage stepped down by a step-down circuit S11 to a crystal oscillation circuit R11 as shown in FIG. 2 in order to reduce current consumption.

FIG. 7 is a general circuit example of the crystal oscillation circuit R11. In FIG. 7, one electrode of the crystal oscillator XT is grounded via a capacitor C _X1 , and the other electrode is grounded via a capacitor C _X2 . Further, one electrode of the crystal oscillator XT is a P-electrode constituting the inverter amplifier AMP.
MOS transistor P _X1 and N-type MOS transistor N
_X1 connected to the gates of these transistors _Px1 and _Nx1
The drain, i.e., the output terminal of the inverter amplifier AMP is connected to the other electrode of the crystal oscillator XT via a resistor R _X. The source of the transistor P _X1 is supplied with the output voltage V ₁ of the step-down circuit S11, the transistor N _X1
Drain is grounded.

An input terminal of the inverter amplifier AMP is connected to one end of a current path of a P-type MOS transistor P _X2 and an N-type MOS transistor N _X2 which constitute a feedback resistor Rfb, and a current path of the transistors P _X2 and N _X2 is connected. Is connected to the output terminal of the inverter amplifier AMP. The gate of the transistor N _X2 is connected to the source of the transistor P _X1 , and the transistor P _X2
Is connected to the source of the transistor N _X1 .

The inverter amplifier AMP receives a sine wave having a small amplitude near the threshold voltage from the crystal oscillator XT and inverts and amplifies the sine wave. At this time, by keeping the threshold voltage of the inverter amplifier AMP, the amplification gain, and the value of the feedback resistor Rfb constant, the crystal oscillation circuit R11 maintains a stable operation. That is, an operation with little frequency fluctuation is performed. However, the voltage drop or noise occurs in the power supply V _1, the inverter amplifier AM
P threshold voltage, amplification gain and feedback resistance Rf
The resistance value of b fluctuates. Therefore, stable amplification is lost and oscillation becomes unstable. This is the crystal oscillator circuit R
This impairs frequency stability, which is the eleventh feature.

In the conventional example shown in FIG.
Output voltage V ₁ of the 11 cases the power supply potential VDD is 3V 1.5
V, and VGS (gate-source voltage) of the transistor constituting the inverter amplifier AMP is 1.5 at the maximum.
It can only be V. Therefore, the transistor operates in the weak inversion region, and the change in the transistor performance with respect to a minute change in the power supply is significantly increased. That is, the above-described fluctuations in the threshold voltage, the amplification gain, and the feedback resistance are further increased. Therefore, the oscillation becomes unstable, and the minimum operation holding voltage characteristic is deteriorated. In the worst case, the oscillation operation stops. The crystal oscillation circuit R11 is often used as a system lock source in an integrated circuit, and it goes without saying that the entire integrated circuit will not function if the oscillation becomes unstable or stops.

Normally, all circuits formed in an integrated circuit are secured with a stable supply of power, and fluctuations in the power supply are the greatest causes of deterioration in reliability and characteristics. In order to suppress the fluctuation of the output voltage V ₁ of the step-down circuit S11 for the load current I _V2, as it is necessary to increase the frequency of the voltage-falling clock signal CK1 is supplied to the step-down circuit S11, and in this case also above This causes problems such as an increase in operation current consumption and a decrease in reliability.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems. It is an object of the present invention to convert a predetermined voltage from a power supply voltage stably while suppressing an increase in operation current consumption. And with less noise,
An object is to provide a highly reliable power supply voltage conversion circuit.

[0029]

According to the present invention, a first clock generating means for generating a first clock signal and a second clock generating means for generating a second clock signal having a lower frequency than the first clock signal are provided. Clock generation means and clock signal
Multiple switching elements whose conduction is controlled according to the level
And the conduction state of these switching elements.
The first power supply voltage and the higher second power supply voltage
Higher than the first power supply voltage,
For step-down storing a third power supply voltage lower than the second power supply voltage
Having a capacitor, stored in the step-down capacitor
A first voltage conversion means for supplying the third power supply voltage to the first load, the conduction control of in accordance with the level of the clock signal
Switching elements, and these switches
The first to third power supplies according to the conduction state of the switching element.
A fourth voltage higher than the third power supply voltage,
A boost capacitor for storing the power supply voltage of the
Supplying the fourth power supply voltage stored in the first capacitor to a second load of a type different from the first load.
Supplying the first clock signal generated by the first clock generating means to the first and second voltage converting means when the second load operates and the second load; When the load is stopped, the second clock signal generated by the second clock generation means is transmitted to the first and second clock signals.
Signal switching means for supplying to the voltage conversion means,
It is characterized in that it is possible to reduce power supply noise accompanying supply of a power supply voltage to the first and second loads and to optimize current consumption according to the load.

Further, the present invention provides a frequency dividing means for dividing a first clock signal to generate a second clock signal having a lower frequency than the first clock signal, and a level of the clock signal.
A plurality of switching elements whose conduction is controlled according to the
And depending on the conduction state of these switching elements,
Conversion from one power supply voltage to a higher second power supply voltage
And the second power supply voltage is higher than the first power supply voltage.
Step-down capacitor for storing a third power supply voltage lower than the power supply voltage
The step-down capacitor stored in the step-down capacitor.
The third power supply voltage and a first voltage conversion means for supplying a first load, double that conduction is controlled according to the level of the clock signal
Number of switching elements and these switching elements
From the first to third power supply voltages according to the conduction state of the
A fourth power supply that is converted and that is higher than the third power supply voltage
A boost capacitor for storing a voltage;
A second voltage conversion unit that supplies the fourth power supply voltage stored in the capacitor to a second load of a type different from the first load, and a second voltage conversion unit that operates when the second load operates. Is supplied to the first and second voltage conversion means,
Signal switching means for supplying a second clock signal generated by the frequency dividing means to the first and second voltage converting means when the second load is stopped;
It is characterized in that it is possible to reduce power supply noise accompanying supply of a power supply voltage to the second load and optimize current consumption according to the load.

Further, the present invention provides a frequency dividing means for dividing the first clock signal to generate a second clock signal having a lower frequency than the first clock signal, and dividing the clock signal.
Dividing circuit, conducting by the output signal of this dividing circuit
Controlled switching elements, these switching elements
The first power supply voltage and the
Said first power supply converted from a high second power supply voltage
A third voltage higher than the voltage and lower than the second power supply voltage;
Power supply voltage and conversion from the first to third power supply voltages
A fourth power supply voltage higher than the third power supply voltage
A lifting capacitor for storing the
Said third power supply voltage stored in the service to the first load, before
Voltage conversion means for supplying the fourth power supply voltage stored in the raising / lowering capacitor to a second load of a type different from the first load, and the first load when the second load operates.
And a signal switching means for supplying the second clock signal to the voltage conversion means when the second load is stopped.
It is characterized in that it is possible to reduce power supply noise accompanying supply of a power supply voltage to the second load and optimize current consumption according to the load.

The voltage converting means is connected between a frequency dividing means for dividing a clock signal supplied from the signal switching means and a first power supply and a second power supply higher than the first power supply. A plurality of switching elements whose conduction is controlled by an output signal of the frequency dividing means, and a plurality of switching elements connected between the switching elements and storing electric charge in accordance with the conduction of the switching elements; a voltage higher than the second power supply or a second voltage; And a capacitor that outputs a voltage lower than the power supply.

[0033]

In other words, the signal switching means operates the first load generated by the first clock generating means when the second load operates.
Is supplied to the first and second voltage conversion means,
When the second load is stopped, the second clock having a lower frequency than the first clock signal generated by the second clock generation means.
Is supplied to the first and second voltage conversion means. Therefore, since the frequency of the clock signal supplied to the first and second voltage conversion means is switched according to the state of the second load , the amount of current supplied to the first and second loads can be optimized. In addition, the voltage drop and the power supply noise can be reduced.

Further, the frequency of the first clock signal is divided by the frequency dividing means, and the frequency of the second clock having a lower frequency than that of the first clock signal is reduced.
, The number of clock generating means can be reduced.

Further, one capacitor is shared by the first and second voltage conversion means, and this capacitor is time-divisionally controlled by a plurality of switching elements whose conduction is controlled by the frequency-divided clock signal. , The second voltage converting means can be one voltage converting means.

[0036]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a first embodiment of the present invention. In FIG. 1, the same portions as those in FIG. 2 are denoted by the same reference numerals, and only different portions will be described.

In FIG. 1, a first clock oscillator G11 built in the one-chip microcomputer MC oscillates low-frequency clock signals CK11 and CK12,
The second clock oscillator G21 oscillates high frequency clock signals CK21 and CK22. Clock signal CK1
1 and CK12 may be the same frequency or different frequencies.
The clock signals CK21 and CK22 may have the same frequency or different frequencies. First clock oscillator G11
The clock signal CK11 output from the second clock oscillator G21 and the clock signal CK21 output from the second clock oscillator G21 are supplied to the input terminal of the first signal switching circuit K11, and the clock signal CK output from the first clock oscillator G11.
12 and the clock signal CK22 output from the second clock oscillator G21 are supplied to the input terminal of the second signal switching circuit K21. The first and second signal switching circuits K11,
K21 is a CPU of a one-chip microcomputer MC
The switching is performed by a switching signal SW1 output from the switch 10. The output terminal of the first signal switching circuit K11 is connected to the input terminal of the step-down circuit S11, and the output terminal of the second signal switching circuit K21 is connected to the input terminal of the boost circuit S21.

The operation of the above configuration will be described. The output of the liquid crystal drive circuit R21 is fixed when the liquid crystal driving circuit R21 is stopped, that is, in the non-display state, and the load current I _V2 becomes “0”.
In the operating state, that is, in the display state, the load current I _V2
Flows.

When the liquid crystal drive circuit R21 is in a stopped state, the CPU 10 outputs a "0" level switching signal SW1. The second signal switching circuit K21 outputs the switching signal SW
According to 1, the clock signal CK12 is selected and supplied to the booster circuit S21. Further, the first signal switching circuit K11
Is a clock signal CK11 according to the switching signal SW1.
And supplies it to the step-down circuit S11. At this time, since the load current I _V2 is “0” as described above, there is no charge flowing out of the booster circuit S21, and the current consumption is only the switching current of the booster circuit itself and the gate capacitance parasitic on the booster circuit. Is almost a value close to “0”. Therefore, the load current I _V1 of the step-down circuit S11 is
It is limited to one current consumption. This is the liquid crystal drive circuit R2
1 is very small compared to the current consumption when it is operating. Therefore, even if the step-down circuit S11 is driven by the low-frequency clock signal CK11, the voltage drop and the amount of noise are suppressed low, and it is possible to sufficiently satisfy the predetermined specifications.

On the other hand, the CPU 10 has a liquid crystal driving circuit R21.
Outputs an "1" level switching signal SW1 when is in the operating state. At this time, the second signal switching circuit K21
The clock signal CK22 is selected according to the switching signal SW1, and supplied to the booster circuit S21. Further, the first signal switching circuit K11 selects the clock signal CK21 according to the switching signal SW1, and supplies the clock signal CK21 to the step-down circuit S11. Therefore, the high-frequency clock signals CK22 and CK21 are supplied to the booster circuit S21 and the step-down circuit S11. Therefore, even if the current consumption of the liquid crystal driving circuit R21 increases, the current supply capability of the booster circuit S21 improves, so that the voltage drop of the output voltage V2 and the noise amount can be suppressed low. In addition, the booster circuit S increases as the load current _IV2 increases.
21 increases, and I _V1 increases. However, since the current supply capability of the step-down circuit S11 is also improved, the output voltage V
1 is also stable, and voltage drop and power supply noise can be reduced.

According to the above embodiment, the liquid crystal driving circuit R21
Is in the operating state, the booster circuit S21 and the step-down circuit S
11 is supplied with a high frequency clock signal, and when the liquid crystal drive circuit R21 is stopped, a low frequency clock signal is supplied to the booster circuit S21 and the step-down circuit S11. Therefore, when the liquid crystal drive circuit R21 is stopped, current consumption and power supply noise can be reduced, and when the liquid crystal drive circuit R21 is operating, a drop in output voltage can be reduced.

FIG. 8 shows a second embodiment of the present invention.
8, the same parts as those in FIG. 1 are denoted by the same reference numerals. FIG. 8 has a clock signal input terminal 11 to which a clock signal CK3 is input from outside the integrated circuit. This input terminal 11 is connected to a first signal switching circuit K12.
, And to the first signal switching circuit K12 via the frequency dividing circuit B11. Dividing circuit B1
1 divides the clock signal CK3 to a lower frequency.
The first signal switching circuit K12 includes OR circuits OR1, OR
2. It is composed of an AND circuit AND1 and an inverter circuit IN1. One input terminal of the OR circuit OR1 is connected to the input terminal 11, and the output terminal is an AND circuit AND1.
Is connected to one of the input terminals. One input terminal of the OR circuit OR2 is connected to the output terminal of the frequency dividing circuit B11, and the other input terminal is connected to the output terminal of the CPU 10 and connected to the other input terminal of the OR circuit OR1 via the inverter circuit IN1. Have been. An output terminal of the OR circuit OR2 is connected to one input terminal of the AND circuit AND1.
The output terminal of the AND circuit AND1 is connected to the step-down circuit S11.
It is connected to the. Further, the input terminal 11 is connected to one input terminal of an AND circuit AND2 constituting a second signal switching circuit. The other input terminal of the AND circuit AND2 is connected to the output terminal of the CPU 10, and the output terminal is connected to the booster circuit S21.

In the above configuration, when the liquid crystal driving circuit R21 is in the operating state, the CPU 10 outputs the "1" level switching signal SW1. At this time, the first signal switching circuit K12 and the AND circuit AN as the second switching circuit
D2 is a clock signal CK3 according to the switching signal SW1.
Is supplied to the step-down circuit S11 and the step-up circuit S21. Therefore, the step-down circuit S11 and the step-up circuit S21
Is supplied with a clock signal of a high frequency, the load current of the crystal oscillation circuit R11 and the liquid crystal drive circuit R21 can be sufficiently supplied, and the voltage drop of the output power sources V1 and V2 can be suppressed low.

When the liquid crystal driving circuit R21 is in a stopped state, the CPU 10 outputs a "0" level switching signal SW1. At this time, the first signal switching circuit K12 selects the clock signal CK31 output from the frequency dividing circuit B11 according to the switching signal SW1, and supplies the clock signal CK31 to the step-down circuit S11. AND circuit AND2 as second switching circuit
Does not output a clock signal. Therefore, the booster circuit S21 is stopped, and a low-frequency clock signal is supplied to the step-down circuit S11. At this time, the liquid crystal driving circuit R21
And the load current flowing through the booster circuit S21 becomes “0”, so that the load current I _V1 of the step-down circuit S11 is
11, the drop of the output voltage V1 and the amount of noise are suppressed low, and the crystal oscillation circuit R11 can be operated stably. Moreover, since the operation of the booster circuit S21 is stopped and the step-down circuit S11 is operated at a low frequency, current consumption can be reduced.

FIG. 9 shows a third embodiment of the present invention. In the figure, the same parts as those in FIGS. 1 and 8 are denoted by the same reference numerals. This embodiment is different from the step-down circuit S in FIG.
And the step-up / down circuit S31
It is what it was. A signal switching circuit K31 is connected to an input terminal of the step-up / step-down circuit S31, the crystal oscillation circuit R11 is connected to a first output terminal, and a liquid crystal drive circuit R21 is connected to a second output terminal. I have. Further, a buck-boost capacitor C31 is connected to the buck-boost circuit S31. This elevating capacitor C31 combines the capacitors C11 and C21 shown in FIG. 8 into one and is used in a time-division manner.

FIG. 10 shows an example of the step-up / step-down circuit S31. The counter CNT1 divides the frequency of the output signal of the switching circuit K31, and outputs signals CT1 and CT as shown in FIG.
2. Output CT3. N between ground and power supply VDD
The current paths of the channel transistor N11 and the P-channel transistors P12, P13, P14 are connected in series. The signal CT1 is supplied to the gate of the transistor P13, and the signal CT1 is supplied to the gate of the transistor N11 via the inverter circuit IN31. The signal CT2 is connected to the gates of the transistors P12 and P14.
Is supplied. The step-down output voltage V ₁ is the transistor P
12 and P13 are output from each other. One electrode A3 of the raising / lowering capacitor C31 is connected to the transistors N11 and P3.
12, and the other electrode B3 is connected between the transistors P13 and P14. There is a P between the electrode A3 of the raising / lowering capacitor C31 and the power supply VDD.
The current path of the channel transistor P15 is connected, and one end of the current path of the P-channel transistor P16 is connected to the other electrode B3. The boosted output voltage V ₂ from the other end of the current path of the transistor P16 is output. The signal CT3 is supplied to the gates of the transistors P15 and P16.

In the step-up / step-down circuit S31 having the above-described configuration, the transistors N11, P12, P13, and P14 are controlled by signals CT1, CT2, and CT3 output from the counter CNT1, and the one electrode A3 and the other electrode B3 of the step-up / down capacitor C31 are connected. The supplied voltage is switched. That is, as shown in FIG. 11, the step-up / step-down circuit S31 holds the voltage when the transistors N11 and P13 are on and the voltage when the transistors P12 and P14 are on in the capacitor C12 for raising and lowering VDD / 2. The step-down voltage is output to V1, and transistors P15 and P16 are output.
Holds the voltage B3 during the ON period in the voltage holding capacitor C22, thereby outputting a boosted voltage of 3VDD / 2 to V2.

The output voltages V1, V of the step-up / step-down circuit S31
2 and the supplyable current are proportional to the frequency of the clock signal CK4 supplied to the step-up / step-down circuit S31. For this reason,
In response to the switching signal SW1, the signal switching circuit K31 switches the clock CK3 and the clock CK31 frequency-divided by the frequency dividing circuit B11 and supplies the clock CK31 to the step-up / step-down circuit S31. In the case of a stop, as in the first and second embodiments, it is possible to reduce power consumption while ensuring reliability. Note that the present invention is not limited to the above embodiment, and various modifications can be made without departing from the spirit of the invention.

[0049]

As described above, according to the present invention, it is possible to stably convert a power supply voltage to a predetermined voltage while suppressing an increase in operating current consumption, and to reduce noise. It is an object of the present invention to provide a highly reliable power supply voltage conversion circuit.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing a first embodiment of the present invention.

FIG. 2 is a configuration diagram showing an example of a conventional power supply voltage conversion circuit.

FIG. 3 is a circuit diagram showing an example of a step-down circuit shown in FIG. 2;

FIG. 4 is a circuit diagram illustrating an example of a booster circuit illustrated in FIG. 2;

FIG. 5 is a waveform chart for explaining the operation of the step-down circuit shown in FIG. 3;

FIG. 6 is a waveform chart for explaining the operation of the booster circuit shown in FIG. 4;

7 is a circuit diagram showing an example of the crystal oscillation circuit shown in FIG.

FIG. 8 is a configuration diagram showing a second embodiment of the present invention.

FIG. 9 is a configuration diagram showing a third embodiment of the present invention.

FIG. 10 is a circuit diagram showing an example of a step-up / step-down circuit shown in FIG. 9;

FIG. 11 is a waveform chart for explaining the operation of the step-up / step-down circuit shown in FIG. 10;

[Explanation of symbols]

10: CPU, MC: 1-chip microcomputer,
S11: step-down circuit, S21: step-up circuit, R11: crystal oscillator circuit, R21: liquid crystal drive circuit, G11, G21: first and second clock oscillators, K11, K21: first and second signal switching circuits, B11 ... Frequency divider circuit, 11 input terminal, CK3, CK4 clock signal, K12 first signal switching circuit, AND2 AND circuit (second signal switching circuit), S31 step-up / step-down circuit, K31 signal switching circuit , CNT1... Counter.

──────────────────────────────────────────────────続 き Continuation of front page (72) Inventor Hiroyuki Mogi 25-1, Ekimae Honcho, Kawasaki-ku, Kawasaki-shi, Kanagawa In-house Toshiba Microelectronics Corporation (56) References JP-A-4-222455 (JP, A) JP-A Heihei 6-62562 (JP, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) H02M 3/07

Claims (4)

(57) [Claims] A first clock signal generating means for generating a first clock signal; a second clock signal generating means for generating a second clock signal having a lower frequency than the first clock signal; Multiple switches whose conduction is controlled according to the level
Switching elements and the conduction of these switching elements.
The first power supply voltage and the second power supply voltage
The first power supply voltage converted from the power supply voltage
A third power supply voltage which is higher and lower than the second power supply voltage.
Having a step-down capacitor for storing, said step-down capacitor
A first voltage conversion means for supplying the third power supply voltage stored in the first power supply to a first load, and a plurality of switches which are controlled to be conductive according to the level of a clock signal.
Switching elements and the conduction of these switching elements.
Converted from the first to third power supply voltages in accordance with the communication state.
A fourth power supply voltage higher than the third power supply voltage.
Having a boosting capacitor for storing the boosting capacitor
A second voltage converting means for supplying the fourth power supply voltage stored in the second load to a second load of a type different from the first load; and The first clock signal generated by the clock generation means,
A signal for supplying to the second voltage converting means and supplying the second clock signal generated by the second clock generating means to the first and second voltage converting means when the second load is stopped. A power supply voltage conversion circuit, comprising: switching means for reducing power supply noise accompanying supply of a power supply voltage to the first and second loads and optimizing a current consumption according to the load. . 2. A frequency dividing means for dividing a first clock signal to generate a second clock signal having a lower frequency than the first clock signal, and a plurality of conduction control means for controlling conduction according to a level of the clock signal. S
Switching elements and the conduction of these switching elements.
The first power supply voltage and the second power supply voltage
The first power supply voltage converted from the power supply voltage
A third power supply voltage which is higher and lower than the second power supply voltage.
Having a step-down capacitor for storing, said step-down capacitor
A first voltage conversion means for supplying the third power supply voltage stored in the first power supply to a first load, and a plurality of switches which are controlled to be conductive according to the level of a clock signal.
Switching elements and the switching elements
Converted from the first to third power supply voltages in accordance with the communication state.
A fourth power supply voltage higher than the third power supply voltage.
Having a boosting capacitor for storing the boosting capacitor
A second voltage converting means for supplying the fourth power supply voltage stored in the second load to a second load of a type different from the first load; and A clock signal is supplied to the first and second voltage converting means, and when the second load is stopped, a second clock signal generated by the frequency dividing means is supplied to the first and second voltage converting means. Signal switching means for supplying power to the first and second loads, thereby reducing power supply noise and optimizing current consumption according to the load. Power supply voltage conversion circuit. 3. A frequency dividing means for dividing a first clock signal to generate a second clock signal having a lower frequency than the first clock signal, a frequency dividing circuit for dividing the clock signal, and a frequency dividing circuit. Circuit output
A plurality of switching elements whose conduction is controlled by a signal,
The first power supply depends on the conduction state of these switching elements.
Source voltage and a higher second power supply voltage
The second power supply voltage higher than the first power supply voltage.
A third power supply voltage lower than the first voltage and
Than the third power supply voltage converted from the power supply voltage
A lifting capacitor for storing a high fourth power supply voltage;
The third power supply voltage stored in the raising / lowering capacitor is stored in a first load, and the fourth power supply voltage stored in the raising / lowering capacitor is stored in a different type from the first load. A voltage converting means for supplying the second clock to the second load, supplying the first clock signal to the voltage converting means when the second load is operating, and supplying the second clock when the second load is stopped. Signal switching means for supplying a signal to the voltage conversion means, enabling reduction of power supply noise accompanying supply of power supply voltage to the first and second loads and optimization of current consumption according to the load. A power supply voltage conversion circuit, comprising: 4. The step-up / down capacitor comprises a step-down capacitor.
And a boost capacitor.
Power supply voltage converting circuit according to claim 3, characterized in that.