JP2006238315A - Method of measures and circuit against emi for electronic circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To attain spectrum diffusion of drive frequency of an electronic circuit by a simple method with no use of an SSCG, resulting in a reduced EMI (radiation noise). <P>SOLUTION: Voltage fluctuation inside an ASIC is increased by raising an impedance of a power supply supplied to the ASIC (integrated circuit) for a reduced radiation noise. The signal required to avoid voltage fluctuation among the control signals outputted from the ASIC is received by a logic gate provided outside the ASIC, to stabilize the power supply voltage which drives the gate. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a method and circuit for reducing EMI (radiated noise) from an electronic circuit board.

  Conventionally, as means for reducing EMI (radiated noise) from an electronic circuit board, there has been a method of using a spread spectrum clock generator (SSCG) as a system clock in order to reduce the dispersion by modulating the frequency of the electronic logic circuit. In addition, when a plurality of functional blocks are provided in one ASIC (integrated circuit), it may be necessary to use an SSCG-off clock for a block that requires high frequency accuracy. Generally, an on clock and an SSCG off clock are used separately for each block.

  Also, because there are blocks that are vulnerable to ripple noise and voltage fluctuations, and conversely, blocks that are sources of ripple noise and voltage fluctuations, a separate power supply terminal is provided for each functional block. The structure which supplies is common.

As another conventional example, Patent Literature 1 and Patent Literature 2 can be cited.
JP 2000-049429 A Japanese Patent Laid-Open No. 2003-332706

  However, in the above-described prior art, SSCG (spread spectrum clock generator) is used as a system clock, which causes an increase in cost. In addition, when a plurality of functional blocks are provided in one ASIC (integrated circuit), it is necessary to use an SSCG-off clock for a block that requires high frequency accuracy. Therefore, an SSCG-on clock is used inside the ASIC. And the SSCG off clock must be used separately for each block, and the circuit configuration is complicated.

  Also, because there are blocks that are vulnerable to ripple noise and voltage fluctuations, and conversely, blocks that are sources of ripple noise and voltage fluctuations, a separate power supply terminal is provided for each functional block. There was a need to supply.

  In order to solve the above-described problems, the present invention provides an electronic circuit board on which an ASIC (integrated circuit) is mounted, by supplying a power source having high impedance to a power terminal of the ASIC, thereby providing a power line and logic circuit signal inside the ASIC. Generate fluctuations in the voltage, decrease the stability of the operating frequency due to voltage fluctuations in the power line and logic circuit signal inside the ASIC, increase the jitter component of the circuit operating frequency, and lengthen the signal state transition time, Accordingly, one of the features is to reduce EMI (radiated noise) from the ASIC and the electronic circuit board.

  In order to increase the voltage accuracy of the signal output from the ASIC (integrated circuit) even if the voltage fluctuation inside the ASIC (integrated circuit) is large, a logic gate element is provided outside the ASIC, and the signal output from the ASIC is Another feature is that the voltage variation value of the power supply for driving the ASIC is made smaller than the voltage variation value of the power supply for driving the ASIC.

  According to the present invention, spectrum spreading of the driving frequency of an electronic circuit can be achieved by a simple method without using SSCG, and as a result, EMI (radiated noise) can be reduced. Further, even if the drive power supply terminals for each functional block cannot be separated inside the ASIC, the power supply voltage can be selectively stabilized only for necessary signals by adding a logic gate element to the outside.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a block diagram of an electronic circuit of an image forming apparatus showing an example of an embodiment of the present invention. In FIG. 1, reference numeral 10 denotes a system chip, which includes functional blocks such as a CPU core unit, a USB-I / F unit, a memory control unit, and an I / O unit. Each functional block includes power supply terminals Vdd1, Vdd2, Vdd3, and Vdd4. Vdd1 is a power supply terminal of the CPU core section, and is usually driven at a low voltage of 1.5V. Further, since the operation of the CPU core section is fast and the current consumption is large, Vdd1 needs a certain low impedance and supply capability. Therefore, normally, the capacity of the bypass capacitor connected to Vdd1 is 0.1 uF or more. Moreover, since it becomes a generation source of harmonic noise, it is necessary to select FBC inserted in series after examination. Vdd2 is a power supply terminal of the USB-I / F unit, and it is necessary to pay close attention to the capacity and impedance of the connected bypass capacitor and the pattern of the substrate. In addition, since it becomes a generation source of harmonic noise, careful attention is also required for selection of FBC inserted in series. Vdd3 is a power supply terminal of the memory control unit, and is often 3.3V when an SDRAM is connected. The memory control unit also operates at high speed, consumes a large amount of current, and is a source of radiation noise. Usually, the capacity of the bypass capacitor to be connected is 0.1 uF or more. In addition, since it becomes a generation source of harmonic noise, careful attention is also required for selection of FBC inserted in series. Vdd4 is a power supply terminal of the I / O unit, and the power supply voltage is often 3.3V. Usually, it operates at a lower speed than the CPU core unit and memory control unit, and therefore consumes less current. However, there may be an I / O signal that requires high voltage accuracy.

  Here, in order to increase the impedance of the power supply, which is a feature of the present invention, the capacitance of 0.1 μF or less, which is smaller than the normally required capacitance, is selected for the bypass capacitors C1, C2, C3, C4. As a result, when each power supply terminal voltage is measured, a ripple of about 40 mV to 100 mV is observed. This ripple causes the voltage fluctuation without the supply side following the fluctuation of the consumption current due to the internal operation. The occurrence of voltage fluctuation means that the state transition time becomes longer in the internal logic operation, the rise and fall are dull, the harmonic components are reduced, and the radiation noise is reduced. Further, the spread of the operating frequency due to the phase delay also contributes to the reduction of radiation noise. However, fluctuations in the internal logic operating voltage lead to a reduction in the margin of AC characteristics, and also have the disadvantage of being weak against external static electricity, AC line noise, and external noise such as lightning surges. The capacity and the resulting voltage fluctuation must be carefully determined. Since the properties of electronic devices are temperature dependent, it is necessary to consider temperature changes and individual differences between devices. Note that the voltage fluctuation inside the device is larger than the measured voltage fluctuation at the power supply terminal.

  A logic gate element 20 is provided outside the system chip and is inserted with respect to a control signal output from the I / O unit. In the first embodiment, one side is fixed to L with a simple OR gate. In the present invention, since the insertion of the logic gate element is not for the purpose of increasing the driving capability but for the purpose of improving the signal voltage accuracy, the driving capability higher than the driving capability of the output buffer of the ASIC is required. There is no guarantee that a certain logic gate element is used.

  In the first embodiment, as an example, a logic gate element is inserted for the CCD control signal. Vdd5 is a power supply terminal of the logic gate element, and the capacitance of the bypass capacitor C5 connected between Vdd5 and GND is increased from 1 uF to 10 uF in order to stabilize the voltage of the output signal. Alternatively, a power source may be generated by providing a regulator independently for Vdd5. The CCD control signal is a digital signal, but is a signal that is greatly affected by phase fluctuations and voltage fluctuations. The CCD control signal is drawn as long as about 500 mm in the apparatus configuration of the first embodiment, and the signal is considerably dull due to the large capacitance component of the cable.

  Reference numeral 30 denotes a CCD unit. FIG. 2 is a diagram showing the effect of stabilizing the voltage of the CCD control signal. Reference numeral 201 in FIG. 2 denotes a waveform before the output buffer inside the output terminal of the ASIC (10) of the clmp signal which is one of the CCD control signals. The output of the ASIC is a square wave, but there is a voltage fluctuation of about 20 mV to 100 mV.

  Reference numeral 202 denotes a waveform of the input terminal of the CCD substrate when the logic gate element (20) is not provided. The output of the ASIC is a square wave, but the connecting cable to the CCD substrate is about 500 mm long and has a large capacitance component, so the rise and fall are considerably slow. The voltage drop of the output signal of the ASIC 201 becomes the voltage drop of the input terminal position of the CCD substrate 202 as it is. Reference numeral 203 denotes a waveform after passing through the buffer on the CCD substrate, and it can be seen that a voltage drop at the input terminal of the CCD substrate at 202 directly becomes a delay of the signal after passing through the buffer on the CCD substrate at 203.

  Reference numeral 204 in FIG. 2 represents a waveform image when a logic gate element (20) is provided at the subsequent stage of the output terminal of the ASIC (10) of the clmp signal which is one of the CCD control signals. The output of the ASIC is a square wave, and the voltage fluctuation of about 20 mV to 100 mV is eliminated by the logic gate element (20). Since the connection cable between the CCD substrate and the capacitance substrate is as long as about 500 mm and has a large capacitance component, the rise and fall are considerably slow. Reference numeral 205 denotes a waveform of the input terminal of the CCD substrate. Since there is no voltage drop of the output signal of the logic gate element (20) 204, a voltage drop at the input terminal position of the CCD substrate 205 does not occur. Reference numeral 206 denotes a waveform after passing through the buffer on the CCD substrate. Since there is no voltage drop at the input terminal position of the 205 CCD substrate, no signal delay occurs after passing through the buffer on the 206 CCD substrate.

  FIG. 3 is a diagram showing the voltage at the power supply terminal of the ASIC according to the first embodiment of the present invention, and 301 is a diagram showing voltage fluctuations at the power supply terminals Vdd1 to Vdd4. It can be seen that voltage fluctuations occur in a plurality of cycles according to the operation inside the ASIC. The voltage fluctuation range is about 20 mV to 100 mV. Reference numeral 302 is a diagram showing the voltage at the power supply terminal of the conventional example, and voltage fluctuations with periodicity are prevented from occurring, so that high-frequency random noise or a ripple of the power supply itself is somewhat observed. Reference numeral 302 denotes a voltage variation of Vdd5 which is a power source supplied to the logic gate element 20 according to the first embodiment of the present invention. This shows that the fluctuation of the power supply voltage of the logic gate element is smaller than the fluctuation of the power supply voltage supplied to the ASIC, which is the feature of the present case.

1 is a block diagram of an electronic circuit of an image forming apparatus according to an embodiment of the present invention. It is a figure which shows the I / O control signal waveform at the time of not providing the logic gate element of this invention Example, and the I / O control signal waveform at the time of providing a logic gate element. It is a figure which shows the voltage waveform of the power supply terminal of ASIC of this invention, and a logic gate element.

Explanation of symbols

10 ASIC (integrated circuit)
20 logic gate element 30 CCD unit

Claims (6)

In an electronic circuit board on which an ASIC (integrated circuit) is mounted, by supplying power with high impedance to the power supply terminal of the ASIC, the voltage of the power line inside the ASIC and the logic circuit signal is changed,
By reducing the stability of the operating frequency due to voltage fluctuations in the power line and logic circuit signal inside the ASIC, increasing the jitter component of the ASIC internal circuit operating frequency, and slowing the rise and fall of the ASIC internal circuit operation,
EMI countermeasure method and circuit characterized by reducing EMI (radiated noise) from ASIC and electronic circuit board.   In an electronic circuit board on which an ASIC (integrated circuit) having a plurality of power supply terminals is mounted, by supplying power with a different impedance for each power supply terminal of the ASIC, fluctuations in power supply voltage that differ for each circuit block inside the ASIC The EMI countermeasure method and circuit according to claim 1, wherein the EMI countermeasure method is generated.   In an electronic circuit board on which an ASIC (integrated circuit) is mounted, in order to increase the impedance of the power supply line supplied to the power supply terminal of the ASIC, an element having DC resistance or AC resistance is inserted in series with the power supply line, and the power supply line 2. The EMI countermeasure method and circuit according to claim 1, wherein a capacitance of a capacitor inserted between the first and the second GND is set smaller than a value necessary for stabilizing the power supply voltage.   In order to increase the voltage accuracy of a signal output from an ASIC (integrated circuit), a logic gate element is provided outside the ASIC, and a signal output from the ASIC is received once by the logic gate and then output. 2. The EMI countermeasure method and circuit according to claim 1, wherein the voltage fluctuation value of the power source for driving the gate is made smaller than the voltage fluctuation value of the power source for driving the ASIC.   2. The EMI countermeasure method and circuit according to claim 1, wherein a voltage fluctuation value generated in a power supply line and a logic circuit signal in the ASIC is about 10 mV to 200 mV.   2. The EMI countermeasure method and circuit according to claim 1, wherein the deviation of the circuit operating frequency generated in the power line and logic circuit signal in the ASIC is about several ppm to several hundred ppm.

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