JPH09266223A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH09266223A JPH09266223A JP8073694A JP7369496A JPH09266223A JP H09266223 A JPH09266223 A JP H09266223A JP 8073694 A JP8073694 A JP 8073694A JP 7369496 A JP7369496 A JP 7369496A JP H09266223 A JPH09266223 A JP H09266223A
- Authority
- JP
- Japan
- Prior art keywords
- wire
- semiconductor device
- semiconductor chip
- wires
- resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05553—Shape in top view being rectangular
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は半導体装置に関し、
特にワイヤショート防止を確保した半導体装置に関する
ものである。The present invention relates to a semiconductor device,
In particular, the present invention relates to a semiconductor device ensuring wire short-circuit prevention.
【0002】[0002]
【従来の技術】従来の樹脂封止型半導体装置は周知のよ
うに、集積回路等が形成された半導体チップをリードフ
レームのダイパッドに接着剤等により取付け、半導体チ
ップの各ボンディングパッドとこれに対応するリードフ
レームのインナリードとをワイヤで接続し、ついで、半
導体チップとその周辺のインナリードとを合成樹脂によ
り一体的に成型し封止したのち、成型されたパッケージ
の外側において、各リードをリードフレームから切り離
し、必要に応じて各リードを適宜折り曲げることにより
製造している。2. Description of the Related Art As is well known, a conventional resin-encapsulated semiconductor device has a semiconductor chip on which an integrated circuit or the like is formed and is attached to a die pad of a lead frame with an adhesive or the like, and each bonding pad of the semiconductor chip and corresponding After connecting the inner lead of the lead frame with a wire and then integrally molding and sealing the semiconductor chip and the inner lead around it with a synthetic resin, lead each lead on the outside of the molded package. It is manufactured by separating it from the frame and bending each lead as needed.
【0003】図5(a),(b)は従来のリードフレー
ムのダイパッドに半導体チップを搭載した半導体装置の
部分拡大斜示図である。従来の半導体装置は、図5
(a)に示すように、半導体チップ5とその周辺のイン
ナリード3とを一定のループ高さのワイヤ4にて接続す
ることによって半導体装置を構成するか、あるいは、図
5(b)に示すように、半導体チップ5とその周辺のイ
ンナリード3とを一本おきに交互にループ高を異にする
ことにより半導体装置を構成していた。上記のようにし
て多数のインナリード3とワイヤ4にて接続された半導
体チップ5は、インナリード3の一部を残して、インナ
リード3、ダイパッド2およびワイヤ4を合成樹脂によ
って樹脂封止され、樹脂封止されたパッケージ部のリー
ドを切断したのち折り曲げ加工をすることで外部端子と
して半導体装置を組立ていた。5A and 5B are partially enlarged perspective views of a semiconductor device in which a semiconductor chip is mounted on a die pad of a conventional lead frame. The conventional semiconductor device is shown in FIG.
As shown in FIG. 5A, the semiconductor device is configured by connecting the semiconductor chip 5 and the inner leads 3 around the semiconductor chip with wires 4 having a constant loop height, or as shown in FIG. As described above, the semiconductor device is configured by alternately making the semiconductor chip 5 and the inner leads 3 around the semiconductor chip 5 different in loop height. In the semiconductor chip 5 connected to the many inner leads 3 with the wires 4 as described above, the inner leads 3, the die pad 2 and the wires 4 are resin-sealed with a synthetic resin, leaving a part of the inner leads 3. The semiconductor device is assembled as an external terminal by cutting the leads of the resin-sealed package portion and then bending the leads.
【0004】[0004]
【発明が解決しようとする課題】第1の問題点は、従来
の樹脂封止型半導体装置において、半導体チップとイン
ナリードとを接続するワイヤが樹脂封止の際流される
が、各ワイヤの封止による流れ量が異なるため、隣接ワ
イヤ間でショートを誘発することである。その理由は、
半導体チップのチップパッドとインナリードとの先端の
距離が構造上不均一である為、長尺ワイヤ程樹脂封止の
際合成樹脂により流され易い構造であるためである。A first problem is that in the conventional resin-sealed semiconductor device, the wire connecting the semiconductor chip and the inner lead is washed away when the resin is sealed, but each wire is sealed. This is to induce a short circuit between adjacent wires because the flow rate due to the stop is different. The reason is,
This is because the distance between the tip of the chip pad of the semiconductor chip and the inner lead is structurally non-uniform, so that the longer the wire, the more easily the synthetic resin will flow when the resin is sealed.
【0005】第2の問題点は、従来の樹脂封止型半導体
装置において、ワイヤのループ高さが一定であるため、
半導体チップとインナリードとを接続するワイヤの長さ
が長尺になる程ボンディング後のワイヤにたるみが生じ
変形し易くかつ樹脂封止の際封止樹脂によりワイヤが流
され易く隣接ワイヤ間でショートを誘発することであ
る。その理由は、半導体チップとインナリードとを接続
するワイヤの長さが長くなる程樹脂封止の際に合成樹脂
によって受ける流動抵抗面積が大きくなり、かつワイヤ
の張力が低いため、樹脂封止の際のワイヤ流れ量が大き
くなるとともにワイヤ長によりワイヤの流れ量が不均一
となり隣接ワイヤ間の流れ量が生じショートを誘発する
ためである。The second problem is that in the conventional resin-sealed semiconductor device, the wire loop height is constant,
As the length of the wire connecting the semiconductor chip and the inner lead becomes longer, the wire after bonding is more likely to be slackened and deformed, and the resin is easily flown by the sealing resin during resin sealing to cause a short between adjacent wires. Is to induce. The reason is that as the length of the wire connecting the semiconductor chip and the inner lead increases, the flow resistance area received by the synthetic resin during resin sealing increases, and the wire tension is low, so This is because the amount of wire flow at that time increases and the amount of wire flow becomes non-uniform due to the wire length, causing a flow amount between adjacent wires and inducing a short circuit.
【0006】本発明の樹脂封止型半導体装置は、半導体
装置組立時における半導体チップとリードフレームのイ
ンナリード先端とをワイヤにてボンディングした際にワ
イヤに張力をもたせ、ワイヤのたるみおよび変形を防止
するとともに樹脂封止時の合成樹脂の注入の際のワイヤ
の流れを防止するか、あるいは、ワイヤの流れ量を一定
量に制御することにより、樹脂封止後の隣接ワイヤ間の
ショートを防止することを目的とする。In the resin-sealed semiconductor device of the present invention, when the semiconductor chip and the inner lead tip of the lead frame are bonded with a wire at the time of assembling the semiconductor device, a tension is applied to the wire to prevent the wire from sagging or deforming. In addition, by preventing the flow of the wire when injecting the synthetic resin at the time of resin sealing, or by controlling the wire flow amount to a constant amount, the short circuit between the adjacent wires after resin sealing is prevented. The purpose is to
【0007】[0007]
【課題を解決するための手段】本発明は、リードフレー
ムのダイパッド上に搭載された半導体チップの複数のボ
ンディングパッドと前記リードフレームの複数のインナ
リードとをそれぞれワイヤで接続し、これらを合成樹脂
等で封止してなる半導体装置において、前記各ワイヤの
ループ高さが前記各ワイヤ長のさに応じて、または前記
半導体チップの中央部の前記ボンディングパッドからの
周辺部の前記ボンディングパッドに向けて階段状に異っ
ていることを特徴とする。According to the present invention, a plurality of bonding pads of a semiconductor chip mounted on a die pad of a lead frame and a plurality of inner leads of the lead frame are connected by wires, respectively, and these are made of synthetic resin. In a semiconductor device formed by sealing the wires with each other, the loop height of each wire is directed toward the bonding pad in the peripheral portion from the bonding pad in the central portion of the semiconductor chip depending on the length of each wire. It is characterized in that it is different in a staircase.
【0008】[0008]
【作用】本発明によれば、半導体チップとリードフレー
ムのインナリード間を接続するワイヤにおいて、ワイヤ
の長さに応じてワイヤループ高さを階段状に異にするこ
とで実質のワイヤ長を均一化することができ、かつワイ
ヤ自身の張力を各ワイヤ毎に制御することが可能とな
る。このため、樹脂封止時に合成樹脂注入の際の樹脂の
流動抵抗により生ずるワイヤ流れに対し、そのワイヤ流
れを防止するかまたは一定のワイヤ流れ量に制御するこ
とが可能となる。例えば、半導体チップのボンディグパ
ッドとリードフレームのインナリード間の距離が長く長
尺化するワイヤについては、一般にワイヤ長が長くかつ
ワイヤの張力が低いため、樹脂封止の際のワイヤ流れ量
は大きくなるため、上記方法により半導体装置を構成す
ることで樹脂封止の際のワイヤ流れ量を制御することが
できる。According to the present invention, in the wire connecting between the semiconductor chip and the inner lead of the lead frame, the wire loop height is stepwise changed according to the length of the wire to make the actual wire length uniform. The tension of the wire itself can be controlled for each wire. For this reason, it is possible to prevent the wire flow from occurring due to the flow resistance of the resin when the synthetic resin is injected during the resin sealing, or to control the wire flow to a constant amount. For example, for a wire with a long distance between the bonding pad of the semiconductor chip and the inner lead of the lead frame, the wire flow amount during resin sealing is generally long because the wire length is long and the wire tension is low. Therefore, the amount of wire flow during resin encapsulation can be controlled by configuring the semiconductor device by the above method.
【0009】また、一般に半導体チップとリードフレー
ムのインナリード間を接続した複数のワイヤにおいて
は、半導体チップの中央から周辺に向かうワイヤである
程、半導体チップのボンディングパッドとリードフレー
ムのインナリード間の距離が長くワイヤが長尺化するの
で、樹脂封止の際の樹脂流動抵抗もまた半導体チップの
中央から周辺に向かう程大きくなる傾向にあるため、上
記方法により半導体装置を構成することで樹脂封止の際
のワイヤ流れ量を制御することができる。[0009] Generally, in a plurality of wires connecting between a semiconductor chip and inner leads of a lead frame, the more the wire goes from the center of the semiconductor chip to the periphery, the more between the bonding pad of the semiconductor chip and the inner lead of the lead frame. Since the distance is long and the wire is long, the resin flow resistance during resin encapsulation also tends to increase from the center of the semiconductor chip toward the periphery. The amount of wire flow at the time of stopping can be controlled.
【0010】[0010]
【発明の実施の形態】次に本発明の実施の形態について
図面を参照して説明する。Embodiments of the present invention will now be described with reference to the drawings.
【0011】図1(a),(b)は本発明の第1の実施
の形態の半導体装置の平面図及びその側面図、図2
(a),(b)は図1のボンディングワイヤの部分拡大
斜視図である。本発明の第1の実施の形態の半導体装置
は、図1(a),(b)及び図2(a),(b)に示す
ように、半導体チップ5に入出力される電気信号は、ボ
ンディングパッド6よりワイヤ4,インナリード3を介
して外部端子へ出力される。ここで、半導体チップ5と
リードフレーム1のインナリード3とをワイヤ4にて接
続するが、複数のワイヤ4のうちの長尺となるワイヤ4
を選択的にループ高さを低くすることで実質的なワイヤ
長を容易に均一化することができ、かつ長尺となるワイ
ヤ4の張力を高め、ボンディング後のワイヤ4の変形及
びその後工程である樹脂封止工程での合成樹脂注入時の
流動抵抗によるワイヤ4の流れを防止またはワイヤ4の
流れ量を複数のワイヤ4間で均一化することができ、ボ
ンディング工程ならびに樹脂封止工程での半導体装置及
びその製造方法を安定化することができる。1A and 1B are a plan view and a side view of the semiconductor device according to the first embodiment of the present invention, and FIG.
(A), (b) is a partially expanded perspective view of the bonding wire of FIG. In the semiconductor device according to the first embodiment of the present invention, as shown in FIGS. 1A and 1B and FIGS. 2A and 2B, an electric signal input / output to / from the semiconductor chip 5 is It is output from the bonding pad 6 to the external terminal via the wire 4 and the inner lead 3. Here, the semiconductor chip 5 and the inner lead 3 of the lead frame 1 are connected by a wire 4, but a long wire 4 of the plurality of wires 4 is connected.
By selectively lowering the loop height, the substantial wire length can be easily made uniform, and the tension of the long wire 4 is increased, so that the deformation of the wire 4 after bonding and the subsequent process can be performed. It is possible to prevent the flow of the wires 4 due to the flow resistance at the time of injecting the synthetic resin in a certain resin sealing process or to make the flow amount of the wires 4 uniform among the plurality of wires 4, and thus, in the bonding process and the resin sealing process. The semiconductor device and the manufacturing method thereof can be stabilized.
【0012】図3(a),(b)は樹脂封止後のワイヤ
流れ量を示す斜視図及びワイヤのループ高さとワイヤ張
力、ワイヤ長さとワイヤ流れ量の関係を示すグラフであ
る。図3(a),(b)に示すように、本発明の第1の
実施の形態の半導体装置は、ワイヤ4のループ高さが高
くなる程ワイヤ張力が低下し、かつワイヤ流れ量は大き
くなる傾向があり、また、ワイヤ長が長くなる程同様
に、ワイヤ張力は低下し、かつワイヤ流れ量は大きくな
る傾向にある関係を利用して構成されたものである。3A and 3B are a perspective view showing a wire flow amount after resin sealing and a graph showing a relation between a wire loop height and a wire tension and a wire length and a wire flow amount. As shown in FIGS. 3A and 3B, in the semiconductor device according to the first embodiment of the present invention, the higher the loop height of the wire 4, the lower the wire tension and the larger the wire flow amount. In addition, as the wire length increases, the wire tension tends to decrease and the wire flow amount tends to increase.
【0013】図4(a)及び(b),(c)は本発明の
第2の実施の形態の半導体装置の側面図及びその斜視図
である。本発明の第2の実施の形態の半導体装置は、図
4(a),(b)に示すように、チップ5中央から周辺
に向うワイヤ4である程ワイヤ長は長くなるが樹脂の流
動抵抗に応じてワイヤ4のループ高さをチップ5中央か
ら周辺に向けて階段的に低くする構造、もしくは、図4
(a),(c)に示すように、チップ5中央部近傍であ
ってもリードフレーム1の構造上ワイヤ長が長くなる部
分について、ワイヤ4のループ高さを階段的に低くする
構造の半導体装置を提供することで、半導体装置組立時
のボンディング工程でのワイヤ4の変形および樹脂封止
工程でのワイヤ流れの防止もしくは一定の変形量に制御
することが可能となる。4A, 4B, and 4C are a side view and a perspective view of a semiconductor device according to a second embodiment of the present invention. In the semiconductor device according to the second embodiment of the present invention, as shown in FIGS. 4A and 4B, as the wire 4 extends from the center of the chip 5 to the periphery, the wire length becomes longer, but the flow resistance of the resin is increased. According to the structure, the loop height of the wire 4 is lowered stepwise from the center of the chip 5 to the periphery, or FIG.
As shown in (a) and (c), a semiconductor having a structure in which the loop height of the wire 4 is stepwise lowered in a portion where the wire length is long due to the structure of the lead frame 1 even near the central portion of the chip 5. By providing the device, it is possible to prevent the wire 4 from being deformed in the bonding process during the semiconductor device assembly and to prevent the wire from flowing in the resin sealing process, or to control the deformation amount to a certain amount.
【0014】[0014]
【発明の効果】第1の効果は、構造上、長尺になるワイ
ヤについてボンディング時のワイヤ変形および樹脂封止
時のワイヤ流れを防止するかもしくは一定のワイヤ流れ
量に制御することができることである。その理由は、構
造上長尺になるワイヤについて、選択的に階段状にルー
プ高さを低くすることで、実質ワイヤ長を均一化するこ
とができ、かつワイヤに張力を持たせることができるた
めボンディング時のワイヤのたるみによる変形、つづい
て樹脂封止時のワイヤ流れを制御することができるため
である。The first effect is that it is possible to prevent wire deformation at the time of bonding and wire flow at the time of resin encapsulation with respect to a wire having a long structure, or to control the wire flow amount to a constant amount. is there. The reason is that for a wire that is structurally long, the loop height can be made uniform and the tension can be given to the wire by selectively lowering the loop height stepwise. This is because it is possible to control the deformation due to the slack of the wire at the time of bonding, and subsequently the wire flow at the time of resin sealing.
【0015】第2の効果は、半導体チップ中央から周辺
に向かうワイヤである程、構造上樹脂封止時の合成樹脂
の注入に対する流動抵抗が高いが、この樹脂の流動抵抗
に応じ耐変形性の高いワイヤ構造を提供できることであ
る。その理由は、半導体チップ中央から周辺に向かって
ワイヤのループ高さを階段的に低くすることで、ワイヤ
に張力をもたせ、かつ実質ワイヤ長もより均一化するこ
とがてきるため、樹脂封止時のワイヤ流れを防止するか
もしくはワイヤ流れ量を均一化することができるためで
ある。The second effect is that the wire extending from the center of the semiconductor chip to the periphery has a higher flow resistance to the injection of the synthetic resin at the time of resin encapsulation due to the structure, but the deformation resistance depends on the flow resistance of the resin. It is possible to provide a high wire structure. The reason is that by lowering the loop height of the wire stepwise from the center of the semiconductor chip toward the periphery, tension can be applied to the wire and the wire length can be made more uniform. This is because the wire flow can be prevented or the wire flow amount can be made uniform.
【図1】(a),(b)は本発明の第1の実施の形態の
半導体装置の平面図及びその側面図である。1A and 1B are a plan view and a side view of a semiconductor device according to a first embodiment of the present invention.
【図2】(a),(b)は図1のボンディングワイヤの
部分拡大斜視図である。2 (a) and 2 (b) are partially enlarged perspective views of the bonding wire of FIG.
【図3】(a),(b)は樹脂封止後のワイヤ流れ量を
示す斜視図及びワイヤのループ高さとワイヤ張力,ワイ
ヤ長さワイヤ流れ量の関係を示すグラフである。3A and 3B are a perspective view showing a wire flow amount after resin sealing and a graph showing a relationship between a wire loop height, a wire tension, and a wire length wire flow amount.
【図4】(a)及び(b),(c)は本発明の第2の実
施の形態の半導体装置の側面図及び斜視図である。4 (a), (b), and (c) are a side view and a perspective view of a semiconductor device according to a second embodiment of the present invention.
【図5】(a),(b)は従来の半導体装置のボンディ
ングワイヤの一例及び他の例を示す斜視図である。5A and 5B are perspective views showing an example and another example of a bonding wire of a conventional semiconductor device.
1 リードフレーム 2 ダイパッド 3 インナリード 4 ワイヤ 5 半導体チップ 6 ボンディングパッド 7 ワイヤ流れ量 1 lead frame 2 die pad 3 inner lead 4 wire 5 semiconductor chip 6 bonding pad 7 wire flow rate
Claims (3)
れた半導体チップの複数のボンディングパッドと前記リ
ードフレームの複数のインナリードとをそれぞれワイヤ
で接続し、これらを合成樹脂等で封止してなる半導体装
置において、前記各ワイヤのループ高さが階段状に異る
ことを特徴とする半導体装置。1. A semiconductor in which a plurality of bonding pads of a semiconductor chip mounted on a die pad of a lead frame and a plurality of inner leads of the lead frame are respectively connected by wires and these are sealed with a synthetic resin or the like. The semiconductor device is characterized in that the loop height of each of the wires is different stepwise.
の長さに応じて階段状に異っていることを特徴とする請
求項1記載の半導体装置。2. The semiconductor device according to claim 1, wherein the loop height of each wire differs stepwise according to the length of the wire.
プの中央部のボンディングパッドからの周辺部の前記ボ
ンディングパッドに向けて階段状に異っていることを特
徴とする請求項1記載の半導体載置。3. The semiconductor according to claim 1, wherein the loop height of each wire is different from the central bonding pad of the semiconductor chip toward the peripheral bonding pad in a stepwise manner. Placement.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8073694A JPH09266223A (en) | 1996-03-28 | 1996-03-28 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8073694A JPH09266223A (en) | 1996-03-28 | 1996-03-28 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH09266223A true JPH09266223A (en) | 1997-10-07 |
Family
ID=13525591
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8073694A Pending JPH09266223A (en) | 1996-03-28 | 1996-03-28 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH09266223A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008166699A (en) * | 2006-12-04 | 2008-07-17 | Asmo Co Ltd | Resin encapsulated semiconductor device |
US7407270B2 (en) | 2002-03-18 | 2008-08-05 | Seiko Epson Corporation | Liquid jet head and liquid jet apparatus |
CN104103534A (en) * | 2013-04-02 | 2014-10-15 | 瑞萨电子株式会社 | Semiconductor device manufacturing method and semiconductor device |
CN110649004A (en) * | 2018-06-26 | 2020-01-03 | 三菱电机株式会社 | Power module and power conversion device |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0256942A (en) * | 1988-08-23 | 1990-02-26 | Fuji Xerox Co Ltd | Semiconductor device |
JPH02210856A (en) * | 1989-02-10 | 1990-08-22 | Fujitsu Ltd | Semiconductor device |
JPH04107936A (en) * | 1990-08-29 | 1992-04-09 | Fujitsu Miyagi Electron:Kk | Semiconductor device |
JPH08139125A (en) * | 1994-11-11 | 1996-05-31 | Yamaha Corp | Semiconductor device |
JP3112936B2 (en) * | 1990-04-06 | 2000-11-27 | アンステイテユ・ナシオナル・ドウ・ラ・サンテ・エ・ドウ・ラ・ルシエルシユ・メデイカル | Polypeptides having dopamine receptor activity, nucleic acids encoding these polypeptides and the use of these polypeptides to screen for substances active against these polypeptides |
-
1996
- 1996-03-28 JP JP8073694A patent/JPH09266223A/en active Pending
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0256942A (en) * | 1988-08-23 | 1990-02-26 | Fuji Xerox Co Ltd | Semiconductor device |
JPH02210856A (en) * | 1989-02-10 | 1990-08-22 | Fujitsu Ltd | Semiconductor device |
JP3112936B2 (en) * | 1990-04-06 | 2000-11-27 | アンステイテユ・ナシオナル・ドウ・ラ・サンテ・エ・ドウ・ラ・ルシエルシユ・メデイカル | Polypeptides having dopamine receptor activity, nucleic acids encoding these polypeptides and the use of these polypeptides to screen for substances active against these polypeptides |
JPH04107936A (en) * | 1990-08-29 | 1992-04-09 | Fujitsu Miyagi Electron:Kk | Semiconductor device |
JPH08139125A (en) * | 1994-11-11 | 1996-05-31 | Yamaha Corp | Semiconductor device |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7407270B2 (en) | 2002-03-18 | 2008-08-05 | Seiko Epson Corporation | Liquid jet head and liquid jet apparatus |
JP2008166699A (en) * | 2006-12-04 | 2008-07-17 | Asmo Co Ltd | Resin encapsulated semiconductor device |
CN104103534A (en) * | 2013-04-02 | 2014-10-15 | 瑞萨电子株式会社 | Semiconductor device manufacturing method and semiconductor device |
CN110649004A (en) * | 2018-06-26 | 2020-01-03 | 三菱电机株式会社 | Power module and power conversion device |
JP2020004784A (en) * | 2018-06-26 | 2020-01-09 | 三菱電機株式会社 | Power module and power converter |
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