JPH09260601A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent an increase in the number of manufacturing steps or a reduction in the manufacturing yield by a method, wherein there is provided an etching stop pattern which is larger than a redundancy pattern window corresponding to a redundancy pattern and which maintains accurately the thickness of an insulation film covering the redundancy pattern so as to be cut by fusing. SOLUTION: There are formed an element pattern 2, a redundancy pattern 3, an insulation film 4, an element pattern 5 and an etching stop pattern 5A on an underlayer insulation film 1. The etching stop pattern 5A is larger than a redundancy pattern window 13R, and a thickness of the insulation film 4 covering the redundancy pattern 3 is kept accurately, so as to be cut by fusing. Next, a first layer metal layer, an insulation film 9 or the like is formed and a second layer metal layer, a cover film 13 or the like is formed by deposition etc. Next, the redundancy pattern 13R is formed by etching. The etching is automatically stopped by the etching stop pattern 5A. Further, when fail occurs, the insulation film 4 and the redundancy pattern 3 are cut by fusing by applying a laser beam.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to improvement of a semiconductor integrated circuit device having a redundant circuit for repairing an electrically defective circuit.

Generally, in a semiconductor integrated circuit device,
An extra circuit, that is, a redundant circuit is built in anticipation of a defective circuit, and when a defective circuit occurs, switching to a normal circuit in the redundant circuit is performed.

In recent years, the structure of the semiconductor integrated circuit device has changed, for example, the multi-layered structure is naturally adopted. Therefore, the structure for surely performing the switching for activating the redundant circuit is required. Where it is needed,
According to the present invention, a means therefor is provided.

[0004]

2. Description of the Related Art In a semiconductor integrated circuit device, in order to activate a redundant circuit, a fuse portion in a redundant pattern is electrically cut or a laser beam is cut. Is done.

Normally, the redundant pattern in the redundant circuit is formed in the same layer as the element pattern, so that it is covered with a thick insulating film, and the multilayer wiring is adopted in the semiconductor integrated circuit device. If so, the insulating film surely becomes a plurality of layers.

Therefore, when the redundant circuit is activated, the insulating film on the redundant pattern is removed in order to satisfactorily and stably cut the redundant pattern. However, if the insulating film is excessively removed, Due to the influence of water and the like, the cut redundancy pattern suffers from deterioration of insulation such as glow back, which lowers reliability.

Therefore, it is necessary to control the film thickness of the insulating film on the redundant pattern. Conventionally, the bonding window and the redundant pattern portion are separately patterned, and the insulating film is appropriate on the redundant pattern. The thickness of the bonding pattern and the redundant pattern portion window at the same time in order to control the film thickness so that the thickness of the redundant pattern portion window is reduced, or to reduce the number of steps. Control etching is performed.

FIGS. 4 to 6 are side sectional views of essential parts of a semiconductor integrated circuit device in process steps for explaining the conventional technique, which will be described below with reference to these figures.

4 (A) 4- (1) In FIG. 4 (A), an element made of polycrystalline silicon is formed on a base insulating film (field insulating film) 1 covering a substrate in which various element regions are formed. Pattern 2 and redundant pattern 3 are formed, an insulating film 4 covering them is formed, an element pattern 5 made of a conductive film is formed on the insulating film 4, and an insulating film 6 covering them is formed. In order to pattern the first metal layer 7, the first metal layer 7 is formed after forming the electrode contact holes in the insulating films 4 and 6 on the element pattern 2. The state in which the resist film 8 serving as the mask is formed is shown.

As the material for the element pattern 2 and the redundancy pattern 3, not only polycrystalline silicon but also amorphous silicon or WSi / polycrystalline silicon polycide is used.

4 (B) 4- (2) The first metal layer 7 is etched using the resist film 8 as a mask to form a desired wiring pattern.

4- (3) An insulating film 9 is formed on the entire surface including the first metal layer 7.

4- (4) A resist film 10 having an opening for forming an electrode contact hole corresponding to the first metal layer 7 is formed.

5 (A) 5- (1) The insulating film 9 is etched using the resist film 10 as a mask to form electrode contact holes.

5- (2) After removing the resist film 10, the second metal layer 11 is formed.

5- (3) A resist film 12 is formed to serve as an etching mask for the second metal layer 11.

5 (B) 5- (4) The second metal layer 11 is etched using the resist film 12 as a mask to form a required wiring pattern and bonding pad 11P.

5- (5) A cover film 13 is formed on the entire surface including the second metal layer 11.

5- (6) A resist film 14 having a bonding window forming opening 14B and a redundant pattern window forming opening 14R is formed.

6- (1) The cover film 13 is etched using the resist film 14 as a mask to form the bonding window 13B and the redundancy pattern window 13R.

6- (2) The insulating films laminated on the redundancy pattern 3 are controlled and etched to extend the depth of the redundancy pattern window 13R, and then the resist film 14 is removed.

The control etching is stopped with the insulating film having an appropriate thickness left on the redundant pattern 3. For example, the cover film 13 has a thickness of about 0.8 [μ].
m], if the thickness of the insulating film from below the bonding pad 11P formed by the second metal layer 11 to above the redundant pattern 3 is about 1.3 μm, the bonding Cover film 1 for exposing the pad 11P
Etching of 3 is 0.8 [μm], then about 0.9
Control etching of about [μm] is performed so that an insulating film of about 0.4 [μm] remains on the redundancy pattern 3.

[0023]

In the semiconductor integrated circuit device having the redundant circuit created by the above-mentioned conventional technique, when it becomes necessary to activate the redundant circuit, the redundant pattern 3 is covered. All the insulating films that are present will be fused by irradiation with a laser beam, but the redundant pattern window 1
Various problems occur due to insufficient etching or excessive etching of 3R.

FIG. 7 is a side sectional view showing a main part of a semiconductor integrated circuit device for explaining a case where the redundancy pattern window is insufficiently etched. The same symbols as those used in FIGS. 4 to 6 are shown. Represent the same part or have the same meaning.

In this case, since the etching of the redundant pattern window 13R is insufficient and an insulating film having a thickness exceeding the appropriate thickness remains on the redundant pattern 3, the laser beam is emitted. Even if the irradiation is performed, the redundant pattern 3 cannot be blown. In this way, the redundancy pattern 3
Not only is it impossible to melt the wafer, but it is a serious problem that what can and cannot be melted are non-uniformly generated on the wafer surface or in the lot.

FIG. 8 is a fragmentary explanatory view showing a semiconductor integrated circuit device for explaining a case where the redundant pattern window is excessively etched. The same symbols as those used in FIGS. 4 to 7 are shown. Represent the same part or have the same meaning.

In the figure, (A) is a side surface for cutting a main part,
(B) is a main part cutting plane, 3A is a cutting part in the redundancy pattern 3, 15 is a leak generating part, and 100 is a substrate.

In this case, the redundant pattern window 13R is excessively etched, the redundant pattern 3 is completely exposed, and the underlying insulating film 1 is also etched on the side of the redundant pattern 3 to form a substrate. 100 is exposed.

In this state, when the redundant pattern 3 is cut by irradiating it with a laser beam, the redundant pattern 3 and the substrate 100 may leak due to adsorption of moisture or the like.
In addition, the redundant pattern 3 that should have been cut may become conductive.

The cause of such a problem lies mainly in the variation in thickness of various insulating films laminated on the redundancy pattern 3.

FIG. 9 is a fragmentary side view showing the semiconductor integrated circuit device at a process step for explaining the conditions to be considered when forming the redundant pattern window. The same symbols as those used in 6 represent the same parts or have the same meanings.

First, as shown in FIG. 9 (A), the thickness S1 of the insulating film on the redundant pattern 3 is appropriate, and as shown in FIG. 9 (B), the bonding window 13 is formed.
The insulating film does not remain on the bonding pad 11P in B, and as shown in FIG. 9C, the thickness S2 of the insulating film on the side of the redundant pattern 3 forms the redundant pattern window. After that, it keeps an appropriate value, and so on.

Factors influencing the above three conditions are the variation in the film thickness of the cover film 13, the variation in the film thickness of various interlayer insulating films, regardless of the in-plane or the inter-plane, and the film thickness of the lower insulating film (field insulating film). There are variations.

The causes of such film thickness variations are variations in film thickness when the insulating film is grown, variations in film thickness during pretreatment or posttreatment, and etching of the underlying insulating film during formation of the electric circuit pattern. In the same lot, due to variations in film loss due to
Alternatively, it is not uniform even within the wafer surface.

Such an insulating film is not limited to a single layer and is often composed of a plurality of layers grown a plurality of times. In addition to the variation in the film thickness, the bonding window 13B and the redundancy pattern window 13R are formed. The etching rate variation in the etching device is involved.

The etching amount itself can be improved between the wafers by improving the etching distribution of the etching apparatus, changing the batch type etching apparatus to a single wafer type etching apparatus, or by using an etching end point detecting apparatus. Although it is not impossible to suppress the variation in the etching amount, it is not possible to deal with the variation in the film thickness of the insulating film before etching by improving the etching apparatus.

In the present invention, the thickness of the insulating film covering the redundancy pattern is maintained at an appropriate value by utilizing the technique of providing an etching stopper layer which has been frequently used, but it is effective by a simple means. We try to be able to achieve our goals and to be highly reliable.

[0038]

In the field of manufacturing semiconductor integrated circuit devices, when an insulating film is desired to be etched to leave a certain thickness accurately, an etching stop layer for automatically stopping the etching is provided. The technology to be used is well known, and the technology is also used in the present invention to form the pattern window for redundancy.

However, at present, the reduction of the manufacturing cost and the improvement of the reliability of the semiconductor integrated circuit device are the most important issues, and the provision of the etching stop layer does not complicate the manufacturing process or lower the manufacturing yield. Unacceptable.

In the present invention, a conductive film formed on the insulating film covering the redundancy pattern, for example, a DRAM (dynam) is used.
whether to use a material film for forming a cell plate, a bit line, a cell node, etc., which are common electrodes of a memory capacitor in an ic random access memory), and to simultaneously pattern them with the same mask Or, use the bottom metal wiring layer,
At the same time, the etching stop layer is basically formed by simultaneously patterning using a mask for forming wiring.

Further, when the conductive film is used as the etching stop layer, the lowermost metal wiring layer formed above the conductive film has another very useful usage. Therefore, it will be described below. To do.

Generally, in the etching process for forming the bonding window, the improvement of the through-put of the pattern formation is important, that is, the sensitivity is more important than the resolution of the pattern, and the etching time is long. It is necessary to open a small bonding window for the reason that a thick resist film is required because the resist film as a mask is severely thinned, and various step differences appear on the surface under the influence of the element pattern of the lower layer. This is difficult, and of course, this also affects the redundant pattern window, and there is a concern about the defective opening.

Therefore, in order to sufficiently open the redundant pattern window, if it is made large in design, it is necessary to increase the margin between the redundant pattern and the element pattern, which leads to an increase in the chip area.

Further, when the mask is used to form the redundant pattern window and the exposure amount is increased to open the opening, the opening is often too large. In such a case, the element pattern adjacent to the redundant pattern is formed. Is exposed.

By the way, in forming the bonding window, since the bonding pad is made of metal, the etching rate between the metal layer and the insulating film is set to a large value. Therefore, the metal layer may be used as an etching stop layer. it can.

Therefore, if a pattern of the metal layer is introduced on the redundant pattern window, the mask for forming the redundant pattern window is sufficiently exposed, or
It is possible to prevent the opening failure by designing the redundant pattern window to a large size. Of course, as the metal layer in this case, for example, by using the lowermost metal wiring layer, the manufacturing process can be improved. Increase and decrease in manufacturing yield.

By the way, the size of the redundant pattern window is
It is larger than the contact window between the wiring patterns, and the contact window between the wiring patterns is required to have a fine window diameter in terms of device design, and an opening of 1 [μm] or less is also formed.

If the formation of the redundant pattern window is carried out simultaneously with the formation of the contact windows between the wiring patterns, the size of the redundant pattern window is determined by the window diameter of the contact window between the wiring patterns, and the opening can be made small. Therefore, the element pattern of the lower layer will not be exposed in the redundant pattern window, but in order to realize the formation of such a small redundant pattern window without the occurrence of opening defects, as described above, This is substantially possible by introducing a pattern of metal layers on the redundant pattern window.

From the above, in the semiconductor integrated circuit device according to the present invention, (1) on the insulating film (for example, the base insulating film 1 which is a field insulating film) covering the substrate in which the required element region is formed. A redundant pattern (for example, redundant pattern 3) formed in the same layer as the element pattern (for example, element pattern 2),
An insulating film (for example, the insulating film 4) that covers the redundant pattern and accurately maintains a fusingable thickness together with the redundant pattern, and an element pattern is formed on the insulating film that covers the redundant pattern. An insulating film that uses a part of the material film (for example, a conductive film) and is formed larger than the redundant pattern window (for example, the redundant pattern window 13R) corresponding to the redundant pattern and covers the redundant pattern. Or an etching stop pattern (for example, an etching stop pattern 5A) for maintaining the thickness of the layer so that it can be accurately blown, or,

(2) In the above (1), the material film used for the etching stop pattern includes the cell plate, the bit line, the cell node, etc., which are the common electrodes of the memory capacitor in the semiconductor integrated circuit device. Characterized by being a conductive film for forming, or

(3) In the above (1), is it characterized in that the material film used for the etching stop pattern is a metal layer for forming the lowermost metal wiring in the semiconductor integrated circuit device? Or

(4) Formed in the same layer as an element pattern (eg element pattern 2) on an insulating film (eg a base insulating film 1 which is a field insulating film) covering a substrate in which required element regions are formed. The redundant pattern (for example, the redundant pattern 3), the insulating film (for example, the insulating film 4) that covers the redundant pattern and maintains the fusingable thickness together with the redundant pattern, and the redundant pattern On the insulating film, a part of a conductive film for forming a cell plate, a bit line, a cell node, etc., which is a common electrode of a memory capacitor in a semiconductor integrated circuit, is used and the redundancy pattern is used. Of the redundant pattern window (for example, the redundant pattern window 13R) corresponding to the above, the thickness of the insulating film covering the redundant pattern is maintained so that it can be accurately blown. First etching stop pattern (e.g. etch stop pattern 5A) and an insulating film covering said first etch stop pattern (for example, an insulating film 6)
A redundancy pattern corresponding to the redundancy pattern while using a part of the metal layer (for example, the first metal layer 7) for forming the lowermost metal wiring (for example, the metal wiring pattern 7L) It is characterized in that it is provided with a second etching stop pattern (for example, etching stop pattern 7D) formed to be larger than the window.

As described above, the present invention employs the technique of utilizing the etching stop layer, which is a technique which has been used and aged in the past, when forming the redundant pattern window. In addition to the above, as a material of a pattern to be an etching stop layer, a film required for a semiconductor integrated circuit device, for example, a conductive film formed on an insulating film covering a redundancy pattern, that is, DR
A material film for forming a cell plate, a bit line, a cell node, etc., which is a common electrode of a memory capacitor in AM, is used, and is patterned at the same time with the same mask as those, or By using the metal layer for forming the lower metal wiring and patterning at the same time using the mask for forming the wiring, problems such as an increase in the number of manufacturing steps and a decrease in manufacturing yield do not occur. I have to.

Further, the effect obtained by introducing the technique related to the etching stop pattern into the formation of the pattern window for redundancy,
That is, the thickness of the insulating film covering the redundancy pattern can be maintained thin and uniform, and the over-etching margin can be increased.
For example, even when the opening of the redundant pattern window is performed at the same time as the opening of the bonding window, it becomes possible to perform etching for a long time so that the insulating film does not remain in the bonding window. Even if the etching is enlarged or the position is deviated, there is no danger of exposing the underlying material, such as the bulk, and a unique effect is brought about by introducing the etching stop pattern into the formation of the pattern window for redundancy. Can play.

[0055]

1 to 3 are side sectional views showing a main part of a semiconductor integrated circuit device at a process step for explaining an embodiment of the present invention. Will be described with reference to FIG. The same symbols as those used in FIGS. 4 to 9 represent the same parts or have the same meanings.

See FIG. 1A 1- (1) In FIG. 1A, an element pattern 2 and a redundancy pattern are formed on a base insulating film (field insulating film) 1 covering a substrate in which various element regions are formed. Pattern 3 is formed, insulating film 4 covering them is formed, and element pattern 5 and etching stop pattern 5A made of a conductive film are formed on insulating film 4 and insulating film 6 covering them is formed. In order to pattern the first metal layer 7, the first metal layer 7 is formed after forming the electrode contact holes in the insulating films 4 and 6 on the element pattern 2. The state in which the resist film 8 serving as the mask is formed is shown.

The main data regarding each of the above-mentioned parts are illustrated below.

(1) Base Insulating Film 1 Material: For example, LOCOS (lo
cal oxidation of silicon)
Formed by the SiO _{2 method}

(2) Regarding the element pattern 2 and the redundancy pattern 3 Material: For example, polycrystalline silicon (as needed, amorphous silicon, WSi / polycrystalline silicon polycide, etc.) Thickness: 20 nm to 40 [nm] nm]

(3) Insulating film 4 Material: For example, SiO ₂ thickness: 20 [nm]

(4) Regarding the element pattern 5 and the etching stop pattern 5A Material: For example, polycrystalline silicon (amorphous silicon, WSi / polycrystalline silicon polycide, etc., if necessary)

(5) Regarding the insulating film 6 Material: For example, SiO ₂ thickness: 10 [nm] to 20 [nm]

(6) Regarding the first metal layer 7 Material: For example, Al / Si alloy Thickness: -50 nm

See FIG. 1B. 1- (2) The etching gas is Cl ₂ gas or (Cl ₂ + BCl).
₃ ) Reactive ion etching with a mixed gas (rea
by applying the active ion etching (RIE) method, using the resist film 8 as a mask, Al /
The first metal layer 7 made of a Si alloy is etched to form a first metal wiring pattern 7L and an etching stop pattern 7D.

1- (3) Chemical vapor deposition
The insulating film 9 made of SiO ₂ having a thickness of, for example, 80 [nm] to 90 [nm] is formed on the entire surface by applying the position (CVD) method.

1- (4) By applying a resist process in the lithography technique, the resist film 10 having openings in the electrode contact hole formation planned portion and the redundant pattern window formation planned portion is formed.

2 (A) 2- (1) The etching gas is CF ₄ gas or (CF ₄ + CHF).
₃ ) By applying the RIE method using mixed gas, S
The insulating film 9 made of iO ₂ is etched to form electrode contact holes and redundant pattern windows.

The redundancy pattern window formed here can be formed small unlike the case where it is formed simultaneously with the bonding window which requires over-etching.

2- (2) By applying the vacuum deposition method, the thickness is, for example, -10.
Second layer metal layer 1 made of 0 [nm] Al / Si alloy
Form one.

2- (3) A resist which serves as a mask for etching the second metal layer 11 to form a second metal wiring pattern by applying a resist process in the lithography technique. The film 12 is formed.

2 (B). 2- (4) The etching gas is Cl ₂ gas or (Cl ₂ + BCl).
₃ ) By applying the RIE method using a mixed gas, the second layer metal layer 11 made of an Al / Si alloy is etched using the resist film 12 as a mask, and the second layer metal wiring pattern 11L and bonding are performed. -Pad 11P is formed.

When the second-layer metal layer 11 is etched, the second-layer metal layer 11 and the underlying etching stop pattern 7D, which have entered the redundancy pattern window, are also etched. Since it is etching, the side wall 11W remains on the side wall of the pattern window for redundancy,
Therefore, the etching stop pattern 7D on the lower side and the portion covered with the insulating film 9 remains.

2- (6) By applying the CVD method, for example, the thickness is 200.
Phospho-silicate glass (phospho-si) that is [nm]
licate glass (PSG) film and thickness is 400
SiON film or Si having a thickness of [nm] to 500 [nm]
A cover film 13 having a structure in which an N film is laminated is formed.

2- (7) By applying a resist process in the lithography technique, a resist film 14 having openings 14B and 14R is formed in the bonding window formation planned portion and the redundant pattern window formation planned portion.

See FIG. 3A. 3- (1) By applying the RIE method using a (CHF ₃ + CF ₄ ) -based mixed gas as an etching gas, the resist film 14 is used as a mask to cover the cover film 13 and the insulating film. 6 is etched to form the bonding window 13B and the redundant pattern window 1
Form 3R.

Of course, this etching is automatically stopped by the bonding pad 11P acting as an etching stop layer in the bonding window 13B and the etching stop pattern 5A acting in the redundancy pattern window 13R.

3 (B). 3- (2) The etching stop pattern 5A is etched by applying the RIE method using CF ₄ gas as the etching gas to extend the redundancy pattern window 13R. To do.

3- (3) When the above steps are completed, a chip operation test is conducted,
When a defective chip is generated, the redundant pattern window 13R is irradiated with a laser beam as needed, and the insulating film 4 is formed.
At the same time, the redundant pattern 3 is melted and the redundant circuit is activated.

In this case, the thickness of the insulating film 4 on the redundancy pattern 3 is almost uniform on the wafer surface or in the lot due to the function of the etching stop pattern 5A, and therefore the same power is applied. All can be surely blown by the laser beam.

[0080]

In the semiconductor integrated circuit device according to the present invention, the redundant pattern formed in the same layer as the element pattern on the insulating film covering the substrate, the redundant pattern covering the redundant pattern and being fused together with the redundant pattern. Compared to the redundant pattern window corresponding to the redundant pattern while using the insulating film that maintains the possible thickness accurately and a part of the material film that constitutes the element pattern on the insulating film that covers the redundant pattern And an etching stop pattern for maintaining the thickness of the insulating film, which is formed large and covers the redundancy pattern, accurately.

As described above, the present invention adopts the technique of utilizing the etching stop layer, which is a technique which has been widely used and aged in forming the redundant pattern window, as described above. In addition to the above, as a material of a pattern to be an etching stop layer, a film required for a semiconductor integrated circuit device, for example, a conductive film formed on an insulating film covering a redundancy pattern, that is, DR
A material film for forming a cell plate, a bit line, a cell node, etc., which is a common electrode of a memory capacitor in AM, is used, and is patterned at the same time with the same mask as those, or By using the metal layer for forming the lower metal wiring and patterning at the same time using the mask for forming the wiring, problems such as an increase in the number of manufacturing steps and a decrease in manufacturing yield do not occur. I have to.

Further, the effect obtained by introducing the technique concerning the etching stop pattern into the formation of the redundant pattern window,
That is, the thickness of the insulating film covering the redundancy pattern can be maintained thin and uniform, and the over-etching margin can be increased.
For example, even when the opening of the redundant pattern window is performed at the same time as the opening of the bonding window, it becomes possible to perform etching for a long time so that the insulating film does not remain in the bonding window. Even if the etching is enlarged or the position is deviated, there is no danger of exposing the underlying material, such as the bulk, and a unique effect is brought about by introducing the etching stop pattern into the formation of the pattern window for redundancy. Can play.

[Brief description of drawings]

FIG. 1 is a side sectional view showing a main part of a semiconductor integrated circuit device at a process step for explaining an embodiment of the present invention.

FIG. 2 is a side sectional view showing a main part of a semiconductor integrated circuit device at a process step for explaining an embodiment of the present invention.

FIG. 3 is a side sectional view showing a main part of a semiconductor integrated circuit device at a process key point for explaining an embodiment of the present invention.

FIG. 4 is a sectional side view of a main part of a semiconductor integrated circuit device in a process key point for explaining a conventional technique.

FIG. 5 is a side sectional view of a main part of a semiconductor integrated circuit device in a process key point for explaining a conventional technique.

FIG. 6 is a side sectional view of a main part of a semiconductor integrated circuit device in a process key point for explaining a conventional technique.

FIG. 7 is a fragmentary side view showing a semiconductor integrated circuit device for explaining a case where the redundancy pattern window is insufficiently etched.

FIG. 8 is a fragmentary explanatory view showing a semiconductor integrated circuit device for explaining a case where a redundant pattern window is excessively etched.

FIG. 9 is a fragmentary side view showing a semiconductor integrated circuit device in a process key point for explaining a condition to be considered when forming a redundant pattern window.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Base insulating film 2 Element pattern 3 Redundant pattern 3A Cut portion of redundant pattern 4 Insulating film 5 Element pattern 5A Etching stop pattern 6 Insulating film 7 First metal layer 7D Etching stop pattern 8 Resist film 9 Insulating film Reference Signs List 10 resist film 11 second metal layer 11P bonding pad 11W side wall 12 resist film 13 cover film 13B bonding window 13R redundant pattern window 14 resist film 14B bonding window forming opening 14R redundant pattern window forming opening 15 Leakage occurrence part 100 substrate

Claims (4)

[Claims] 1. A redundant pattern formed in the same layer as an element pattern on an insulating film covering a substrate in which a required element region is formed, and a fusible pattern covering the redundant pattern and fusing together with the redundant pattern. An insulating film whose thickness is accurately maintained and a part of a material film forming an element pattern on the insulating film covering the redundant pattern are used, and a redundant pattern window corresponding to the redundant pattern is formed. A semiconductor integrated circuit device, comprising: an etching stop pattern for maintaining a thickness of an insulating film, which is formed to be large in size and covers the redundancy pattern, so that it can be accurately blown. 2. A material film used for an etching stop pattern is a conductive film for forming a cell plate, a bit line, a cell node, etc. which are common electrodes of a memory capacitor in a semiconductor integrated circuit. The semiconductor integrated circuit device according to claim 1, wherein 3. The semiconductor integrated circuit device according to claim 1, wherein the material film used for the etching stop pattern is a metal layer for forming a lowermost metal wiring in the semiconductor integrated circuit. 4. A redundant pattern formed in the same layer as an element pattern on an insulating film covering a substrate in which a required element region is formed, and a redundant pattern covering the redundant pattern and fusible together with the redundant pattern. An insulating film whose thickness is accurately maintained, and a cell which is a common electrode of a memory capacitor in a semiconductor integrated circuit on the insulating film covering the redundancy pattern.
Insulation that uses a part of a conductive film for forming a plate, a bit line, a cell node, etc. and is formed larger than a redundancy pattern window corresponding to the redundancy pattern to cover the redundancy pattern. A first etching stop pattern for maintaining the thickness of the film so that it can be accurately blown, and a metal wiring of the lowest layer on the insulating film covering the first etching stop pattern. A semiconductor integrated circuit device, comprising: a second etching stop pattern, which is formed to be larger than a redundant pattern window corresponding to the redundant pattern and using a part of the metal layer.