JPH09260202A - Laminated capacitor - Google Patents

Laminated capacitor

Info

Publication number
JPH09260202A
JPH09260202A JP7060596A JP7060596A JPH09260202A JP H09260202 A JPH09260202 A JP H09260202A JP 7060596 A JP7060596 A JP 7060596A JP 7060596 A JP7060596 A JP 7060596A JP H09260202 A JPH09260202 A JP H09260202A
Authority
JP
Japan
Prior art keywords
internal electrode
internal
multilayer capacitor
layers
electrodes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7060596A
Other languages
Japanese (ja)
Inventor
Katsuyuki Horie
克之 堀江
Yoichi Mizuno
洋一 水野
Nobuo Mamada
信雄 儘田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiyo Yuden Co Ltd
Original Assignee
Taiyo Yuden Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiyo Yuden Co Ltd filed Critical Taiyo Yuden Co Ltd
Priority to JP7060596A priority Critical patent/JPH09260202A/en
Publication of JPH09260202A publication Critical patent/JPH09260202A/en
Pending legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To provide a laminated capacitor which is free from inside structural defect. SOLUTION: An inside electrode piece 22b laminated through a dielectric layer 21 is formed by being shifted alternately by a specified distance in its width direction for each specified number of layers. Since the lamination number of the inside electrode piece 22b and the dielectric layer 21 in vertical layer direction can be made uniform, it is possible to reduce a structural defect caused by inner stress generated during conventional manufacturing and to improve a yield even if a miniaturized laminated capacitor is formed.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明が属する技術分野】本発明は、積層コンデンサに
関するものである。
TECHNICAL FIELD The present invention relates to a multilayer capacitor.

【0002】[0002]

【従来の技術】図2乃至図4に従来例の積層コンデンサ
を示す。図2は分解斜視図、図3は平面図、図4は図3
のA−A線矢視方向断面図である。
2. Description of the Related Art FIGS. 2 to 4 show a conventional multilayer capacitor. 2 is an exploded perspective view, FIG. 3 is a plan view, and FIG.
3 is a sectional view taken along line AA of FIG.

【0003】図において、10は積層コンデンサで、誘
電体層11と内部電極12とを交互に積層してなる素体
13と、素体13の両端部において内部電極を交互に並
列に接続している一対の外部電極14とから構成されて
いる。
[0003] In the drawing, reference numeral 10 denotes a multilayer capacitor in which a dielectric body 13 formed by alternately laminating dielectric layers 11 and internal electrodes 12 and internal electrodes are alternately connected in parallel at both ends of the dielectric body 13. And a pair of external electrodes 14.

【0004】内部電極12は、誘電体層11の中央領域
付近に設けられた内部電極片12aと、外部電極14に
沿って外部電極14に接続した状態で設けられた内部電
極引出部12bとから成り、内部電極片12aは内部電
極引出部12bを介して外部電極14に接続されてい
る。
The internal electrode 12 is composed of an internal electrode piece 12a provided near the central region of the dielectric layer 11 and an internal electrode lead portion 12b provided along the external electrode 14 and connected to the external electrode 14. The internal electrode piece 12a is connected to the external electrode 14 via the internal electrode lead-out portion 12b.

【0005】誘電体層11は矩形のシート上のセラミッ
ク焼結体からなり、セラミック焼結体は、例えばチタン
酸バリウム等を主成分とする誘電体磁器材料から形成さ
れている。内部電極12は金属ペーストを焼結させた金
属薄膜からなり、金属ペーストとしては、例えばPdや
Ag−Pdのような貴金属材料を主成分とするものが使
用されている。外部電極14も内部電極12と同様の材
料により形成され、表面には半田濡れ性をよくするため
に半田メッキが施されている。
[0005] The dielectric layer 11 is formed of a ceramic sintered body on a rectangular sheet, and the ceramic sintered body is formed of a dielectric ceramic material containing, for example, barium titanate as a main component. The internal electrode 12 is formed of a metal thin film obtained by sintering a metal paste. As the metal paste, for example, an electrode mainly containing a noble metal material such as Pd or Ag-Pd is used. The external electrode 14 is also formed of the same material as the internal electrode 12, and the surface is plated with solder to improve solder wettability.

【0006】[0006]

【発明が解決しようとする課題】しかしながら、積層コ
ンデンサを形成する場合、内部電極層と誘電体層を交互
に積層しているため、内部電極が形成されている部分と
内部電極が形成されていない部分とでは積層数が異なる
ので、加圧の際に応力が生じて構造欠陥(デラミネーシ
ョン、クラック等)の発生率が大きくなってしまう。こ
れは、小型の積層コンデンサを製造する際に顕著に現
れ、歩留まりの低下を招いていた。
However, when forming a multilayer capacitor, since the internal electrode layers and the dielectric layers are alternately laminated, the portions where the internal electrodes are formed and the internal electrodes are not formed. Since the number of laminated layers is different from that of the portion, stress is generated at the time of pressurization, and the occurrence rate of structural defects (delamination, cracks, etc.) increases. This appears remarkably when manufacturing a small multilayer capacitor, leading to a decrease in yield.

【0007】本発明の目的は上記の問題点に鑑み、内部
構造欠陥のない積層コンデンサを提供することにある。
In view of the above problems, it is an object of the present invention to provide a multilayer capacitor having no internal structural defect.

【0008】[0008]

【課題を解決するための手段】本発明は上記の目的を達
成するために請求項1では、誘電体層と内部電極層とを
交互に積層してなる直方体形状の素体と、該素体の両端
部において該内部電極層に形成された内部電極を交互に
並列に接続している一対の外部電極とからなる積層コン
デンサであって、前記内部電極は、該内部電極面に平行
に側縁部方向に変位して形成されている積層コンデンサ
を提案する。
In order to achieve the above object, the present invention provides a rectangular parallelepiped shaped element body in which dielectric layers and internal electrode layers are alternately laminated, and the element body. Is a multilayer capacitor composed of a pair of external electrodes in which the internal electrodes formed on the internal electrode layer are alternately connected in parallel at both ends of the internal electrode, the internal electrodes having side edges parallel to the internal electrode surface. We propose a multilayer capacitor formed by displacing in the direction of the part.

【0009】該積層コンデンサによれば、前記一対の外
部電極に接続されたそれぞれの内部電極は、該内部電極
面に平行に側縁部方向に変位して形成されているので、
上下層方向における積層数を均一化することができる。
According to the multilayer capacitor, each internal electrode connected to the pair of external electrodes is formed by being displaced in the side edge direction parallel to the internal electrode surface.
The number of stacked layers in the upper and lower layers can be made uniform.

【0010】また、請求項2では、請求項1記載の積層
コンデンサにおいて、前記内部電極は連続した所定数の
層毎に側縁部方向に交互に変位して形成されている積層
コンデンサを提案する。
A second aspect of the present invention proposes the multilayer capacitor according to the first aspect, wherein the internal electrodes are formed by alternately displacing each of a predetermined number of continuous layers in a side edge direction. .

【0011】該積層コンデンサによれば、内部電極が連
続した所定数の層毎に側縁部方向に交互に変位して形成
されているため、側縁部方向のバランスを保って積層数
の均一化を図れる。
According to the multilayer capacitor, the internal electrodes are formed by being displaced alternately in the direction of the side edge portion for each of a predetermined number of continuous layers. Can be realized.

【0012】[0012]

【発明の実施の形態】以下、図面に基づいて本発明の一
実施形態を説明する。図1は一実施形態における一実施
例の積層コンデンサを示す分解斜視図、図5は平断面
図、図6は図5におけるB−B線矢視方向断面図であ
る。図において、20は積層コンデンサで、誘電体層2
1と内部電極22とを交互に積層してなる素体23と、
素体23の両端部において内部電極22を交互に並列に
接続している一対の外部電極24とから構成されてい
る。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. 1 is an exploded perspective view showing a multilayer capacitor according to an embodiment of the present invention, FIG. 5 is a plan sectional view, and FIG. 6 is a sectional view taken along line BB in FIG. In the figure, reference numeral 20 denotes a multilayer capacitor, which is a dielectric layer 2
Element body 23 formed by alternately laminating 1 and internal electrodes 22;
It is composed of a pair of external electrodes 24 that alternately connect the internal electrodes 22 in parallel at both ends of the element body 23.

【0013】誘電体層21は、矩形のシート状のセラミ
ック焼結体からなり、焼結体は例えばチタン酸バリウム
を主成分とするグリーンシートを焼成して形成した誘電
体磁器材料からなる。
The dielectric layer 21 is made of a rectangular sheet-shaped ceramic sintered body, and the sintered body is made of a dielectric ceramic material formed by firing a green sheet containing barium titanate as a main component, for example.

【0014】誘電体層21を介して隣り合う一対の内部
電極22のそれぞれは、外部電極24に沿って設けられ
た内部電極引出部22aと、この内部電極引出部22a
に基端部が接続された内部電極片22bとから構成され
ている。この内部電極片22bは矩形になっており、内
部電極片22bの長辺は外部電極24に対して略直角に
なっている。
Each of the pair of internal electrodes 22 adjacent to each other through the dielectric layer 21 has an internal electrode lead-out portion 22a provided along the external electrode 24 and the internal electrode lead-out portion 22a.
And an internal electrode piece 22b to which the base end is connected. The internal electrode piece 22b has a rectangular shape, and the long side of the internal electrode piece 22b is substantially perpendicular to the external electrode 24.

【0015】また、各内部電極22における内部電極片
22bの幅は各々等しく形成されている。
The widths of the internal electrode pieces 22b in the internal electrodes 22 are equal to each other.

【0016】一方、内部電極片22bは連続した2層毎
に交互にその幅方向に所定距離だけずらして形成されて
いる。これにより、図6に示すように、A部、B部、C
部の粗密が段階的に変化している。
On the other hand, the internal electrode pieces 22b are formed alternately every two continuous layers with a predetermined distance offset in the width direction. As a result, as shown in FIG.
The density of the parts is changing in stages.

【0017】これらの内部電極22は導電性ペーストの
薄膜を焼結させた金属薄膜からなり、導電性ペーストと
しては、例えばパラジウム粉末を主成分とするものが使
用されている。外部電極24も内部電極22と同様の材
料により形成され、表面には半田濡れ性をよくするため
に半田メッキが施されている。
These internal electrodes 22 are made of a metal thin film obtained by sintering a thin film of a conductive paste, and the conductive paste is mainly composed of palladium powder, for example. The external electrode 24 is also formed of the same material as the internal electrode 22, and its surface is plated with solder to improve solder wettability.

【0018】この積層コンデンサは次のようにして製造
した。まず、誘電体の原料粉末に有機バインダーを15
重量%添加し、さらに水を50重量%加え、これらをボ
ールミルに入れて十分に混合し、誘電体磁器原料のスラ
リーを作成した。
This multilayer capacitor was manufactured as follows. First, an organic binder was added to the dielectric raw material powder.
% By weight, and further 50% by weight of water, and these were put into a ball mill and mixed well to prepare a slurry of a dielectric ceramic raw material.

【0019】次に、このスラリーを真空脱泡器に入れて
脱泡した後、リバースロールコーターに入れ、ポリエス
テルフィルム上にこのスラリーからなる薄膜を形成し、
この薄膜をポリエステルフィルム上で100℃に加熱し
て乾燥させ、これを打ち抜いて、10cm角、厚さ約2
0μmのグリーンシートを得た。
Next, after putting this slurry in a vacuum defoamer to defoam it, put it in a reverse roll coater to form a thin film of this slurry on a polyester film,
This thin film is dried by heating to 100 ° C. on a polyester film, punched out, and 10 cm square, about 2 mm thick.
A green sheet of 0 μm was obtained.

【0020】一方、平均粒径が1.5μmのパラジウム
粉末10gと、エチルセルロース0.9gをブチルカル
ビトール9.1gに溶解させたものとを攪拌器に入れ、
10時間攪拌することにより内部電極用の導電性ペース
トを得た。
On the other hand, 10 g of palladium powder having an average particle size of 1.5 μm and 0.9 g of ethyl cellulose dissolved in 9.1 g of butyl carbitol were placed in a stirrer.
By stirring for 10 hours, a conductive paste for an internal electrode was obtained.

【0021】この後、上述した内部電極のパターンを5
0個有する各スクリーンを用いて、上記グリーンシート
の片面にこの導電性ペーストからなる内部電極のパター
ンを各々印刷し、これを乾燥させた。
After that, the above-mentioned internal electrode pattern
Using each of the screens having zero, a pattern of the internal electrode made of the conductive paste was printed on one surface of the green sheet, and dried.

【0022】次に、上記印刷面を上にしてグリーンシー
トを複数枚積層し、さらにこの積層物の上下両面に印刷
の施されていないグリーンシートを積層した。次いで、
この積層物を約50℃の温度で厚さ方向に約40トンの
圧力を加えて圧着させた。この後、この積層物を格子状
に裁断し、約50個の積層チップを得た。
Next, a plurality of green sheets were laminated with the printing surface facing upward, and further, unprinted green sheets were laminated on the upper and lower surfaces of this laminate. Then
This laminate was pressed at a temperature of about 50 ° C. by applying a pressure of about 40 tons in the thickness direction. Thereafter, the laminate was cut into a lattice to obtain about 50 laminated chips.

【0023】次に、この積層チップを雰囲気焼成可能な
炉に入れ、大気中で600℃まで加熱して、有機バイン
ダーを焼成させ、その後、炉の雰囲気を大気中雰囲気と
し、積層体チップの加熱温度を600℃から焼成温度の
1150℃(最高温度)を3時間保持した。この後、1
00℃/hrの速度で600℃まで降温し、室温まで冷
却して、焼結体チップを得た。
Next, this laminated chip is placed in a furnace capable of firing in an atmosphere, heated to 600 ° C. in the atmosphere to fire the organic binder, and then the atmosphere of the oven is set to the atmosphere in the atmosphere to heat the laminated chip. The temperature was maintained at 600 ° C. to 1150 ° C. (maximum temperature), which is the firing temperature, for 3 hours. After this, 1
The temperature was lowered to 600 ° C. at a rate of 00 ° C./hr and cooled to room temperature to obtain a sintered body chip.

【0024】次いで、内部電極が露出する焼結体チップ
の側面に銀とガラスフリットとビヒクルからなる導電性
ペーストを塗布して乾燥させ、これを大気中で800℃
の温度で15分間焼き付け、銀電極層を形成し、さらに
この上に銅を無電解メッキで被着させ、この上に電気メ
ッキ法でPb−Sn半田層を設けて、一対の外部電極を
形成した。これによって積層コンデンサが得られた。
Next, a conductive paste consisting of silver, glass frit and vehicle is applied to the side surface of the sintered body chip where the internal electrodes are exposed and dried, and this is dried in air at 800 ° C.
Baking at a temperature of 15 minutes to form a silver electrode layer, further depositing copper thereon by electroless plating, and providing a Pb-Sn solder layer thereon by electroplating to form a pair of external electrodes did. As a result, a multilayer capacitor was obtained.

【0025】前述の構成よりなる積層コンデンサによれ
ば、一対の外部電極24に接続されたそれぞれの内部電
極片22bは、2層毎に、内部電極面に平行にその幅方
向に交互にずらして形成されているため、幅方向のバラ
ンスを保って上下層方向における積層数を均一化するこ
とができ、内部応力の発生を低減することができる。ま
た、密着性が向上する。これにより、従来製造時に発生
していた内部応力に起因する構造欠陥を低減することが
できると共に、小型の積層コンデンサを形成した場合に
も歩留まりの向上を図ることができる。
According to the multilayer capacitor having the above-mentioned structure, each of the internal electrode pieces 22b connected to the pair of external electrodes 24 is alternately arranged in the width direction in parallel with the internal electrode surface every two layers. Since it is formed, it is possible to maintain the balance in the width direction and make the number of stacked layers in the upper and lower layers uniform, thereby reducing the occurrence of internal stress. Also, the adhesion is improved. As a result, it is possible to reduce structural defects due to internal stress that have occurred during conventional manufacturing, and it is possible to improve the yield even when a small multilayer capacitor is formed.

【0026】尚、これらの実施例は一例であり本発明が
これに限定されることはない。例えば、図7に示すよう
に内部電極22を1層毎に徐々にその幅方向にずらし、
これを所定の層数毎に繰り返すように積層してもほぼ同
様の効果を得ることができる。
These embodiments are merely examples, and the present invention is not limited to these. For example, as shown in FIG. 7, the internal electrodes 22 are gradually shifted in the width direction for each layer,
Almost the same effect can be obtained by repeating this process for each predetermined number of layers.

【0027】また、内部電極片22bの面積は全ての層
に亘って等しく設定する必要はなく、異なっていても同
様の効果を奏する。
Further, it is not necessary to set the area of the internal electrode pieces 22b equal over all the layers, and the same effect can be obtained even if they are different.

【0028】[0028]

【発明の効果】以上説明したように本発明の請求項1に
よれば、一対の外部電極に接続されたそれぞれの内部電
極は、該内部電極面に平行に側縁部方向に変位して形成
されているため、上下層方向における積層数を均一化す
ることができ、内部応力の発生を低減することができる
ので、従来製造時に発生していた内部応力に起因する構
造欠陥を低減することができると共に、小型の積層コン
デンサを形成した場合にも歩留まりの向上を図ることが
できる。
As described above, according to claim 1 of the present invention, each internal electrode connected to the pair of external electrodes is formed by being displaced in the side edge direction parallel to the internal electrode surface. Therefore, the number of stacked layers in the upper and lower layers can be made uniform, and the generation of internal stress can be reduced. Therefore, it is possible to reduce the structural defects due to the internal stress that have occurred during conventional manufacturing. In addition, the yield can be improved even when a small multilayer capacitor is formed.

【0029】また、請求項2によれば、上記の効果に加
えて、内部電極が連続した所定数の層毎に側縁部方向に
交互に変位して形成されているため、側縁部方向のバラ
ンスを保って積層数の均一化を図ることができ、さらに
内部応力歪の発生を低減することができ、クラックやデ
ラミネーション等の構造欠陥の発生を防止することがで
きる。
According to the second aspect, in addition to the above effect, since the internal electrodes are alternately displaced in the direction of the side edge portion for every predetermined number of continuous layers, the direction of the side edge portion is formed. The number of laminated layers can be made uniform while maintaining the above balance, the occurrence of internal stress strain can be reduced, and the occurrence of structural defects such as cracks and delamination can be prevented.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例の積層コンデンサを示す分解
斜視図
FIG. 1 is an exploded perspective view showing a multilayer capacitor according to an embodiment of the present invention.

【図2】従来例の積層コンデンサを示す分解斜視図FIG. 2 is an exploded perspective view showing a conventional multilayer capacitor.

【図3】従来例の積層コンデンサを示す平断面図FIG. 3 is a cross-sectional plan view showing a conventional multilayer capacitor.

【図4】図3のA−A線矢視方向断面図FIG. 4 is a sectional view taken along line AA of FIG. 3;

【図5】本発明の一実施例の積層コンデンサを示す平断
面図
FIG. 5 is a plan sectional view showing a multilayer capacitor according to an embodiment of the present invention.

【図6】図5におけるB−B線矢視方向断面図6 is a sectional view taken along the line BB in FIG.

【図7】本発明の他の実施例の積層コンデンサを示す断
面図
FIG. 7 is a sectional view showing a multilayer capacitor of another embodiment of the present invention.

【符号の説明】[Explanation of symbols]

20…積層コンデンサ、21…誘電体層、22…内部電
極、22a…内部電極引出部、22b…内部電極片、2
3…素体、24…外部電極。
20 ... Multilayer capacitor, 21 ... Dielectric layer, 22 ... Internal electrode, 22a ... Internal electrode lead-out part, 22b ... Internal electrode piece, 2
3 ... Element body, 24 ... External electrodes.

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 誘電体層と内部電極層とを交互に積層し
てなる直方体形状の素体と、該素体の両端部において該
内部電極層に形成された内部電極を交互に並列に接続し
ている一対の外部電極とからなる積層コンデンサであっ
て、 前記内部電極は、該内部電極面に平行に側縁部方向に変
位して形成されていることを特徴とする積層コンデン
サ。
1. A rectangular parallelepiped element body in which dielectric layers and internal electrode layers are alternately laminated, and internal electrodes formed on the internal electrode layers at both ends of the element body are alternately connected in parallel. A multilayer capacitor comprising a pair of external electrodes, wherein the internal electrode is formed by being displaced in a side edge direction parallel to the internal electrode surface.
【請求項2】 前記内部電極は連続した所定数の層毎に
側縁部方向に交互に変位して形成されていることを特徴
とする請求項1記載の積層コンデンサ。
2. The multilayer capacitor according to claim 1, wherein the internal electrodes are formed by alternately displacing each of a predetermined number of continuous layers in a side edge direction.
JP7060596A 1996-03-26 1996-03-26 Laminated capacitor Pending JPH09260202A (en)

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JPH09260202A true JPH09260202A (en) 1997-10-03

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015053511A (en) * 2012-12-20 2015-03-19 サムソン エレクトロ−メカニックス カンパニーリミテッド. Multilayer ceramic electronic component and method of manufacturing the same
US20170352483A1 (en) * 2016-06-07 2017-12-07 Taiyo Yuden Co., Ltd. Multilayer ceramic capacitor
US10347428B2 (en) 2016-07-05 2019-07-09 Taiyo Yuden Co., Ltd. Multilayer ceramic capacitor

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015053511A (en) * 2012-12-20 2015-03-19 サムソン エレクトロ−メカニックス カンパニーリミテッド. Multilayer ceramic electronic component and method of manufacturing the same
US9484153B2 (en) 2012-12-20 2016-11-01 Samsung Electro-Mechanics Co., Ltd. Multilayer ceramic electronic component having a plurality of internal electrodes and method for manufacturing the same
US20170352483A1 (en) * 2016-06-07 2017-12-07 Taiyo Yuden Co., Ltd. Multilayer ceramic capacitor
JP2017220560A (en) * 2016-06-07 2017-12-14 太陽誘電株式会社 Multilayer ceramic capacitor
US10529487B2 (en) 2016-06-07 2020-01-07 Taiyo Yuden Co., Ltd. Multilayer ceramic capacitor with internal electrodes having different edge positions
US10347428B2 (en) 2016-07-05 2019-07-09 Taiyo Yuden Co., Ltd. Multilayer ceramic capacitor

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