JPH09129477A - Laminated capacitor - Google Patents

Laminated capacitor

Info

Publication number
JPH09129477A
JPH09129477A JP28012495A JP28012495A JPH09129477A JP H09129477 A JPH09129477 A JP H09129477A JP 28012495 A JP28012495 A JP 28012495A JP 28012495 A JP28012495 A JP 28012495A JP H09129477 A JPH09129477 A JP H09129477A
Authority
JP
Japan
Prior art keywords
internal electrode
cross
section
ratio
length
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP28012495A
Other languages
Japanese (ja)
Inventor
Yoichi Mizuno
洋一 水野
Atsushi Masuda
淳 増田
Koichi Chazono
広一 茶園
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiyo Yuden Co Ltd
Original Assignee
Taiyo Yuden Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiyo Yuden Co Ltd filed Critical Taiyo Yuden Co Ltd
Priority to JP28012495A priority Critical patent/JPH09129477A/en
Publication of JPH09129477A publication Critical patent/JPH09129477A/en
Withdrawn legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To provide a laminated capacitor having a low electrostatic capacitance and a high quality factor and having no defect in its internal structure. SOLUTION: The size of a dielectric layer 21 and the shape of internal electrode pieces 22b are set in such a manner that the ratio of the width D of the internal electrode pieces 22b and the width W of the dielectric layer 21 becomes the prescribed value in the range of 0.1 to 0.4, and at the same time, the ratio (L1/L) of the length L1 of the internal electrode pieces 22b and the length L of the dielectric layer 21 becomes in the range of 0.5 to 0.9. As a result, the dielectric layers of the upper and the lower layers of the dielctric layer 1 can be sufficiently adhered directly with each other on the area, in the widthwise direction and the longitudinal direction of the internal electrode pieces without intermediary of the internal electrode pieces 22b. As a result, the generation of the structural defects such as cracks, delamination, etc., can be prevented.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明が属する技術分野】本発明は、積層コンデンサに
関し、特に静電容量の小さな高周波用の積層コンデンサ
に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer capacitor, and more particularly to a high-frequency multilayer capacitor having a small capacitance.

【0002】[0002]

【従来の技術】図2乃至図4に従来例の積層コンデンサ
を示す。図2は分解斜視図、図3は平面図、図4は図3
のA−A線矢視方向断面図である。
2. Description of the Related Art FIGS. 2 to 4 show a conventional multilayer capacitor. 2 is an exploded perspective view, FIG. 3 is a plan view, and FIG.
3 is a sectional view taken along line AA of FIG.

【0003】図において、10は積層コンデンサで、誘
電体層11と内部電極12とを交互に積層してなる素体
13と、素体13の両端部において内部電極を交互に並
列に接続している一対の外部電極14とから構成されて
いる。
[0003] In the drawing, reference numeral 10 denotes a multilayer capacitor in which a dielectric body 13 formed by alternately laminating dielectric layers 11 and internal electrodes 12 and internal electrodes are alternately connected in parallel at both ends of the dielectric body 13. And a pair of external electrodes 14.

【0004】内部電極12は、誘電体層11の中央領域
付近に設けられた内部電極片12aと、外部電極14に
沿って外部電極14に接続した状態で設けられた内部電
極引出部12bとから成り、内部電極片12aは内部電
極引出部12bを介して外部電極14に接続されてい
る。
The internal electrode 12 is composed of an internal electrode piece 12a provided near the central region of the dielectric layer 11 and an internal electrode lead portion 12b provided along the external electrode 14 and connected to the external electrode 14. The internal electrode piece 12a is connected to the external electrode 14 via the internal electrode lead-out portion 12b.

【0005】誘電体層11は矩形のシート上のセラミッ
ク焼結体からなり、セラミック焼結体は、例えばチタン
酸バリウム等を主成分とする誘電体磁器材料から形成さ
れている。内部電極12は金属ペーストを焼結させた金
属薄膜からなり、金属ペーストとしては、例えばPdや
Ag−Pdのような貴金属材料を主成分とするものが使
用されている。外部電極14もない部電極12と同様の
材料により形成され、表面には半田濡れ性をよくするた
めに半田メッキが施されている。
[0005] The dielectric layer 11 is formed of a ceramic sintered body on a rectangular sheet, and the ceramic sintered body is formed of a dielectric ceramic material containing, for example, barium titanate as a main component. The internal electrode 12 is formed of a metal thin film obtained by sintering a metal paste. As the metal paste, for example, an electrode mainly containing a noble metal material such as Pd or Ag-Pd is used. It is formed of the same material as the part electrode 12 without the external electrode 14, and its surface is plated with solder to improve solder wettability.

【0006】[0006]

【発明が解決しようとする課題】ところで、近年、移動
通信機器等に使用される通信用の周波数が高周波帯(G
Hz帯)へ移行してきており、これに伴って移動通信機
器等に使用される積層コンデンサも高周波帯への対応を
余儀なくされている。
In recent years, communication frequencies used in mobile communication devices and the like have been changed to high frequency bands (G-bands).
(Hz band), and accordingly, multilayer capacitors used in mobile communication devices and the like have to be adapted to the high frequency band.

【0007】積層コンデンサを高周波帯へ対応させるた
めには、高周波域において低容量、例えば10pF以下
の静電容量の積層コンデンサのQ値を高める必要があ
る。
In order to make a multilayer capacitor compatible with a high frequency band, it is necessary to increase the Q value of a multilayer capacitor having a low capacitance, for example, a capacitance of 10 pF or less in a high frequency range.

【0008】このように高周波域において、低容量の積
層コンデンサのQ値を高めるためには、内部電極の電気
抵抗を小さくする必要がある。
As described above, in order to increase the Q value of a low-capacitance multilayer capacitor in a high-frequency range, it is necessary to reduce the electric resistance of internal electrodes.

【0009】内部電極の電気抵抗を小さくする方法とし
ては、内部電極の面積を広くしたり、内部電極の厚みを
厚くしたりする方法がある。
As a method of reducing the electric resistance of the internal electrode, there are methods of increasing the area of the internal electrode and increasing the thickness of the internal electrode.

【0010】しかしながら、内部電極の面積を大きくす
ると静電容量が大きくなりすぎるので、内部電極間の距
離を広げたり、積層数を減らしたりしなければならず、
このため、内部電極間の電気抵抗が高まったり、Q値が
低下したりする。
However, when the area of the internal electrodes is increased, the capacitance becomes too large. Therefore, it is necessary to increase the distance between the internal electrodes and reduce the number of layers.
For this reason, the electric resistance between the internal electrodes increases or the Q value decreases.

【0011】また、内部電極を厚くすると、内部電極の
電気抵抗は下がるが、内部電極の局部的な累積によりそ
の部分は局部的に厚くなって内部歪みが増大したり、P
d等からなる内部電極の酸化膨張により、構造欠陥(デ
ラミネーション、クラック等)の発生率が大きくなって
しまう。
When the internal electrode is made thicker, the electric resistance of the internal electrode is lowered. However, due to the local accumulation of the internal electrode, the portion is locally thickened and the internal strain is increased.
Due to oxidative expansion of the internal electrode made of d or the like, the incidence of structural defects (delamination, cracks, etc.) increases.

【0012】本発明の目的は上記の問題点に鑑み、低い
静電容量を保ち、高いQ値を有すると共に内部構造欠陥
のない積層コンデンサを提供することにある。
In view of the above problems, an object of the present invention is to provide a multilayer capacitor having a low capacitance, a high Q value and no internal structural defects.

【0013】[0013]

【課題を解決するための手段】本発明は上記の目的を達
成するために請求項1では、誘電体層と内部電極層とを
交互に積層してなる直方体形状の素体と、該素体の両端
部において該内部電極層に形成された内部電極を交互に
並列に接続している一対の外部電極とからなる積層コン
デンサであって、前記内部電極は、同層内に形成され、
所定間隔をあけてほぼ平行に延びる2つの内部電極片を
有し、前記内部電極片の幅Dと前記誘電体層の幅Wとの
比(D/W)が0.1以上0.4以下の範囲内の所定値
に設定されている積層コンデンサを提案する。
In order to achieve the above object, the present invention provides a rectangular parallelepiped shaped element body in which dielectric layers and internal electrode layers are alternately laminated, and the element body. A pair of external electrodes in which the internal electrodes formed in the internal electrode layer are alternately connected in parallel at both ends of the internal electrode, the internal electrodes being formed in the same layer,
It has two internal electrode pieces that extend substantially in parallel at a predetermined interval, and the ratio (D / W) of the width D of the internal electrode pieces to the width W of the dielectric layer is 0.1 or more and 0.4 or less. We propose a multilayer capacitor set to a predetermined value within the range.

【0014】該積層コンデンサによれば、前記内部電極
片の幅Dと前記誘電体層の幅Wとの比(D/W)が0.
1以上0.4以下の範囲内の所定値に設定されているの
で、内部電極片の面積、及び幅方向において内部電極片
を介さずに直接上下層の誘電体層が密着する割合が必要
十分に得られる。
According to the multilayer capacitor, the ratio (D / W) of the width D of the internal electrode piece to the width W of the dielectric layer is 0.
Since it is set to a predetermined value within the range of 1 or more and 0.4 or less, it is necessary and sufficient that the area of the internal electrode piece and the ratio in which the upper and lower dielectric layers directly adhere to each other in the width direction without interposing the internal electrode piece Can be obtained.

【0015】また、請求項2では、誘電体層と内部電極
層とを交互に積層してなる直方体形状の素体と、該素体
の両端部において該内部電極層に形成された内部電極を
交互に並列に接続している一対の外部電極とからなる積
層コンデンサであって、前記内部電極は、同層内に形成
され、所定間隔をあけてほぼ平行に延びる2つの内部電
極片を有し、前記内部電極片の長さL1と前記誘電体層
の長さLとの比(L1/L)が0.5以上0.9以下の
範囲内の所定値に設定されている積層コンデンサを提案
する。
According to a second aspect of the present invention, a rectangular parallelepiped element body formed by alternately laminating dielectric layers and internal electrode layers and internal electrodes formed on the internal electrode layer at both ends of the element body are provided. A multilayer capacitor comprising a pair of external electrodes that are alternately connected in parallel, wherein the internal electrodes have two internal electrode pieces formed in the same layer and extending substantially in parallel at a predetermined interval. Proposing a multilayer capacitor in which the ratio (L1 / L) of the length L1 of the internal electrode piece to the length L of the dielectric layer is set to a predetermined value within the range of 0.5 or more and 0.9 or less. To do.

【0016】該積層コンデンサによれば、前記内部電極
片の長さL1と前記誘電体層の長さLとの比(L1/
L)が0.5以上0.9以下の範囲内の所定値に設定さ
れているので、内部電極片の面積、及び長さ方向におい
て内部電極片を介さずに直接上下層の誘電体層が密着す
る割合が必要十分に得られる。
According to the multilayer capacitor, the ratio of the length L1 of the internal electrode piece to the length L of the dielectric layer (L1 /
L) is set to a predetermined value within the range of 0.5 or more and 0.9 or less, so that the upper and lower dielectric layers can be directly connected in the area of the internal electrode piece and in the length direction without the internal electrode piece. A necessary and sufficient ratio of close contact can be obtained.

【0017】また、請求項3では、誘電体層と内部電極
層とを交互に積層してなる直方体形状の素体と、該素体
の両端部において該内部電極層に形成された内部電極を
交互に並列に接続している一対の外部電極とからなる積
層コンデンサであって、前記内部電極は、同層内に形成
され、所定間隔をあけてほぼ平行に延びる2つの内部電
極片を有し、前記内部電極片の幅Dと前記誘電体層の幅
Wとの比(D/W)が0.1以上0.4以下の範囲内の
所定値に設定されると共に、前記内部電極片の長さL1
と前記誘電体層の長さLとの比(L1/L)が0.5以
上0.9以下の範囲内の所定値に設定されている積層コ
ンデンサを提案する。
According to a third aspect of the present invention, a rectangular parallelepiped element body formed by alternately laminating dielectric layers and internal electrode layers and internal electrodes formed on the internal electrode layer at both ends of the element body are provided. A multilayer capacitor comprising a pair of external electrodes that are alternately connected in parallel, wherein the internal electrodes have two internal electrode pieces formed in the same layer and extending substantially in parallel at a predetermined interval. , The ratio (D / W) of the width D of the internal electrode piece to the width W of the dielectric layer is set to a predetermined value within the range of 0.1 or more and 0.4 or less, and Length L1
A multilayer capacitor is proposed in which the ratio (L1 / L) of the dielectric layer to the length L of the dielectric layer is set to a predetermined value within the range of 0.5 or more and 0.9 or less.

【0018】該積層コンデンサによれば、前記内部電極
片の幅Dと前記誘電体層の幅Wとの比(D/W)が0.
1以上0.4以下の範囲内の所定値に設定されると共
に、前記内部電極片の長さL1と前記誘電体層の長さL
との比(L1/L)が0.5以上0.9以下の範囲内の
所定値に設定されているので、内部電極片の面積、及び
内部電極片を介さずに直接上下層の誘電体層が密着する
割合が必要十分に得られる。
According to the multilayer capacitor, the ratio (D / W) of the width D of the internal electrode piece to the width W of the dielectric layer is 0.
It is set to a predetermined value within the range of 1 or more and 0.4 or less, and the length L1 of the internal electrode piece and the length L of the dielectric layer are set.
(L1 / L) is set to a predetermined value within the range of 0.5 or more and 0.9 or less, the area of the internal electrode piece and the dielectric material of the upper and lower layers directly without the internal electrode piece. A sufficient ratio of the layers to be in close contact can be obtained.

【0019】また、請求項4では、誘電体層と内部電極
層とを交互に積層してなる直方体形状の素体と、該素体
の両端部において該内部電極層に形成された内部電極を
交互に並列に接続している一対の外部電極とからなる積
層コンデンサであって、前記内部電極は、同層内に形成
され、所定間隔をあけてほぼ平行に延びる2つの内部電
極片を有し、両端の外部電極を結ぶ軸に直角に交わる断
面において、該断面の縦方向の長さTと、前記断面内に
おける内部電極の形成領域の周縁から前記内部電極面に
平行に延びる前記断面の外辺までの距離T1との比(T
1/T)が、前記断面の横方向の長さWと、前記断面内
における内部電極の形成領域の周縁から前記内部電極面
に対して直角方向に延びる前記断面の外辺までの距離W
1との比(W1/W)とほぼ等しく設定され、これらの
比(T1/T、W1/W)が0.15以上0.4以下の
範囲内の所定値に設定されている積層コンデンサを提案
する。
According to a fourth aspect of the present invention, a rectangular parallelepiped element body formed by alternately laminating dielectric layers and internal electrode layers and internal electrodes formed on the internal electrode layer at both ends of the element body are provided. A multilayer capacitor comprising a pair of external electrodes that are alternately connected in parallel, wherein the internal electrodes have two internal electrode pieces formed in the same layer and extending substantially in parallel at a predetermined interval. , In a cross section perpendicular to the axis connecting the external electrodes at both ends, the length T in the longitudinal direction of the cross section and the outside of the cross section extending parallel to the internal electrode surface from the peripheral edge of the formation region of the internal electrode in the cross section. Ratio to the distance T1 to the side (T
1 / T) is the lateral length W of the cross section and the distance W from the peripheral edge of the internal electrode formation region in the cross section to the outer edge of the cross section extending in the direction perpendicular to the internal electrode surface.
A multilayer capacitor that is set to be substantially equal to the ratio (W1 / W) to 1 and these ratios (T1 / T, W1 / W) are set to a predetermined value within the range of 0.15 to 0.4. suggest.

【0020】該積層コンデンサによれば、前記断面内に
おける内部電極の形成領域の周縁から前記内部電極面に
平行に延びる前記断面の外辺までの距離T1との比(T
1/T)が、前記断面の横方向の長さWと、前記断面内
における内部電極の形成領域の周縁から前記内部電極面
に対して直角方向に延びる前記断面の外辺までの距離W
1との比(W1/W)とほぼ等しく設定され、これらの
比(T1/T、W1/W)が0.15以上0.4以下の
範囲内の所定値に設定されているので、素体外部に存在
する導体と内部電極片との間の距離を必要十分に得られ
る。
According to the multilayer capacitor, the ratio (T) to the distance T1 from the peripheral edge of the area where the internal electrode is formed in the cross section to the outer side of the cross section that extends parallel to the internal electrode surface.
1 / T) is the lateral length W of the cross section and the distance W from the peripheral edge of the internal electrode formation region in the cross section to the outer edge of the cross section extending in the direction perpendicular to the internal electrode surface.
It is set to be almost equal to the ratio (W1 / W) to 1 and these ratios (T1 / T, W1 / W) are set to a predetermined value within the range of 0.15 or more and 0.4 or less. A sufficient distance can be obtained between the conductor existing outside the body and the internal electrode piece.

【0021】また、請求項5では、誘電体層と内部電極
層とを交互に積層してなる直方体形状の素体と、該素体
の両端部において該内部電極層に形成された内部電極を
交互に並列に接続している一対の外部電極とからなる積
層コンデンサであって、前記内部電極は、同層内に形成
され、所定間隔をあけてほぼ平行に延びる2つの内部電
極片を有し、両端の外部電極を結ぶ軸に直角に交わる断
面の縦方向の長さTと、該断面における前記内部電極の
形成領域の縦方向の長さT2との比(T2/T)が0.
2以上0.7以下の範囲内の所定値に設定されている積
層コンデンサを提案する。
Further, in the present invention, a rectangular parallelepiped element body formed by alternately laminating dielectric layers and internal electrode layers and internal electrodes formed on the internal electrode layers at both ends of the element body are provided. A multilayer capacitor comprising a pair of external electrodes that are alternately connected in parallel, wherein the internal electrodes have two internal electrode pieces formed in the same layer and extending substantially in parallel at a predetermined interval. , The ratio (T2 / T) of the vertical length T of the cross section perpendicular to the axis connecting the external electrodes at both ends to the vertical length T2 of the internal electrode formation region in the cross section is 0.
We propose a multilayer capacitor set to a predetermined value within the range of 2 or more and 0.7 or less.

【0022】該積層コンデンサによれば、前記断面の縦
方向の長さTと、前記内部電極の形成領域の縦方向の長
さT2との比(T2/T)が0.2以上0.7以下の範
囲内の所定値に設定されているので、素体外部に存在す
る導体と内部電極片の面との間の距離を必要十分に得ら
れる。
According to the multilayer capacitor, the ratio (T2 / T) of the length T in the vertical direction of the cross section to the length T2 in the vertical direction of the area where the internal electrodes are formed is 0.2 or more and 0.7. Since it is set to a predetermined value within the following range, a sufficient distance can be obtained between the conductor existing outside the element body and the surface of the internal electrode piece.

【0023】また、請求項6では、誘電体層と内部電極
層とを交互に積層してなる直方体形状の素体と、該素体
の両端部において該内部電極層に形成された内部電極を
交互に並列に接続している一対の外部電極とからなる積
層コンデンサであって、前記内部電極は、同層内に形成
され、所定間隔をあけてほぼ平行に延びる2つの内部電
極片を有し、両端の外部電極を結ぶ軸に直角に交わる断
面における前記内部電極の形成領域の縦方向の長さT2
と前記内部電極片の厚さT3との比(T3/T2)が
0.004以上0.1以下の範囲内の所定値に設定され
ている積層コンデンサを提案する。
According to a sixth aspect of the present invention, a rectangular parallelepiped element body formed by alternately laminating dielectric layers and internal electrode layers and internal electrodes formed on the internal electrode layer at both ends of the element body are provided. A multilayer capacitor comprising a pair of external electrodes that are alternately connected in parallel, wherein the internal electrodes have two internal electrode pieces formed in the same layer and extending substantially in parallel at a predetermined interval. , The length T2 in the vertical direction of the formation region of the internal electrodes in a cross section perpendicular to the axis connecting the external electrodes at both ends.
And a thickness T3 of the internal electrode piece (T3 / T2) is set to a predetermined value within the range of 0.004 or more and 0.1 or less.

【0024】該積層コンデンサによれば、前記断面にお
ける前記内部電極の形成領域の縦方向の長さT2と前記
内部電極片の厚さT3との比(T3/T2)が0.00
4以上0.1以下の範囲内の所定値に設定されているの
で、前記内部電極片の厚みを必要十分に厚く形成できる
と共に、その抵抗を小さくすることができる。
According to the multilayer capacitor, the ratio (T3 / T2) of the longitudinal length T2 of the internal electrode formation region in the cross section to the internal electrode piece thickness T3 is 0.00.
Since it is set to a predetermined value within the range of 4 or more and 0.1 or less, the thickness of the internal electrode piece can be made sufficiently thick and the resistance thereof can be reduced.

【0025】また、請求項7では、誘電体層と内部電極
層とを交互に積層してなる直方体形状の素体と、該素体
の両端部において該内部電極層に形成された内部電極を
交互に並列に接続している一対の外部電極とからなる積
層コンデンサであって、前記内部電極は、同層内に形成
され、所定間隔をあけてほぼ平行に延びる2つの内部電
極片を有し、両端の外部電極を結ぶ軸に直角に交わる断
面において、該断面の縦方向の長さTと、前記断面内に
おける内部電極の形成領域の周縁から前記内部電極面に
平行に延びる前記断面の外辺までの距離T1との比(T
1/T)が、前記断面の横方向の長さWと、前記断面内
における内部電極の形成領域の周縁から前記内部電極面
に対して直角方向に延びる前記断面の外辺までの距離W
1との比(W1/W)とほぼ等しく設定され、これらの
比(T1/T、W1/W)が0.15以上0.4以下の
範囲内の所定値に設定されていると共に、両端の外部電
極を結ぶ軸に直角に交わる断面の縦方向の長さTと、該
断面における前記内部電極の形成領域の縦方向の長さT
2との比(T2/T)が0.2以上0.7以下の範囲内
の所定値に設定されている積層コンデンサを提案する。
According to a seventh aspect of the present invention, a rectangular parallelepiped element body formed by alternately laminating dielectric layers and internal electrode layers and internal electrodes formed on the internal electrode layer at both ends of the element body are provided. A multilayer capacitor comprising a pair of external electrodes that are alternately connected in parallel, wherein the internal electrodes have two internal electrode pieces formed in the same layer and extending substantially in parallel at a predetermined interval. , In a cross section perpendicular to the axis connecting the external electrodes at both ends, the length T in the longitudinal direction of the cross section and the outside of the cross section extending parallel to the internal electrode surface from the peripheral edge of the formation region of the internal electrode in the cross section. Ratio to the distance T1 to the side (T
1 / T) is the lateral length W of the cross section and the distance W from the peripheral edge of the internal electrode formation region in the cross section to the outer edge of the cross section extending in the direction perpendicular to the internal electrode surface.
It is set to be almost equal to the ratio (W1 / W) to 1 and these ratios (T1 / T, W1 / W) are set to a predetermined value within the range of 0.15 or more and 0.4 or less and both ends. And a longitudinal length T of a cross section perpendicular to the axis connecting the external electrodes, and a longitudinal length T of the formation region of the internal electrode in the cross section.
A multilayer capacitor having a ratio (T2 / T) with 2 set to a predetermined value within the range of 0.2 or more and 0.7 or less is proposed.

【0026】該積層コンデンサによれば、前記断面内に
おける内部電極の形成領域の周縁から前記内部電極面に
平行に延びる前記断面の外辺までの距離T1との比(T
1/T)が、前記断面の横方向の長さWと、前記断面内
における内部電極の形成領域の周縁から前記内部電極面
に対して直角方向に延びる前記断面の外辺までの距離W
1との比(W1/W)とほぼ等しく設定され、これらの
比(T1/T、W1/W)が0.15以上0.4以下の
範囲内の所定値に設定され、さらに前記断面の縦方向の
長さTと、前記内部電極の形成領域の縦方向の長さT2
との比(T2/T)が0.2以上0.7以下の範囲内の
所定値に設定されているので、素体外部に存在する導体
と内部電極片及び該内部電極面との間の距離を必要十分
に得られる。
According to the multilayer capacitor, the ratio (T) to the distance T1 from the peripheral edge of the area where the internal electrode is formed in the cross section to the outer side of the cross section extending parallel to the internal electrode surface.
1 / T) is the lateral length W of the cross section and the distance W from the peripheral edge of the internal electrode formation region in the cross section to the outer edge of the cross section extending in the direction perpendicular to the internal electrode surface.
The ratio (T1 / T, W1 / W) is set to be substantially equal to the ratio (W1 / W) to 1 and is set to a predetermined value within the range of 0.15 or more and 0.4 or less. The length T in the vertical direction and the length T2 in the vertical direction of the formation region of the internal electrode.
Since the ratio (T2 / T) is set to a predetermined value within the range of 0.2 or more and 0.7 or less, between the conductor existing outside the element body and the internal electrode piece and the internal electrode surface. You can get enough distance.

【0027】また、請求項8では、誘電体層と内部電極
層とを交互に積層してなる直方体形状の素体と、該素体
の両端部において該内部電極層に形成された内部電極を
交互に並列に接続している一対の外部電極とからなる積
層コンデンサであって、前記内部電極は、同層内に形成
され、所定間隔をあけてほぼ平行に延びる2つの内部電
極片を有し、両端の外部電極を結ぶ軸に直角に交わる断
面において、該断面の縦方向の長さTと、前記断面内に
おける内部電極の形成領域の周縁から前記内部電極面に
平行に延びる前記断面の外辺までの距離T1との比(T
1/T)が、前記断面の横方向の長さWと、前記断面内
における内部電極の形成領域の周縁から前記内部電極面
に対して直角方向に延びる前記断面の外辺までの距離W
1との比(W1/W)とほぼ等しく設定され、これらの
比(T1/T、W1/W)が0.15以上0.4以下の
範囲内の所定値に設定されていると共に、両端の外部電
極を結ぶ軸に直角に交わる断面における前記内部電極の
形成領域の縦方向の長さT2と前記内部電極片の厚さT
3との比(T3/T2)が0.004以上0.1以下の
範囲内の所定値に設定されている積層コンデンサを提案
する。
Further, according to the present invention, a rectangular parallelepiped element body formed by alternately laminating dielectric layers and internal electrode layers and internal electrodes formed on the internal electrode layer at both ends of the element body are provided. A multilayer capacitor comprising a pair of external electrodes that are alternately connected in parallel, wherein the internal electrodes have two internal electrode pieces formed in the same layer and extending substantially in parallel at a predetermined interval. , In a cross section perpendicular to the axis connecting the external electrodes at both ends, the length T in the longitudinal direction of the cross section and the outside of the cross section extending parallel to the internal electrode surface from the peripheral edge of the formation region of the internal electrode in the cross section. Ratio to the distance T1 to the side (T
1 / T) is the lateral length W of the cross section and the distance W from the peripheral edge of the internal electrode formation region in the cross section to the outer edge of the cross section extending in the direction perpendicular to the internal electrode surface.
It is set to be almost equal to the ratio (W1 / W) to 1 and these ratios (T1 / T, W1 / W) are set to a predetermined value within the range of 0.15 or more and 0.4 or less and both ends. The longitudinal length T2 of the area where the internal electrode is formed and the thickness T of the internal electrode piece in a cross section that intersects at right angles with the axis connecting the external electrodes.
A multilayer capacitor is proposed in which the ratio (T3 / T2) with respect to 3 is set to a predetermined value within the range of 0.004 or more and 0.1 or less.

【0028】該積層コンデンサによれば、前記断面内に
おける内部電極の形成領域の周縁から前記内部電極面に
平行に延びる前記断面の外辺までの距離T1との比(T
1/T)が、前記断面の横方向の長さWと、前記断面内
における内部電極の形成領域の周縁から前記内部電極面
に対して直角方向に延びる前記断面の外辺までの距離W
1との比(W1/W)とほぼ等しく設定され、これらの
比(T1/T、W1/W)が0.15以上0.4以下の
範囲内の所定値に設定され、さらに前記断面における前
記内部電極の形成領域の縦方向の長さT2と前記内部電
極片の厚さT3との比(T3/T2)が0.004以上
0.1以下の範囲内の所定値に設定されているので、素
体外部に存在する導体と内部電極片との間の距離を必要
十分に得られると共に、前記内部電極片の厚みを必要十
分に厚く形成でき、その抵抗を小さくすることができ
る。
According to the multilayer capacitor, the ratio of the distance (T1) from the peripheral edge of the area where the internal electrode is formed in the cross section to the outer edge of the cross section extending parallel to the internal electrode surface (T
1 / T) is the lateral length W of the cross section and the distance W from the peripheral edge of the internal electrode formation region in the cross section to the outer edge of the cross section extending in the direction perpendicular to the internal electrode surface.
It is set to be substantially equal to the ratio (W1 / W) to 1 and these ratios (T1 / T, W1 / W) are set to a predetermined value within the range of 0.15 or more and 0.4 or less. The ratio (T3 / T2) of the length T2 in the vertical direction of the formation region of the internal electrode and the thickness T3 of the internal electrode piece is set to a predetermined value within the range of 0.004 or more and 0.1 or less. Therefore, it is possible to obtain a necessary and sufficient distance between the conductor existing outside the element body and the internal electrode piece, and it is possible to form the internal electrode piece to a necessary and sufficient thickness and reduce its resistance.

【0029】また、請求項9では、請求項8記載の積層
コンデンサにおいて、前記両端の外部電極を結ぶ軸に直
角に交わる断面の縦方向の長さTと、該断面における前
記内部電極の形成領域の縦方向の長さT2との比(T2
/T)が0.2以上0.7以下の範囲内の所定値に設定
されている積層コンデンサを提案する。
According to a ninth aspect, in the multilayer capacitor according to the eighth aspect, a longitudinal length T of a cross section perpendicular to an axis connecting the external electrodes at both ends and a formation region of the internal electrode in the cross section. Of the vertical length of T2 (T2
We propose a multilayer capacitor in which / T) is set to a predetermined value within the range of 0.2 or more and 0.7 or less.

【0030】該積層コンデンサによれば、前記断面内に
おける内部電極の形成領域の周縁から前記内部電極面に
平行に延びる前記断面の外辺までの距離T1との比(T
1/T)が、前記断面の横方向の長さWと、前記断面内
における内部電極の形成領域の周縁から前記内部電極面
に対して直角方向に延びる前記断面の外辺までの距離W
1との比(W1/W)とほぼ等しく設定され、これらの
比(T1/T、W1/W)が0.15以上0.4以下の
範囲内の所定値に設定され、さらに前記断面における前
記内部電極の形成領域の縦方向の長さT2と前記内部電
極片の厚さT3との比(T3/T2)が0.004以上
0.1以下の範囲内の所定値に設定されると共に、前記
両端の外部電極を結ぶ軸に直角に交わる断面の縦方向の
長さTと、該断面における前記内部電極の形成領域の縦
方向の長さT2との比(T2/T)が0.2以上0.7
以下の範囲内の所定値に設定されているので、素体外部
に存在する導体と内部電極片との間の距離を必要十分に
得られると共に、前記内部電極片の厚みを必要十分に厚
く形成でき、その抵抗を小さくすることができる。
According to the multilayer capacitor, the ratio (T) to the distance T1 from the peripheral edge of the area where the internal electrode is formed in the cross section to the outer side of the cross section extending parallel to the internal electrode surface.
1 / T) is the lateral length W of the cross section and the distance W from the peripheral edge of the internal electrode formation region in the cross section to the outer edge of the cross section extending in the direction perpendicular to the internal electrode surface.
It is set to be substantially equal to the ratio (W1 / W) to 1 and these ratios (T1 / T, W1 / W) are set to a predetermined value within the range of 0.15 or more and 0.4 or less. The ratio (T3 / T2) of the length T2 in the vertical direction of the formation region of the internal electrode to the thickness T3 of the internal electrode piece is set to a predetermined value within the range of 0.004 or more and 0.1 or less. , The ratio (T2 / T) of the vertical length T of the cross section perpendicular to the axis connecting the external electrodes at both ends to the vertical length T2 of the internal electrode forming region in the cross section is 0. 2 or more 0.7
Since it is set to a predetermined value within the following range, a sufficient distance can be obtained between the conductor existing outside the element body and the internal electrode piece, and the thickness of the internal electrode piece can be formed to be sufficiently thick. Therefore, the resistance can be reduced.

【0031】また、請求項10では、請求項4乃至9の
何れかに記載の積層コンデンサにおいて、前記内部電極
片の幅Dと前記誘電体層の幅Wとの比(D/W)が0.
1以上0.4以下の範囲内の所定値に設定されている積
層コンデンサを提案する。
According to a tenth aspect of the present invention, in the multilayer capacitor according to any of the fourth to ninth aspects, the ratio (D / W) of the width D of the internal electrode piece to the width W of the dielectric layer is 0. .
We propose a multilayer capacitor set to a predetermined value within the range of 1 or more and 0.4 or less.

【0032】該積層コンデンサによれば、素体外部に存
在する導体と内部電極片との間の距離を必要十分に得ら
れ、さらに前記内部電極片の厚みを必要十分に厚く形成
でき、その抵抗を小さくすることができると共に、内部
電極片の面積、及び幅方向において内部電極片を介さず
に直接上下層の誘電体層が密着する割合が必要十分に得
られる。
According to the multilayer capacitor, a sufficient distance can be obtained between the conductor existing outside the element body and the internal electrode piece, and further, the internal electrode piece can be formed to have a necessary and sufficient thickness, and the resistance thereof can be increased. In addition, the area of the internal electrode piece and the ratio of the upper and lower dielectric layers directly contacting each other in the width direction without interposing the internal electrode piece can be obtained sufficiently.

【0033】また、請求項11では、請求項4乃至10
の何れかに記載の積層コンデンサにおいて、前記内部電
極片の長さL1と前記誘電体層の長さLとの比(L1/
L)が0.5以上0.9以下の範囲内の所定値に設定さ
れている積層コンデンサを提案する。
In the eleventh aspect, the fourth to tenth aspects are provided.
In the multilayer capacitor according to any one of items 1 to 5, the ratio of the length L1 of the internal electrode piece to the length L of the dielectric layer (L1 /
We propose a multilayer capacitor in which L) is set to a predetermined value within the range of 0.5 or more and 0.9 or less.

【0034】該積層コンデンサによれば、素体外部に存
在する導体と内部電極片との間の距離を必要十分に得ら
れ、さらに前記内部電極片の厚みを必要十分に厚く形成
でき、その抵抗を小さくすることができると共に、内部
電極片の面積、及び内部電極片を介さずに直接上下層の
誘電体層が密着する割合が必要十分に得られる。
According to the multilayer capacitor, the distance between the conductor existing outside the element body and the internal electrode piece can be obtained sufficiently, and further, the thickness of the internal electrode piece can be formed to be necessary and sufficient, and the resistance thereof can be increased. In addition, the area of the internal electrode piece and the ratio of the upper and lower dielectric layers directly adhering to each other without interposing the internal electrode piece can be sufficiently obtained.

【0035】[0035]

【発明の実施の形態】以下、図面に基づいて本発明の一
実施形態を説明する。図1は一実施形態における第1の
実施例の積層コンデンサを示す分解斜視図、図5は平断
面図、図6は図5におけるB−B線矢視方向断面図であ
る。図において、20は積層コンデンサで、誘電体層2
1と内部電極22とを交互に積層してなる素体23と、
素体23の両端部において内部電極22を交互に並列に
接続している一対の外部電極24とから構成されてい
る。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is an exploded perspective view showing a multilayer capacitor of a first example in one embodiment, FIG. 5 is a plan sectional view, and FIG. 6 is a sectional view taken along line BB in FIG. In the figure, reference numeral 20 denotes a multilayer capacitor, which is a dielectric layer 2
Element body 23 formed by alternately laminating 1 and internal electrodes 22;
It is composed of a pair of external electrodes 24 that alternately connect the internal electrodes 22 in parallel at both ends of the element body 23.

【0036】誘電体層21は、矩形のシート状のセラミ
ック焼結体からなり、焼結体は例えばチタン酸バリウム
を主成分とするグリーンシートを焼成して形成した誘電
体磁器材料からなる。
The dielectric layer 21 is made of a rectangular sheet-shaped ceramic sintered body, and the sintered body is made of a dielectric ceramic material formed by firing a green sheet containing barium titanate as a main component, for example.

【0037】誘電体層21を介して隣り合う一対の内部
電極22のそれぞれは、1つのスリット22aを介して
隣り合う2つの内部電極片22bを有している。各内部
電極片22bは矩形になっており、内部電極片22bの
長辺は外部電極24に対して略直角になっている。ま
た、同一内部電極22内の2つの内部電極片22b相互
の幅、及び誘電体層21を介して対向する内部電極22
間における内部電極片22bの幅は各々等しく形成され
ている。
Each of the pair of internal electrodes 22 adjacent to each other via the dielectric layer 21 has two internal electrode pieces 22b adjacent to each other via one slit 22a. Each internal electrode piece 22b has a rectangular shape, and the long side of the internal electrode piece 22b is substantially perpendicular to the external electrode 24. Further, the width of the two internal electrode pieces 22b in the same internal electrode 22 and the internal electrode 22 facing each other with the dielectric layer 21 in between.
The widths of the internal electrode pieces 22b between them are formed to be equal to each other.

【0038】さらに、内部電極片22bの基端部は、外
部電極24に沿って設けられた内部電極引出部22cを
介して外部電極24に接続されている。
Further, the base end portion of the internal electrode piece 22b is connected to the external electrode 24 via an internal electrode lead-out portion 22c provided along the external electrode 24.

【0039】一方、誘電体層21を介して隣り合う一対
の内部電極22において、一方の層の内部電極22の内
部電極片22bの一方の側に向いた全ての側縁部は、他
方の層の内部電極22の内部電極片22bの他方の側に
向いた全ての側縁部と対向している。
On the other hand, in the pair of internal electrodes 22 adjacent to each other with the dielectric layer 21 in between, all the side edge portions of the internal electrode 22 of one layer facing one side of the internal electrode piece 22b are the other layers. The inner electrode 22 faces all the side edges of the inner electrode piece 22b facing the other side.

【0040】これらの内部電極22は導電性ペーストの
薄膜を焼結させた金属薄膜からなり、導電性ペーストと
しては、例えばパラジウム粉末を主成分とするものが使
用されている。外部電極24も内部電極22と同様の材
料により形成され、表面には半田濡れ性をよくするため
に半田メッキが施されている。
These internal electrodes 22 are made of a metal thin film obtained by sintering a thin film of a conductive paste, and as the conductive paste, for example, one containing palladium powder as a main component is used. The external electrode 24 is also formed of the same material as the internal electrode 22, and its surface is plated with solder to improve solder wettability.

【0041】ここで、図5に示すように、内部電極片2
2bの幅Dと誘電体層21の幅Wとの比(D/W)が
0.1以上0.4以下の範囲内の所定値になると共に、
内部電極片22bの長さL1と誘電体層21の長さLと
の比(L1/L)が0.5以上0.9以下の範囲内の所
定値になるように誘電体層21の大きさ及び内部電極片
22bの形状が設定されている。
Here, as shown in FIG. 5, the internal electrode piece 2
The ratio (D / W) between the width D of 2b and the width W of the dielectric layer 21 becomes a predetermined value within the range of 0.1 or more and 0.4 or less, and
The size of the dielectric layer 21 is set so that the ratio (L1 / L) of the length L1 of the internal electrode piece 22b and the length L of the dielectric layer 21 becomes a predetermined value within the range of 0.5 or more and 0.9 or less. The shape of the inner electrode piece 22b is set.

【0042】本実施例では、D、W、L1、Lの長さを
それぞれ100μm、460μm、600μm、900
μmに設定した。
In this embodiment, the lengths of D, W, L1 and L are 100 μm, 460 μm, 600 μm and 900, respectively.
It was set to μm.

【0043】この積層コンデンサは次のようにして製造
した。まず、誘電体の原料粉末に有機バインダーを15
重量%添加し、さらに水を50重量%加え、これらをボ
ールミルに入れて十分に混合し、誘電体磁器原料のスラ
リーを作成した。
This multilayer capacitor was manufactured as follows. First, an organic binder was added to the dielectric raw material powder.
% By weight, and further 50% by weight of water, and these were put into a ball mill and mixed well to prepare a slurry of a dielectric ceramic raw material.

【0044】次に、このスラリーを真空脱泡器に入れて
脱泡した後、リバースロールコーターに入れ、ポリエス
テルフィルム上にこのスラリーからなる薄膜を形成し、
この薄膜をポリエステルフィルム上で100℃に加熱し
て乾燥させ、これを打ち抜いて、10cm角、厚さ約2
0μmのグリーンシートを得た。
Next, after putting this slurry in a vacuum defoamer to defoam it, put it in a reverse roll coater to form a thin film of this slurry on a polyester film,
This thin film is dried by heating to 100 ° C. on a polyester film, punched out, and 10 cm square, about 2 mm thick.
A green sheet of 0 μm was obtained.

【0045】一方、平均粒径が1.5μmのパラジウム
粉末10gと、エチルセルロース0.9gをブチルカル
ビトール9.1gに溶解させたものとを攪拌器に入れ、
10時間攪拌することにより内部電極用の導電性ペース
トを得た。
On the other hand, 10 g of palladium powder having an average particle diameter of 1.5 μm and 0.9 g of ethyl cellulose dissolved in 9.1 g of butyl carbitol were placed in a stirrer.
By stirring for 10 hours, a conductive paste for an internal electrode was obtained.

【0046】この後、上述した内部電極のパターンを5
0個有する各スクリーンを用いて、上記グリーンシート
の片面にこの導電性ペーストからなる内部電極のパター
ンを各々印刷し、これを乾燥させた。
After that, the internal electrode pattern described above is applied to 5
Using each of the screens having zero, a pattern of the internal electrode made of the conductive paste was printed on one surface of the green sheet, and dried.

【0047】次に、上記印刷面を上にしてグリーンシー
トを複数枚積層し、さらにこの積層物の上下両面に印刷
の施されていないグリーンシートを積層した。次いで、
この積層物を約50℃の温度で厚さ方向に約40トンの
圧力を加えて圧着させた。この後、この積層物を格子状
に裁断し、約50個の積層チップを得た。
Next, a plurality of green sheets were laminated with the printing surface facing upward, and further, unprinted green sheets were laminated on the upper and lower surfaces of this laminate. Then
This laminate was pressed at a temperature of about 50 ° C. by applying a pressure of about 40 tons in the thickness direction. Thereafter, the laminate was cut into a lattice to obtain about 50 laminated chips.

【0048】次に、この積層チップを雰囲気焼成可能な
炉に入れ、大気中で600℃まで加熱して、有機バイン
ダーを焼成させ、その後、炉の雰囲気を大気中雰囲気と
し、積層体チップの加熱温度を600℃から焼成温度の
1150℃(最高温度)を3時間保持した。この後、1
00℃/hrの速度で600℃まで降温し、室温まで冷
却して、焼結体チップを得た。
Next, this laminated chip is placed in a furnace capable of firing in an atmosphere and heated to 600 ° C. in the atmosphere to burn the organic binder, and then the atmosphere in the furnace is set in the atmosphere to heat the laminated chip. The temperature was maintained at 600 ° C. to 1150 ° C. (maximum temperature), which is the firing temperature, for 3 hours. After this, 1
The temperature was lowered to 600 ° C. at a rate of 00 ° C./hr and cooled to room temperature to obtain a sintered body chip.

【0049】次いで、内部電極が露出する焼結体チップ
の側面に銀とガラスフリットとビヒクルからなる導電性
ペーストを塗布して乾燥させ、これを大気中で800℃
の温度で15分間焼き付け、銀電極層を形成し、さらに
この上に銅を無電解メッキで被着させ、この上に電気メ
ッキ法でPb−Sn半田層を設けて、一対の外部電極を
形成した。これによって積層コンデンサが得られた。
Next, a conductive paste composed of silver, glass frit and vehicle is applied to the side surface of the sintered body chip where the internal electrodes are exposed and dried, and this is dried in air at 800 ° C.
Baking at a temperature of 15 minutes to form a silver electrode layer, further depositing copper thereon by electroless plating, and providing a Pb-Sn solder layer thereon by electroplating to form a pair of external electrodes did. As a result, a multilayer capacitor was obtained.

【0050】前述の構成よりなる積層コンデンサによれ
ば、内部電極片22bの面積、並びに幅方向及び長さ方
向において内部電極片22bを介さずに直接上下層の誘
電体層21が密着する割合が必要十分に得られるので、
クラックやデラミネーション等の構造欠陥の発生を防止
することができる。
According to the multilayer capacitor having the above-described structure, the area of the internal electrode piece 22b and the proportion of the upper and lower dielectric layers 21 directly adhering to each other in the width direction and the length direction without interposing the internal electrode piece 22b. Because you can get enough,
It is possible to prevent the occurrence of structural defects such as cracks and delamination.

【0051】次に、本発明の第2の実施例を説明する。
第2の実施例では第1の実施例の構成に加えて、図7に
示すように、断面の縦方向の長さTと、断面内における
内部電極形成領域25の周縁から内部電極面に平行に延
びる断面の外辺までの距離T1との比(T1/T)が、
断面の横方向の長さWと、内部電極形成領域25の周縁
から内部電極面に対して直角方向に延びる断面の外辺ま
での距離W1との比(W1/W)とほぼ等しく設定さ
れ、これらの比(T1/T、W1/W)が0.15以上
0.4以下の範囲内の所定値に設定されている。さらに
これと共に、断面の縦方向の長さTと、内部電極形成領
域25の縦方向の長さT2との比(T2/T)が0.2
以上0.7以下の範囲内の所定値に設定されている。
Next, a second embodiment of the present invention will be described.
In the second embodiment, in addition to the structure of the first embodiment, as shown in FIG. 7, the length T in the vertical direction of the cross section and the inner electrode forming region 25 in the cross section are parallel to the inner electrode surface. The ratio (T1 / T) with the distance T1 to the outer edge of the cross section extending to
The ratio (W1 / W) of the lateral length W of the cross section and the distance W1 from the peripheral edge of the internal electrode formation region 25 to the outer edge of the cross section extending in the direction perpendicular to the internal electrode surface is set to be substantially equal to, These ratios (T1 / T, W1 / W) are set to predetermined values within the range of 0.15 or more and 0.4 or less. Along with this, the ratio (T2 / T) of the vertical length T of the cross section to the vertical length T2 of the internal electrode forming region 25 is 0.2.
It is set to a predetermined value within the range of not less than 0.7 and not more than 0.7.

【0052】本実施例では、T1、T2、Tをそれぞれ
100μm、260μm、460μmに、またW1、W
をそれぞれ100μm、460μmに設定している。
In this embodiment, T1, T2, and T are set to 100 μm, 260 μm, and 460 μm, respectively, and W1 and W are set.
Are set to 100 μm and 460 μm, respectively.

【0053】前述の構成よりなる積層コンデンサによれ
ば、距離T1と距離Tとの比(T1/T)が、長さWと
距離W1との比(W1/W)とほぼ等しく設定され、こ
れらの比(T1/T、W1/W)が0.15以上0.4
以下の範囲内の所定値に設定されると共に、長さTと長
さT2との比(T2/T)が0.2以上0.7以下の範
囲内の所定値に設定されているため、素体23外部に存
在する回路基板等の導体と内部電極片22bとの間の距
離を必要十分に得られるので、素体23外部に存在する
導体と内部電極片22bとの間のストレー容量の発生を
抑制でき、低容量のコンデンサにおいても設計値の静電
容量を得ることができる。
According to the multilayer capacitor having the above structure, the ratio (T1 / T) between the distance T1 and the distance T is set to be substantially equal to the ratio (W1 / W) between the length W and the distance W1. Ratio (T1 / T, W1 / W) is 0.15 or more 0.4
Since the ratio (T2 / T) of the length T and the length T2 is set to a predetermined value within the range of 0.2 or more and 0.7 or less as well as being set to a predetermined value within the following range, Since a sufficient distance can be obtained between the conductor such as a circuit board existing outside the element body 23 and the internal electrode piece 22b, the stray capacitance between the conductor existing outside the element body 23 and the internal electrode piece 22b can be reduced. Generation can be suppressed, and the capacitance of the designed value can be obtained even in a low-capacity capacitor.

【0054】従って、この積層コンデンサを回路基板上
に搭載する場合、内部電極22と回路基板上の導体パタ
ーンとの間に生ずるストレー容量は、内部電極面が回路
基板と平行になるように搭載したとき、または内部電極
面が回路基板に対して垂直になるように搭載したときに
おいても、ごく微少量となると共にほぼ同程度となるの
で、回路基板上への積層コンデンサの搭載状態の違いに
よって、得られる静電容量が変化することがなく、ほぼ
規定値を得ることができる。
Therefore, when this multilayer capacitor is mounted on a circuit board, the stray capacitance generated between the internal electrode 22 and the conductor pattern on the circuit board is mounted so that the internal electrode surface is parallel to the circuit board. At this time, or even when mounted so that the internal electrode surface is perpendicular to the circuit board, it will be very small and almost the same, so depending on the mounting state of the multilayer capacitor on the circuit board, The obtained capacitance does not change, and a nearly specified value can be obtained.

【0055】次に、本発明の第3の実施例を説明する。
第3の実施例では第1又は第2の実施例の構成に加え
て、図8に示すように、断面における内部電極形成領域
25の縦方向の長さT2と内部電極片22bの厚さT3
との比(T3/T2)が0.004以上0.1以下の範
囲内の所定値に設定されている。本実施例では、T3、
T2をそれぞれ8μm、260μmに設定した。
Next, a third embodiment of the present invention will be described.
In the third embodiment, in addition to the configuration of the first or second embodiment, as shown in FIG. 8, the longitudinal length T2 of the internal electrode formation region 25 and the thickness T3 of the internal electrode piece 22b in the cross section are shown.
(T3 / T2) is set to a predetermined value within the range of 0.004 or more and 0.1 or less. In this embodiment, T3,
T2 was set to 8 μm and 260 μm, respectively.

【0056】前述の構成よりなる積層コンデンサによれ
ば、断面における内部電極形成領域25の縦方向の長さ
T2と内部電極片22bの厚さT3との比(T3/T
2)が0.004以上0.1以下の範囲内の所定値に設
定されているため、内部電極片22bの厚みを必要十分
に厚く形成できると共に、その抵抗を小さくすることが
できるので、高周波域において高いQ値を得ることがで
きる。
According to the multilayer capacitor having the above-described structure, the ratio (T3 / T) of the length T2 of the internal electrode forming region 25 in the cross section in the vertical direction to the thickness T3 of the internal electrode piece 22b is obtained.
Since 2) is set to a predetermined value within the range of 0.004 or more and 0.1 or less, the internal electrode piece 22b can be formed to a necessary and sufficient thickness, and its resistance can be reduced. A high Q value can be obtained in the range.

【0057】尚、これらの実施例は一例であり本発明が
これに限定されることはない。例えば、図9乃至図17
に示すように、同層に存在する2つの内部電極片22b
の長さや幅が異なっていても同様の効果を得ることがで
きる。
Incidentally, these embodiments are merely examples, and the present invention is not limited to these. For example, FIGS.
As shown in, two internal electrode pieces 22b existing in the same layer
The same effect can be obtained even if the length and width of the are different.

【0058】[0058]

【発明の効果】以上説明したように本発明の請求項1に
よれば、内部電極片の幅Dと誘電体層の幅Wとの比(D
/W)が0.1以上0.4以下の範囲内の所定値に設定
されているため、内部電極片の面積、及び幅方向におい
て内部電極片を介さずに直接上下層の誘電体層が密着す
る割合が必要十分に得られるので、クラックやデラミネ
ーション等の構造欠陥の発生を防止することができる。
As described above, according to the first aspect of the present invention, the ratio (D) of the width D of the internal electrode piece to the width W of the dielectric layer is set.
/ W) is set to a predetermined value within the range of 0.1 or more and 0.4 or less, the upper and lower dielectric layers can be directly formed in the area of the internal electrode piece and in the width direction without interposing the internal electrode piece. Since a sufficient adhesion ratio can be obtained, the occurrence of structural defects such as cracks and delamination can be prevented.

【0059】また、請求項2によれば、内部電極片の長
さL1と誘電体層の長さLとの比(L1/L)が0.5
以上0.9以下の範囲内の所定値に設定されているた
め、内部電極片の面積、及び長さ方向において内部電極
片を介さずに直接上下層の誘電体層が密着する割合が必
要十分に得られるので、クラックやデラミネーション等
の構造欠陥の発生を防止することができる。
According to claim 2, the ratio (L1 / L) of the length L1 of the internal electrode piece to the length L of the dielectric layer is 0.5.
Since it is set to a predetermined value within the range of 0.9 or more, the area of the internal electrode piece and the proportion of the upper and lower dielectric layers directly adhering in the length direction without interposing the internal electrode piece are necessary and sufficient. As a result, structural defects such as cracks and delamination can be prevented from occurring.

【0060】また、請求項3によれば、内部電極片の幅
Dと誘電体層の幅Wとの比(D/W)が0.1以上0.
4以下の範囲内の所定値に設定されると共に、前記内部
電極片の長さL1と前記誘電体層の長さLとの比(L1
/L)が0.5以上0.9以下の範囲内の所定値に設定
されているため、内部電極片の面積、及び内部電極片を
介さずに直接上下層の誘電体層が密着する割合が必要十
分に得られるので、クラックやデラミネーション等の構
造欠陥の発生を防止することができる。
According to the third aspect of the invention, the ratio (D / W) of the width D of the internal electrode piece to the width W of the dielectric layer is 0.1 or more.
It is set to a predetermined value within the range of 4 or less, and the ratio of the length L1 of the internal electrode piece to the length L of the dielectric layer (L1
/ L) is set to a predetermined value within the range of 0.5 or more and 0.9 or less, the area of the internal electrode piece and the ratio of the upper and lower dielectric layers directly adhering to each other without interposing the internal electrode piece. Therefore, it is possible to prevent structural defects such as cracks and delamination from occurring.

【0061】また、請求項4によれば、両端の外部電極
を結ぶ軸に直角に交わる断面内における内部電極の形成
領域の周縁から内部電極面に平行に延びる前記断面の外
辺までの距離T1との比(T1/T)が、前記断面の横
方向の長さWと、前記断面内における内部電極の形成領
域の周縁から前記内部電極面に対して直角方向に延びる
前記断面の外辺までの距離W1との比(W1/W)とほ
ぼ等しく設定され、これらの比(T1/T、W1/W)
が0.15以上0.4以下の範囲内の所定値に設定され
ているため、素体外部に存在する導体と内部電極片との
間の距離を必要十分に得られるので、前記素体外部に存
在する導体と内部電極片との間のストレー容量の発生を
抑制でき、低容量のコンデンサにおいても設計値の静電
容量を得ることができる。
Further, according to claim 4, the distance T1 from the peripheral edge of the area where the internal electrode is formed in the cross section perpendicular to the axis connecting the external electrodes at both ends to the outer edge of the cross section extending parallel to the internal electrode surface. And the ratio (T1 / T) to the lateral length W of the cross section and the outer edge of the cross section extending in the direction perpendicular to the internal electrode surface from the peripheral edge of the internal electrode formation region in the cross section. Is set to be approximately equal to the ratio of the distance W1 to W1 (W1 / W), and these ratios (T1 / T, W1 / W)
Is set to a predetermined value within the range of 0.15 or more and 0.4 or less, so that the distance between the conductor existing inside the element body and the internal electrode piece can be obtained sufficiently, It is possible to suppress the generation of stray capacitance between the conductor and the internal electrode piece existing in, and it is possible to obtain the designed capacitance even in a low-capacity capacitor.

【0062】また、請求項5によれば、両端の外部電極
を結ぶ軸に直角に交わる断面の縦方向の長さTと、該断
面内における内部電極の形成領域の縦方向の長さT2と
の比(T2/T)が0.2以上0.7以下の範囲内の所
定値に設定されているため、素体外部に存在する導体と
内部電極片の面との間の距離を必要十分に得られるの
で、前記素体外部に存在する導体と内部電極片との間の
ストレー容量の発生を抑制でき、低容量のコンデンサに
おいても設計値の静電容量を得ることができる。
According to the present invention, the length T in the vertical direction of the cross section intersecting at right angles with the axis connecting the external electrodes at both ends, and the length T2 in the vertical direction of the formation region of the internal electrode in the cross section. Since the ratio (T2 / T) is set to a predetermined value within the range of 0.2 or more and 0.7 or less, the distance between the conductor existing outside the element body and the surface of the internal electrode piece is necessary and sufficient. Therefore, it is possible to suppress the generation of stray capacitance between the conductor existing outside the element body and the internal electrode piece, and it is possible to obtain the designed capacitance even in the case of a low capacitance capacitor.

【0063】また、請求項6によれば、両端の外部電極
を結ぶ軸に直角に交わる断面における内部電極の形成領
域の縦方向の長さT2と内部電極片の厚さT3との比
(T3/T2)が0.004以上0.1以下の範囲内の
所定値に設定されているため、前記内部電極片の厚みを
必要十分に厚く形成できると共に、その抵抗を小さくす
ることができるので、高周波域において高いQ値を得る
ことができる。
According to the sixth aspect, the ratio (T3) of the vertical length T2 of the internal electrode forming region to the internal electrode piece thickness T3 in the cross section perpendicular to the axis connecting the external electrodes at both ends. Since / T2) is set to a predetermined value within the range of 0.004 or more and 0.1 or less, the internal electrode piece can be formed to have a necessary and sufficient thickness and its resistance can be reduced. A high Q value can be obtained in the high frequency range.

【0064】また、請求項7によれば、両端の外部電極
を結ぶ軸に直角に交わる断面内における内部電極の形成
領域の周縁から前記内部電極面に平行に延びる前記断面
の外辺までの距離T1との比(T1/T)が、前記断面
の横方向の長さWと、前記断面内における内部電極の形
成領域の周縁から前記内部電極面に対して直角方向に延
びる前記断面の外辺までの距離W1との比(W1/W)
とほぼ等しく設定され、これらの比(T1/T、W1/
W)が0.15以上0.4以下の範囲内の所定値に設定
され、さらに前記断面の縦方向の長さTと、前記内部電
極の形成領域の縦方向の長さT2との比(T2/T)が
0.2以上0.7以下の範囲内の所定値に設定されてい
るため、素体外部に存在する導体と内部電極片及び該内
部電極面との間の距離を必要十分に得られるので、前記
素体外部に存在する導体と内部電極片との間のストレー
容量の発生を抑制でき、低容量のコンデンサにおいても
設計値の静電容量を得ることができる。
According to claim 7, the distance from the peripheral edge of the formation region of the internal electrode in the cross section perpendicular to the axis connecting the external electrodes at both ends to the outer edge of the cross section extending parallel to the internal electrode surface. The ratio (T1 / T) to T1 is the lateral length W of the cross section and the outer edge of the cross section extending from the peripheral edge of the internal electrode formation region in the cross section in the direction perpendicular to the internal electrode surface. Ratio to distance W1 (W1 / W)
Are set to be approximately equal to and the ratio of these (T1 / T, W1 /
W) is set to a predetermined value within the range of 0.15 or more and 0.4 or less, and the ratio of the vertical length T2 of the cross section to the vertical length T2 of the internal electrode formation region ( Since T2 / T) is set to a predetermined value within the range of 0.2 or more and 0.7 or less, the distance between the conductor existing outside the element body and the internal electrode piece and the internal electrode surface is necessary and sufficient. Therefore, it is possible to suppress the generation of stray capacitance between the conductor existing outside the element body and the internal electrode piece, and it is possible to obtain the designed capacitance even in the case of a low capacitance capacitor.

【0065】また、請求項8によれば、両端の外部電極
を結ぶ軸に直角に交わる断面内における内部電極の形成
領域の周縁から前記内部電極面に平行に延びる前記断面
の外辺までの距離T1との比(T1/T)が、前記断面
の横方向の長さWと、前記断面内における内部電極の形
成領域の周縁から前記内部電極面に対して直角方向に延
びる前記断面の外辺までの距離W1との比(W1/W)
とほぼ等しく設定され、これらの比(T1/T、W1/
W)が0.15以上0.4以下の範囲内の所定値に設定
され、さらに前記断面における前記内部電極の形成領域
の縦方向の長さT2と前記内部電極片の厚さT3との比
(T3/T2)が0.004以上0.1以下の範囲内の
所定値に設定されているため、素体外部に存在する導体
と内部電極片との間の距離を必要十分に得られると共
に、前記内部電極片の厚みを必要十分に厚く形成でき、
その抵抗を小さくすることができるので、前記素体外部
に存在する導体と内部電極片との間のストレー容量の発
生を抑制でき、低容量のコンデンサにおいても設計値の
静電容量を得ることができると共に、高周波域において
高いQ値を得ることができる。
According to the eighth aspect, the distance from the peripheral edge of the internal electrode forming region in the cross section perpendicular to the axis connecting the external electrodes at both ends to the outer edge of the cross section extending parallel to the internal electrode surface. The ratio (T1 / T) to T1 is the lateral length W of the cross section and the outer edge of the cross section extending from the peripheral edge of the internal electrode formation region in the cross section in the direction perpendicular to the internal electrode surface. Ratio to distance W1 (W1 / W)
Are set to be approximately equal to and the ratio of these (T1 / T, W1 /
W) is set to a predetermined value within the range of 0.15 or more and 0.4 or less, and further, the ratio of the longitudinal length T2 of the formation region of the internal electrode in the cross section to the thickness T3 of the internal electrode piece. Since (T3 / T2) is set to a predetermined value within the range of 0.004 or more and 0.1 or less, a sufficient distance can be obtained between the conductor existing outside the element body and the internal electrode piece. , The thickness of the internal electrode piece can be formed sufficiently thick,
Since the resistance can be reduced, it is possible to suppress the generation of stray capacitance between the conductor existing outside the element body and the internal electrode piece, and it is possible to obtain the designed capacitance even in a low-capacity capacitor. In addition, it is possible to obtain a high Q value in a high frequency range.

【0066】また、請求項9によれば、上記の効果に加
えて、前記素体外部に存在する導体と内部電極片との間
のストレー容量の発生をさらに抑制でき、低容量のコン
デンサにおいても設計値の静電容量を得ることができ
る。
Further, according to claim 9, in addition to the above effects, the generation of stray capacitance between the conductor existing outside the element body and the internal electrode piece can be further suppressed, and even in a low capacitance capacitor. The designed capacitance can be obtained.

【0067】また、請求項10によれば、上記の効果に
加えて、内部電極片の幅Dと誘電体層の幅Wとの比(D
/W)が0.1以上0.4以下の範囲内の所定値に設定
されているため、内部電極片の面積、及び幅方向におい
て内部電極片を介さずに直接上下層の誘電体層が密着す
る割合が必要十分に得られるので、クラックやデラミネ
ーション等の構造欠陥の発生を防止することができる。
According to the tenth aspect, in addition to the above effect, the ratio (D) of the width D of the internal electrode piece to the width W of the dielectric layer is obtained.
/ W) is set to a predetermined value within the range of 0.1 or more and 0.4 or less, the upper and lower dielectric layers can be directly formed in the area of the internal electrode piece and in the width direction without interposing the internal electrode piece. Since a sufficient adhesion ratio can be obtained, the occurrence of structural defects such as cracks and delamination can be prevented.

【0068】また、請求項11によれば、上記の効果に
加えて、内部電極片の長さL1と誘電体層の長さLとの
比(L1/L)が0.5以上0.9以下の範囲内の所定
値に設定されているため、内部電極片の面積、及び長さ
方向において内部電極片を介さずに直接上下層の誘電体
層が密着する割合が必要十分に得られるので、クラック
やデラミネーション等の構造欠陥の発生を防止すること
ができる。
According to claim 11, in addition to the above effects, the ratio (L1 / L) of the length L1 of the internal electrode piece to the length L of the dielectric layer is 0.5 or more and 0.9 or more. Since it is set to a predetermined value within the following range, the area of the internal electrode piece and the ratio in which the upper and lower dielectric layers directly adhere to each other in the length direction without interposing the internal electrode piece can be obtained sufficiently. It is possible to prevent the occurrence of structural defects such as cracks and delamination.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の第1の実施例の積層コンデンサを示す
分解斜視図
FIG. 1 is an exploded perspective view showing a multilayer capacitor according to a first embodiment of the present invention.

【図2】従来例の積層コンデンサを示す分解斜視図FIG. 2 is an exploded perspective view showing a conventional multilayer capacitor.

【図3】従来例の積層コンデンサを示す平断面図FIG. 3 is a cross-sectional plan view showing a conventional multilayer capacitor.

【図4】図3のA−A線矢視方向断面図FIG. 4 is a sectional view taken along line AA of FIG. 3;

【図5】本発明の第1の実施例の積層コンデンサを示す
平断面図
FIG. 5 is a plan sectional view showing a multilayer capacitor of a first embodiment of the present invention.

【図6】図5におけるB−B線矢視方向断面図6 is a sectional view taken along the line BB in FIG.

【図7】本発明の第2の実施例における積層コンデンサ
の縦断面図
FIG. 7 is a vertical sectional view of a multilayer capacitor according to a second embodiment of the present invention.

【図8】本発明の第3の実施例における積層コンデンサ
の縦断面図
FIG. 8 is a vertical sectional view of a multilayer capacitor according to a third embodiment of the present invention.

【図9】本発明の他の実施例における内部電極片形状を
示す図
FIG. 9 is a diagram showing a shape of an internal electrode piece according to another embodiment of the present invention.

【図10】本発明の他の実施例における内部電極片形状
を示す図
FIG. 10 is a view showing a shape of an internal electrode piece according to another embodiment of the present invention.

【図11】本発明の他の実施例における内部電極片形状
を示す図
FIG. 11 is a view showing a shape of an internal electrode piece according to another embodiment of the present invention.

【図12】本発明の他の実施例における内部電極片形状
を示す図
FIG. 12 is a diagram showing a shape of an internal electrode piece according to another embodiment of the present invention.

【図13】本発明の他の実施例における内部電極片形状
を示す図
FIG. 13 is a view showing a shape of an internal electrode piece according to another embodiment of the present invention.

【図14】本発明の他の実施例における内部電極片形状
を示す図
FIG. 14 is a diagram showing a shape of an internal electrode piece according to another embodiment of the present invention.

【図15】本発明の他の実施例における内部電極片形状
を示す図
FIG. 15 is a view showing the shape of an internal electrode piece according to another embodiment of the present invention.

【図16】本発明の他の実施例における内部電極片形状
を示す図
FIG. 16 is a diagram showing a shape of an internal electrode piece according to another embodiment of the present invention.

【図17】本発明の他の実施例における内部電極片形状
を示す図
FIG. 17 is a diagram showing the shape of internal electrode pieces in another embodiment of the present invention.

【符号の説明】[Explanation of symbols]

20…積層コンデンサ、21…誘電体層、22…内部電
極、22a…スリット、22b…内部電極片、22c…
内部電極引出部、23…素体、24…外部電極、25…
内部電極形成領域。
20 ... Multilayer capacitor, 21 ... Dielectric layer, 22 ... Internal electrode, 22a ... Slit, 22b ... Internal electrode piece, 22c ...
Internal electrode lead-out portion, 23 ... Element body, 24 ... External electrode, 25 ...
Internal electrode formation area.

Claims (11)

【特許請求の範囲】[Claims] 【請求項1】 誘電体層と内部電極層とを交互に積層し
てなる直方体形状の素体と、該素体の両端部において該
内部電極層に形成された内部電極を交互に並列に接続し
ている一対の外部電極とからなる積層コンデンサであっ
て、 前記内部電極は、同層内に形成され、所定間隔をあけて
ほぼ平行に延びる2つの内部電極片を有し、 前記内部電極片の幅Dと前記誘電体層の幅Wとの比(D
/W)が0.1以上0.4以下の範囲内の所定値に設定
されていることを特徴とする積層コンデンサ。
1. A rectangular parallelepiped element body in which dielectric layers and internal electrode layers are alternately laminated, and internal electrodes formed on the internal electrode layers at both ends of the element body are alternately connected in parallel. And a pair of external electrodes, the internal electrode having two internal electrode pieces formed in the same layer and extending substantially in parallel with each other at a predetermined interval. Of the width D of the dielectric layer to the width W of the dielectric layer (D
/ W) is set to a predetermined value within the range of 0.1 or more and 0.4 or less.
【請求項2】 誘電体層と内部電極層とを交互に積層し
てなる直方体形状の素体と、該素体の両端部において該
内部電極層に形成された内部電極を交互に並列に接続し
ている一対の外部電極とからなる積層コンデンサであっ
て、 前記内部電極は、同層内に形成され、所定間隔をあけて
ほぼ平行に延びる2つの内部電極片を有し、 前記内部電極片の長さL1と前記誘電体層の長さLとの
比(L1/L)が0.5以上0.9以下の範囲内の所定
値に設定されていることを特徴とする積層コンデンサ。
2. A rectangular parallelepiped element body in which dielectric layers and internal electrode layers are alternately laminated, and internal electrodes formed on the internal electrode layers at both ends of the element body are alternately connected in parallel. And a pair of external electrodes, the internal electrode having two internal electrode pieces formed in the same layer and extending substantially in parallel with each other at a predetermined interval. The multilayer capacitor, wherein the ratio (L1 / L) between the length L1 of the dielectric layer and the length L of the dielectric layer is set to a predetermined value within the range of 0.5 or more and 0.9 or less.
【請求項3】 誘電体層と内部電極層とを交互に積層し
てなる直方体形状の素体と、該素体の両端部において該
内部電極層に形成された内部電極を交互に並列に接続し
ている一対の外部電極とからなる積層コンデンサであっ
て、 前記内部電極は、同層内に形成され、所定間隔をあけて
ほぼ平行に延びる2つの内部電極片を有し、 前記内部電極片の幅Dと前記誘電体層の幅Wとの比(D
/W)が0.1以上0.4以下の範囲内の所定値に設定
されると共に、 前記内部電極片の長さL1と前記誘電体層の長さLとの
比(L1/L)が0.5以上0.9以下の範囲内の所定
値に設定されていることを特徴とする積層コンデンサ。
3. A rectangular parallelepiped shaped element body in which dielectric layers and internal electrode layers are alternately laminated, and internal electrodes formed in the internal electrode layers at both ends of the element body are alternately connected in parallel. And a pair of external electrodes, the internal electrode having two internal electrode pieces formed in the same layer and extending substantially in parallel with each other at a predetermined interval. Of the width D of the dielectric layer to the width W of the dielectric layer (D
/ W) is set to a predetermined value within the range of 0.1 or more and 0.4 or less, and the ratio (L1 / L) between the length L1 of the internal electrode piece and the length L of the dielectric layer is A multilayer capacitor, which is set to a predetermined value within a range of 0.5 or more and 0.9 or less.
【請求項4】 誘電体層と内部電極層とを交互に積層し
てなる直方体形状の素体と、該素体の両端部において該
内部電極層に形成された内部電極を交互に並列に接続し
ている一対の外部電極とからなる積層コンデンサであっ
て、 前記内部電極は、同層内に形成され、所定間隔をあけて
ほぼ平行に延びる2つの内部電極片を有し、 両端の外部電極を結ぶ軸に直角に交わる断面において、
該断面の縦方向の長さTと、前記断面内における内部電
極の形成領域の周縁から前記内部電極面に平行に延びる
前記断面の外辺までの距離T1との比(T1/T)が、
前記断面の横方向の長さWと、前記断面内における内部
電極の形成領域の周縁から前記内部電極面に対して直角
方向に延びる前記断面の外辺までの距離W1との比(W
1/W)とほぼ等しく設定され、 これらの比(T1/T、W1/W)が0.15以上0.
4以下の範囲内の所定値に設定されていることを特徴と
する積層コンデンサ。
4. A rectangular parallelepiped element body in which dielectric layers and internal electrode layers are alternately laminated and internal electrodes formed on the internal electrode layers at both ends of the element body are alternately connected in parallel. And a pair of external electrodes, the internal electrode having two internal electrode pieces formed in the same layer and extending substantially in parallel at a predetermined interval. In the cross section that intersects at right angles to the axis connecting
The ratio (T1 / T) of the length T in the vertical direction of the cross section to the distance T1 from the peripheral edge of the formation region of the internal electrode in the cross section to the outer side of the cross section extending parallel to the internal electrode surface is
The ratio (W) of the lateral length W of the cross section and the distance W1 from the peripheral edge of the formation region of the internal electrode in the cross section to the outer side of the cross section extending in the direction perpendicular to the internal electrode surface.
1 / W) and the ratio (T1 / T, W1 / W) of these is 0.15 or more and 0.1.
A multilayer capacitor, which is set to a predetermined value within a range of 4 or less.
【請求項5】 誘電体層と内部電極層とを交互に積層し
てなる直方体形状の素体と、該素体の両端部において該
内部電極層に形成された内部電極を交互に並列に接続し
ている一対の外部電極とからなる積層コンデンサであっ
て、 前記内部電極は、同層内に形成され、所定間隔をあけて
ほぼ平行に延びる2つの内部電極片を有し、 両端の外部電極を結ぶ軸に直角に交わる断面の縦方向の
長さTと、該断面における前記内部電極の形成領域の縦
方向の長さT2との比(T2/T)が0.2以上0.7
以下の範囲内の所定値に設定されていることを特徴とす
る積層コンデンサ。
5. A rectangular parallelepiped shaped element body in which dielectric layers and internal electrode layers are alternately laminated, and internal electrodes formed on the internal electrode layers at both ends of the element body are alternately connected in parallel. And a pair of external electrodes, the internal electrode having two internal electrode pieces formed in the same layer and extending substantially in parallel at a predetermined interval. The ratio (T2 / T) of the vertical length T of the cross section that intersects at right angles to the axis connecting the two and the vertical length T2 of the internal electrode formation region in the cross section is 0.2 or more and 0.7.
A multilayer capacitor, which is set to a predetermined value within the following range.
【請求項6】 誘電体層と内部電極層とを交互に積層し
てなる直方体形状の素体と、該素体の両端部において該
内部電極層に形成された内部電極を交互に並列に接続し
ている一対の外部電極とからなる積層コンデンサであっ
て、 前記内部電極は、同層内に形成され、所定間隔をあけて
ほぼ平行に延びる2つの内部電極片を有し、 両端の外部電極を結ぶ軸に直角に交わる断面における前
記内部電極の形成領域の縦方向の長さT2と前記内部電
極片の厚さT3との比(T3/T2)が0.004以上
0.1以下の範囲内の所定値に設定されていることを特
徴とする積層コンデンサ。
6. A rectangular parallelepiped element body in which dielectric layers and internal electrode layers are alternately laminated and internal electrodes formed on the internal electrode layers at both ends of the element body are alternately connected in parallel. And a pair of external electrodes, the internal electrode having two internal electrode pieces formed in the same layer and extending substantially in parallel at a predetermined interval. The ratio (T3 / T2) of the longitudinal length T2 of the internal electrode forming region and the thickness T3 of the internal electrode piece in the cross section intersecting at right angles to the axis connecting the lines is 0.004 or more and 0.1 or less. The multilayer capacitor is characterized in that it is set to a predetermined value.
【請求項7】 誘電体層と内部電極層とを交互に積層し
てなる直方体形状の素体と、該素体の両端部において該
内部電極層に形成された内部電極を交互に並列に接続し
ている一対の外部電極とからなる積層コンデンサであっ
て、 前記内部電極は、同層内に形成され、所定間隔をあけて
ほぼ平行に延びる2つの内部電極片を有し、 両端の外部電極を結ぶ軸に直角に交わる断面において、
該断面の縦方向の長さTと、前記断面内における内部電
極の形成領域の周縁から前記内部電極面に平行に延びる
前記断面の外辺までの距離T1との比(T1/T)が、
前記断面の横方向の長さWと、前記断面内における内部
電極の形成領域の周縁から前記内部電極面に対して直角
方向に延びる前記断面の外辺までの距離W1との比(W
1/W)とほぼ等しく設定され、 これらの比(T1/T、W1/W)が0.15以上0.
4以下の範囲内の所定値に設定されていると共に、 両端の外部電極を結ぶ軸に直角に交わる断面の縦方向の
長さTと、該断面における前記内部電極の形成領域の縦
方向の長さT2との比(T2/T)が0.2以上0.7
以下の範囲内の所定値に設定されていることを特徴とす
る積層コンデンサ。
7. A rectangular parallelepiped element body in which dielectric layers and internal electrode layers are alternately laminated and internal electrodes formed on the internal electrode layers at both ends of the element body are alternately connected in parallel. And a pair of external electrodes, the internal electrode having two internal electrode pieces formed in the same layer and extending substantially in parallel at a predetermined interval. In the cross section that intersects at right angles to the axis connecting
The ratio (T1 / T) of the length T in the vertical direction of the cross section to the distance T1 from the peripheral edge of the formation region of the internal electrode in the cross section to the outer side of the cross section extending parallel to the internal electrode surface is
The ratio (W) of the lateral length W of the cross section and the distance W1 from the peripheral edge of the formation region of the internal electrode in the cross section to the outer side of the cross section extending in the direction perpendicular to the internal electrode surface.
1 / W) and the ratio (T1 / T, W1 / W) of these is 0.15 or more and 0.1.
It is set to a predetermined value within the range of 4 or less, and the length T in the vertical direction of a cross section intersecting at right angles with the axis connecting the external electrodes at both ends, and the length in the vertical direction of the formation region of the internal electrode in the cross section Ratio with T2 (T2 / T) is 0.2 or more and 0.7
A multilayer capacitor, which is set to a predetermined value within the following range.
【請求項8】 誘電体層と内部電極層とを交互に積層し
てなる直方体形状の素体と、該素体の両端部において該
内部電極層に形成された内部電極を交互に並列に接続し
ている一対の外部電極とからなる積層コンデンサであっ
て、 前記内部電極は、同層内に形成され、所定間隔をあけて
ほぼ平行に延びる2つの内部電極片を有し、 両端の外部電極を結ぶ軸に直角に交わる断面において、
該断面の縦方向の長さTと、前記断面内における内部電
極の形成領域の周縁から前記内部電極面に平行に延びる
前記断面の外辺までの距離T1との比(T1/T)が、
前記断面の横方向の長さWと、前記断面内における内部
電極の形成領域の周縁から前記内部電極面に対して直角
方向に延びる前記断面の外辺までの距離W1との比(W
1/W)とほぼ等しく設定され、 これらの比(T1/T、W1/W)が0.15以上0.
4以下の範囲内の所定値に設定されていると共に、 両端の外部電極を結ぶ軸に直角に交わる断面における前
記内部電極の形成領域の縦方向の長さT2と前記内部電
極片の厚さT3との比(T3/T2)が0.004以上
0.1以下の範囲内の所定値に設定されていることを特
徴とする積層コンデンサ。
8. A rectangular parallelepiped element body in which dielectric layers and internal electrode layers are alternately laminated, and internal electrodes formed on the internal electrode layers at both ends of the element body are alternately connected in parallel. And a pair of external electrodes, the internal electrode having two internal electrode pieces formed in the same layer and extending substantially in parallel at a predetermined interval. In the cross section that intersects at right angles to the axis connecting
The ratio (T1 / T) of the length T in the vertical direction of the cross section to the distance T1 from the peripheral edge of the formation region of the internal electrode in the cross section to the outer side of the cross section extending parallel to the internal electrode surface is
The ratio (W) of the lateral length W of the cross section and the distance W1 from the peripheral edge of the formation region of the internal electrode in the cross section to the outer side of the cross section extending in the direction perpendicular to the internal electrode surface.
1 / W) and the ratio (T1 / T, W1 / W) of these is 0.15 or more and 0.1.
It is set to a predetermined value within the range of 4 or less, and the length T2 in the vertical direction of the formation region of the internal electrode and the thickness T3 of the internal electrode piece in the cross section perpendicular to the axis connecting the external electrodes at both ends. A multilayer capacitor having a ratio (T3 / T2) to a predetermined value within a range of 0.004 or more and 0.1 or less.
【請求項9】 前記両端の外部電極を結ぶ軸に直角に交
わる断面の縦方向の長さTと、該断面における前記内部
電極の形成領域の縦方向の長さT2との比(T2/T)
が0.2以上0.7以下の範囲内の所定値に設定されて
いることを特徴とする請求項8記載の積層コンデンサ。
9. A ratio (T2 / T) of a vertical length T of a cross section perpendicular to an axis connecting the external electrodes at both ends and a vertical length T2 of a region where the internal electrode is formed in the cross section. )
9. The multilayer capacitor according to claim 8, wherein is set to a predetermined value within the range of 0.2 or more and 0.7 or less.
【請求項10】 前記内部電極片の幅Dと前記誘電体層
の幅Wとの比(D/W)が0.1以上0.4以下の範囲
内の所定値に設定されていることを特徴とする請求項4
乃至9の何れかに記載の積層コンデンサ。
10. The ratio (D / W) of the width D of the internal electrode piece to the width W of the dielectric layer is set to a predetermined value within a range of 0.1 or more and 0.4 or less. Claim 4 characterized by the above-mentioned.
10. The multilayer capacitor according to any one of 9 to 9.
【請求項11】 前記内部電極片の長さL1と前記誘電
体層の長さLとの比(L1/L)が0.5以上0.9以
下の範囲内の所定値に設定されていることを特徴とする
請求項4乃至10の何れかに記載の積層コンデンサ。
11. A ratio (L1 / L) between the length L1 of the internal electrode piece and the length L of the dielectric layer is set to a predetermined value within a range of 0.5 or more and 0.9 or less. The multilayer capacitor according to any one of claims 4 to 10, characterized in that.
JP28012495A 1995-10-27 1995-10-27 Laminated capacitor Withdrawn JPH09129477A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP28012495A JPH09129477A (en) 1995-10-27 1995-10-27 Laminated capacitor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP28012495A JPH09129477A (en) 1995-10-27 1995-10-27 Laminated capacitor

Publications (1)

Publication Number Publication Date
JPH09129477A true JPH09129477A (en) 1997-05-16

Family

ID=17620676

Family Applications (1)

Application Number Title Priority Date Filing Date
JP28012495A Withdrawn JPH09129477A (en) 1995-10-27 1995-10-27 Laminated capacitor

Country Status (1)

Country Link
JP (1) JPH09129477A (en)

Cited By (8)

* Cited by examiner, † Cited by third party
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WO2003063185A3 (en) * 2002-01-25 2004-03-18 Epcos Ag Electroceramic component comprising inner electrodes
US7067172B2 (en) * 2002-04-15 2006-06-27 Avx Corporation Component formation via plating technology
US7152291B2 (en) 2002-04-15 2006-12-26 Avx Corporation Method for forming plated terminations
WO2007020757A1 (en) * 2005-08-19 2007-02-22 Murata Manufacturing Co., Ltd. Multilayer ceramic capacitor
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