JPH09252080A - High-frequency integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enhance a wire bonding operation in reliability in a manufacturing process of a high-frequency integrated circuit which deals with a UHF band, a microwave band, a milliwave band, a sub-milliwave band or the like, by a method wherein solder is prevented from flowing to an unnecessary part when a space between parts is narrow. SOLUTION: An integrated circuit is equipped with a dielectric board 1, a first part (FET) 5 and a second part (chip capacitor) 6 formed on the board 1, conductors 3a, 3b, 4a, and 4b provided onto the board 1, and a metal wire 7a which connects the first board 5 electrically with the conductor 4a, wherein a protrusion 9 of silicon nitride film is provided onto the conductor 4a so as to prevent solder 8b for fixing the second part 6 from reaching a joint between the metal wire 7a and the conductor 4a.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high frequency integrated circuit used in a high frequency band such as the UHF band, the microwave band, the millimeter wave band and the submillimeter wave band, and more particularly to the improvement of its integration degree.

[0002]

2. Description of the Related Art A conventional example of this type of high frequency integrated circuit will be described. FIG. 11 is a perspective view showing the configuration of the high-frequency integrated circuit shown on page 91 of Proceedings of the Electronics, Information and Communication Engineers General Conference Proceedings Electronics 1, for example, 1995. In the figure, 1 is a dielectric substrate, 2 is a ground conductor, 3a and 3b are first gold conductors, 4a and 4b are second gold conductors, 5 is FET, 6 is a chip capacitor, 7a and 7a.
b is a gold wire, and 8a, 8b and 8c are solders. The FET 5 is fixed onto the first gold conductor 3a by the solder 8a, and the second gold conductors 4a and 4b adjacent to the FET 5 are fixed.
The chip capacitor 6 is similarly fixed on the top by solders 8b and 8c. Further, the upper electrode of the FET 5 and the second gold conductor 4a are connected by using the gold wire 7a, and the other upper electrode of the FET 5 and the first gold conductor 3b are connected.
And are connected using a gold wire 7b. Here, the notation of a bias circuit that applies a bias for driving the FET 5 is omitted.

Next, the operation will be described. A DC voltage is generated because a bias voltage is applied to drive the FET 5, but a DC cutting capacitor is provided around the electrode of the FET 5 to prevent the DC current from flowing to other parts of the circuit. Will be needed. Here, this is realized by the chip capacitor 6. The chip capacitor 6 is F
It is installed between the second gold conductor 4a connected to the electrode of ET5 and the second gold conductor 4b connected to another circuit.

[0004]

By the way, in FIG. 11, when the length of the second gold conductor 4a existing between the FET 5 and the chip capacitor 6 is irrelevant in terms of high frequency, miniaturization of the entire circuit is achieved. In order to do so, the length should be short. For example, the configuration shown in FIG. 12 is desirable. However, in the high frequency integrated circuit of FIG. 12, the solder 8b used for fixing the chip capacitor 6 may spread to the portion to which the gold wire 7a should be connected. This state is shown in FIG.
3 is shown. In this way, FET 5 and chip capacitor 6
, The gold wire 7a from the upper electrode of the FET 5 is connected to the second gold conductor 4a near the chip capacitor 6 at a connection point (P in FIG. 13) of the solder 8b.
It may be on top. Such a state is particularly likely to occur in a case where the work of connecting the gold wire 7a is performed after the FET 5 and the chip capacitor 6 are soldered in the automatic machine work. By crimping using heat or ultrasonic waves, strong crimping can be performed between the gold conductor and the gold wire, but since the adhesion between the solder and the gold wire is weak, it may easily peel off. However, there was a problem of lack of reliability.

On the other hand, if the distance between the FET 5 and the chip capacitor 6 is made longer than necessary as shown in FIG. 11, the high frequency integrated circuit may become large. Further, there is a problem that the characteristics are deteriorated in a high frequency signal.

In order to avoid this problem, in the high frequency integrated circuit of FIG. 12, a method of soldering the FET 5 and first connecting the gold wire 7a and then soldering the chip capacitor 6 is also conceivable. In this case, However, there is a problem that the soldering process is required twice and the working time becomes long.

The present invention has been made to solve the above-mentioned problems, and provides a high-frequency integrated circuit which has a small size and which can avoid crimping a gold wire to solder and has high reliability. The purpose is to

[0008]

A high frequency integrated circuit according to a first aspect of the present invention includes a dielectric substrate, a first component and a second component provided on the dielectric substrate, and the dielectric substrate on the dielectric substrate. In a high-frequency integrated circuit including a formed conductor and a metal wire that electrically connects the first component to the conductor, a bonding material for fixing the second component is provided on the conductor. A convex portion is provided to block the bonding material so as not to reach the connection point between the metal wire and the conductor.

The first component and the second component are chip components and the like, for example, gold-tin (Au-Sn), indium-lead (In-Pb), indium-lead-silver (In).
-Pb-In) or other alloy solder. The metal wire is, for example, a gold wire, and is connected to the conductor such as gold by means such as thermocompression bonding or ultrasonic pressure bonding. The convex portion provided between the connection point between the second component, the metal wire and the conductor prevents the bonding material such as alloy solder from flowing and spreading on the conductor, Preventing reaching the connection point with the conductor.

In the high frequency integrated circuit according to a second aspect of the present invention, the convex portion is formed by a passivation film.

The passivation film is a device protection film made of silicon oxide (SiO ₂ ), a silicon nitride film or the like, and is usually formed over the entire integrated circuit. However, in the present invention, by forming only on the conductor, the bonding material is prevented from flowing and spreading on the conductor.

In the high frequency integrated circuit according to a third aspect of the present invention, the convex portion is formed by thermocompression bonding a gold ribbon to the conductor.

In the high frequency integrated circuit according to a fourth aspect of the present invention, the convex portion is an air bridge formed by separating a part of the conductor from the dielectric substrate.

The air bridge is a bridge-like portion formed by lifting the conductor. Normally, there is a space between the conductor and the dielectric substrate, but in the present invention, it is sufficient if a convex portion can be formed, and this portion may be a space or filled with some substance, whichever is desired. Good.

A high frequency integrated circuit according to a fifth aspect of the present invention includes a dielectric substrate, a first component and a second component provided on the dielectric substrate, and a conductor formed on the dielectric substrate.
In a high-frequency integrated circuit including a metal wire that electrically connects the first component to the conductor, a bonding material for fixing the second component on the conductor is the metal wire and the conductor. The recess is provided so as to block the bonding material so as not to reach the connection point.

The bonding material accumulates in the recess. This prevents the joining material such as alloy solder from flowing and spreading on the conductor, and preventing it from reaching the connection point between the metal wire and the conductor.

According to a sixth aspect of the present invention, there is provided a high frequency integrated circuit, wherein a base metal layer is provided between the dielectric substrate and the conductor, and the recess is formed by removing a part of the conductor.

A high frequency integrated circuit according to a seventh aspect of the present invention comprises a base metal layer and a resistance layer between the dielectric substrate and the conductor, and the recess is formed by removing a part of the conductor. is there.

A high frequency integrated circuit according to an eighth aspect of the present invention is a dielectric substrate, a first component and a second component provided on the dielectric substrate, a conductor formed on the dielectric substrate.
In a high-frequency integrated circuit including a metal wire that electrically connects the first component to the conductor, a bonding material for fixing the second component on the conductor is the metal wire and the conductor. A narrow portion is provided to block the above-mentioned bonding material so as not to reach the connection point.

The joining material such as solder flowing on the conductor has a certain viscosity. When reaching the narrow portion, the bonding material stops flowing due to the surface tension. Therefore, the narrow portion prevents the bonding material from reaching the connection point between the metal wire and the conductor. The width of the narrow portion is set to such a degree that the flow can be blocked in relation to the degree of viscosity of the bonding material. For example, the conductor has a width of 100 to 600 μm, and the bonding material is gold-tin (Au—Sn) or indium-lead (In-P).
b), when using an alloy solder such as indium-lead-silver (In-Pb-In), the width of the narrow portion may be, for example, about half the width of the conductor.

According to a ninth aspect of the high frequency integrated circuit of the present invention, the narrow portion is formed by removing a part of the conductor to narrow the width.

If a part of the conductor is removed to reduce the width, the narrow portion can be formed at the same time when the conductor pattern is formed. As for the shape when a part of the conductor is removed, the portions on both sides thereof may be removed, or the intermediate portion may be removed. Further, the portion to be removed may be one place or plural places.

A high frequency integrated circuit according to a tenth aspect of the present invention is a dielectric substrate, a first component and a second component provided on the dielectric substrate, a conductor formed on the dielectric substrate, and In a high-frequency integrated circuit including a metal wire that electrically connects the first component to the conductor, the bonding material for fixing the second component does not reach the connection point between the metal wire and the conductor. As described above, the metal block for soldering the bonding material is soldered to the conductor, and the metal wire is connected to the metal block.

A high frequency integrated circuit according to an eleventh aspect of the present invention is a dielectric substrate, a first component and a second component provided on the dielectric substrate, a conductor formed on the dielectric substrate, and In a high-frequency integrated circuit including a metal wire that electrically connects the first component to the conductor, the bonding material for fixing the second component does not reach the connection point between the metal wire and the conductor. As described above, the conductor is provided with a gold ribbon thermocompression bonded to the conductor, and the metal wire is connected to the gold ribbon.

[0025]

BEST MODE FOR CARRYING OUT THE INVENTION

First Embodiment of the Invention 1 is a perspective view showing the configuration of a high frequency integrated circuit according to a first embodiment of the invention. In the figure,
Reference numeral 1 is a dielectric substrate, 2 is a ground conductor provided on one surface (back surface in the figure) of the dielectric substrate 1, and 3a and 3b are provided on the other surface (front surface in the figure) of the dielectric substrate 1. The first gold conductors 4a and 4b are second gold conductors provided on the same surface, 5 is a transistor (FET) provided on the first gold conductor 3a, and 6 is a second gold conductor 4a. 4b is a chip capacitor provided so as to be connected to 4b, and 7a is a second
A gold wire connecting the gold conductor 4a and the FET 5, and a gold wire 7b connecting the first gold conductor 3b and the FET 5,
a is a solder for fixing the FET 5 to the first gold conductor 3a, 8b and 8c are solders for fixing the chip capacitor 6 to the second gold conductors 4a, 4b, and 9 is on the second gold conductor 4a. It is a layer (SiN layer) of a silicon nitride film provided. Note that 9 may be polyimide.

The width of the first gold conductors 3a, 3b and the second gold conductors 4a, 4b is, for example, about 100 to 600 μm. The solders 8a, 8b, 8c are, for example, gold-tin (Au).
-Sn), indium-lead (In-Pb), indium-lead-silver (In-Pb-In), and other alloy solders. These solders have higher viscosity than general tin-lead alloy solders. The SiN layer 9 is provided between the gold wire 7a and the chip capacitor 6 and prevents the solder 8b from flowing to the gold wire 7a side. The SiN layer (polyimide) 9 plays a role of a breakwater of the solder 8b, so to speak.

The circuit shown in FIG. 1 is a part of a high frequency integrated circuit, which amplifies a signal input by the FET 5 and outputs it via a chip capacitor 6.
The circuit of FIG. 1 is merely an example, and is merely selected for convenience of explanation of the first embodiment of the present invention. Further, the description of the bias circuit for applying the bias to the FET 5 is omitted here. FIG.
FIG. 3 is a sectional view taken along the line AA ′ in FIG. 1. As can be seen from FIG. 2, the solder 8b is blocked by the SiN layer 9 and does not flow to the gold wire 7a side. The manufacturing process of the SiN layer (polyimide) 9 is as follows. (1) A SiN layer is formed on the entire surface of a substrate on which a metal pattern has been vapor-deposited (or paste polyimide is applied and then heated and cured). (2) A resist layer (not shown) is formed on the entire surface. The resist layer is for forming a predetermined pattern, and is like rubber used for negatives. That is, the resist layer has a shape corresponding to the shape of the SiN layer (polyimide) 9 shown in FIG. (3) Etching is performed using this resist layer as a mask to remove unnecessary portions of the resist layer and the SiN layer (polyimide) together. If photosensitive polyimide is used, there is no need to form a resist layer, but the reliability may be poor. Therefore, when high reliability is not required, photosensitive polyimide can be used. The SiN layer (polyimide) 9 formed in the above steps has a thickness of, for example, about 1.5 to 3 μm. The width is, for example, about 100 μm, but a desired pattern can be formed by appropriately changing the resist pattern.

The FET 5 is soldered 8a on the first gold conductor 3a.
Then, the chip capacitor 6 is similarly soldered on the second gold conductors 4a and 4b by the solders 8b and 8c. Here, the FET 5 on the second gold conductor 4a
Since the SiN layer (polyimide) 9 used for the passivation film is provided on the side and the solder 8b used for fixing the chip capacitor 6 does not spread in this direction, the gold wire 7a from the upper electrode of the FET 5 is It can be easily connected to the second gold conductor 4a.

Although the FET and the chip capacitor are used as the chip parts here, the same effect can be obtained even if other chip parts are used.

Although SiN is used as the passivation film here, the same effect can be obtained by using other types of passivation films used for the same purpose such as silicon oxide (SiO ₂ ), nitride, and polyimide. Play. It should be noted that since polyimide takes less time to remove than silicon oxide, the layer can be made thicker. Also, cracks are less likely to occur.

Embodiment 2 of the Invention FIG. 3 is a sectional view showing a configuration of a high frequency integrated circuit according to a second embodiment of the invention.
FIG. 3 is a sectional view similar to FIG. In the figure, 10
Is a gold ribbon provided on the second gold conductor 4a. The gold ribbon 10 is provided between the gold wire 7a and the chip capacitor 9 in a direction orthogonal to the direction of the second gold conductor 4a, and prevents the solder 8b from flowing to the gold wire 7a side.

In the first embodiment of the invention, the passivation film prevents the solder 8b used for fixing the chip capacitor 6 from spreading to the FET 5 side.
Here, the gold ribbon 1 thermocompression-bonded on the second gold conductor 4a
0 prevents the solder 8b from spreading. Since the second embodiment of the present invention does not complicate the manufacturing process, it can be configured relatively easily as compared with the first embodiment of the invention.

Although the FET and the chip capacitor are used as the chip parts here, the same effect can be obtained even if other chip parts are used.

Embodiment 3 of the Invention FIG. 4 is a sectional view showing the configuration of the high frequency integrated circuit according to the third embodiment of the invention.
In the figure, 11 is an air bridge formed by lifting a part of the second gold conductor 4a in a bridge shape. There is a space between the air bridge 11 and the dielectric substrate 1. This space may be a hollow space surrounded by four sides or may be an open space. Also, the dielectric 1 has a convex portion,
The space may be filled with a dielectric. It may also be filled with another substance, for example SiN. The point is that the second gold conductor 4a may be provided with a convex portion for preventing the solder 8b from spreading.

In the first embodiment of the invention, the solder 8b used for fixing the chip capacitor 6 is prevented from spreading to the FET 5 side by the passivation film, but here, the solder 8b between the chip capacitor 6 and the gold wire 7a is prevented. The second gold conductor 4a is provided with the air bridge 11 having the same shape as the SiN layer 9 of FIG. 1 to prevent the solder 8b from spreading. An example of a method for manufacturing the air bridge 11 will be described. (1) A metal pattern other than the portion to be the air bridge 11 is vapor-deposited in a normal process. (2) A resist layer (not shown) is applied to the lower part where the air bridge 11 crosses. (3) A metal pattern (“gold” in the case of FIG. 4) to be the air bridge 11 is deposited. (4) The resist layer under the air bridge 11 is removed by etching. Then, the resist layer below the gold conductor 4a disappears, and the air bridge 11 becomes hollow. Through the above steps, for example, the size is 30 μm and the length is 100 μm.
An air bridge of about m can be formed.

Although the FET and the chip capacitor are used as the chip parts here, the same effect can be obtained by using other chip parts. 5 is a sectional view showing a structure of a high frequency integrated circuit according to a fifth embodiment of the invention.

Embodiment 4 of the Invention FIG. 5 is a sectional view showing a structure of a high frequency integrated circuit according to a fourth embodiment of the invention.
In the figure, reference numeral 12 is a base metal layer provided on the dielectric substrate 1. The underlying metal layer 12 is for facilitating vapor deposition of a metal film, and chromium, nichrome, or the like is used for this.

In the first embodiment of the invention, the passivation film prevents the solder 8b used for fixing the chip capacitor 6 from spreading to the FET 5 side.
Here, the dielectric substrate 1 in which the underlying metal layer 12 is provided below the first gold conductors 3a and 3b and the second gold conductors 4a and 4b is used, and the chip capacitor 6 of the second gold conductors 4a is used. By removing the portion between the gold wire 7a and the gold wire 7a, a step is provided between the FET 5 and the chip capacitor 6 to prevent the solder 8b from spreading. At this time, the second gold conductor 4a is divided, but the underlying metal layer 12
Since it is connected by, there is almost no effect on the high frequency characteristics. This step portion can be formed at the same time when the pattern of the gold conductors 3 and 4 is formed.

According to the fourth embodiment of the present invention, a special step for providing the SiN layer 9 of the first embodiment, the gold ribbon 10 of the second embodiment, and the air bridge 11 of the third embodiment is required. Since it does not, it is advantageous in production.

Although the FET and the chip capacitor are used as the chip parts here, the same effect can be obtained even if other chip parts are used.

Embodiment 5 of the Invention 6 is a sectional view showing the structure of a high frequency integrated circuit according to a fifth embodiment of the invention.
In the figure, 13 is a resistance layer provided between the base metal layer 12 and the gold conductors 3 and 4.

Also in the fifth embodiment of the invention, the gold conductor 4 is used.
The second gold conductor 4a is divided by removing a part of it to form a concave portion and prevent the solder 8b from spreading. In this case as well, the second gold conductor 4a is divided, but since the base metal layer 12 and the resistance layer 13 are connected, there is almost no effect on the high frequency characteristics. Since the resistance layer 13 is provided, when it is desired to insert a resistor between the FET 5 and the chip capacitor 6, it is possible to simultaneously perform this by forming this concave portion.

Although the FET and the chip capacitor are used as the chip parts here, the same effect can be obtained even if other chip parts are used.

Sixth Embodiment of the Invention FIG. 7 is a perspective view showing the structure of a high frequency integrated circuit according to a sixth embodiment of the invention.
In this figure, a part of the second gold conductor 4a is narrower than other parts.

In the first embodiment of the invention, the passivation film is formed in a breakwater shape to prevent the solder 8b used for fixing the chip capacitor 6 from spreading to the FET 5 side. By narrowing the width of the portion of the conductor 4a between the chip capacitor 6 and the gold wire 7a compared to the other portions, the solder 8b is prevented from spreading. The width of the second gold conductor 4a is 100
It is about 600 μm, but the narrowed portion is about half of that.

By the way, the solders 8a, 8b, 8c are, for example, gold-tin (Au-Sn), indium-lead (In-P).
b), alloy solders such as indium-lead-silver (In-Pb-In). These solders have higher viscosity than general tin-lead alloy solders, and this kind of solder has a surface tension of Because of this, it is difficult to flow in a narrow area. Therefore, even if the solder 8b flows on the second gold conductor 4a toward the FET 5 side, it stops at a narrow portion in the middle thereof.

As can be seen from the above description, the solder 8b does not flow to the FET 5 side even in the sixth embodiment of the present invention.

Although the FET and the chip capacitor are used as the chip parts here, the same effect can be obtained even if other chip parts are used.

Seventh Embodiment of the Invention FIG. 8 is a perspective view showing the configuration of a high frequency integrated circuit according to a seventh embodiment of the invention.
In the sixth embodiment of the invention, the width of the portion of the second gold conductor 4a between the chip capacitor 6 and the gold wire 7a is made narrower than the other portions to prevent the solder 8b from spreading. However, here, the same effect can be obtained by arranging a plurality of lines having a sufficiently narrow width in parallel. Alternatively, the shape of FIG. 8 may be formed by removing a part of the second gold conductor 4a by etching.

Although the FET and the chip capacitor are used as the chip parts here, the same effect can be obtained even if other chip parts are used.

Eighth Embodiment of the Invention 9 is a sectional view showing a structure of a high frequency integrated circuit according to an eighth embodiment of the invention.
In the figure, 14 is a metal block fixed by solder 8b at a position facing the FET 5 on the second gold conductor 4a. The gold wire 7a is bonded onto the metal block 14.

Since the metal block 14 is fixed by the solder 8b, regardless of the spread of the solder 8b, the gold wire 7a.
Can be connected. Moreover, since the solder is used for fixing, the metal block 14 is stable, and the connection of the gold wire is also stable.

Although the FET and the chip capacitor are used as the chip parts here, the same effect can be obtained even if other chip parts are used.

Ninth Embodiment of the Invention 10 is a sectional view showing the structure of a high frequency integrated circuit according to a ninth embodiment of the invention.
You. In this figure, the gold ribbon 10 is the second gold conductor 4a.
It is thermocompression bonded on top.

In the eighth embodiment of the invention, the metal block 1 is provided on the second gold conductor 4a at a position facing the FET 5.
4 is soldered and the influence of the solder 8b is avoided by connecting the gold wire 7a on the metal block 14, but here, instead of the metal block 14, the gold ribbon 10 is thermocompression-bonded, and the gold ribbon 10 is similarly formed. The same effect is achieved by connecting the gold wire 7a to the upper part of the.

Although the FET and the chip capacitor are used as the chip parts here, the same effect can be obtained by using other chip parts.

[0057]

As described above, according to the present invention, the dielectric substrate, the first component and the second component provided on the dielectric substrate, and the dielectric substrate are formed on the dielectric substrate. In a high-frequency integrated circuit including a conductor and a metal wire that electrically connects the first component to the conductor, on the conductor,
Since the convex portion that shields the joining material for fixing the second component does not reach the connection point between the metal wire and the conductor, the second component and the connection point are provided. Even if the distance is not large, the joining material does not reach the connection point. Therefore, the connection can be surely made. That is, it is possible to provide a high-frequency integrated circuit which has a small size, can avoid the pressure bonding of the gold wire to the solder, and is highly reliable.

According to the present invention, on the conductor,
Since the recess for blocking the joining material is provided so that the joining material for fixing the second component does not reach the connection point between the metal wire and the conductor, the second component and the connection point are Even when the distance is not large, the joining material does not reach the connection point. Therefore, the connection can be surely made. That is, it is possible to provide a high-frequency integrated circuit which has a small size, can avoid the pressure bonding of the gold wire to the solder, and is highly reliable.

Further, according to the present invention, the base metal layer and the resistance layer are provided between the dielectric substrate and the conductor, and the recess is formed by removing a part of the conductor. That is, the resistance can be formed at the same time, which is advantageous in the manufacturing process.

Further, according to the present invention, since the joining material for fixing the second component is provided with the narrow portion for blocking the joining material so as not to reach the connection point between the metal wire and the conductor. The narrow portion can be formed simultaneously with the formation of the conductor pattern, which is advantageous in the manufacturing process.

Further, according to the present invention, the conductor for blocking the joining material for fixing the second component does not reach the connection point between the metal wire and the conductor. Since a metal block soldered or a gold ribbon thermocompression bonded is provided and the metal wire is connected to the metal block or the gold ribbon, the distance between the second component and the connection point is large. Even when not
The joining material does not reach the connection point. Therefore, the connection can be surely made. That is,
It is possible to provide a high-reliability high-frequency integrated circuit that can avoid crimping a gold wire to solder while reducing the shape. This invention has a narrow space between parts,
This is particularly advantageous when there is no room to provide a convex portion or the like.

[Brief description of drawings]

FIG. 1 is a perspective view showing a configuration of a high frequency integrated circuit according to a first embodiment of the invention.

FIG. 2 is a cross-sectional view showing the configuration of the high frequency integrated circuit according to the first embodiment of the present invention.

FIG. 3 is a sectional view showing a configuration of a high frequency integrated circuit according to a second embodiment of the invention.

FIG. 4 is a sectional view showing a configuration of a high frequency integrated circuit according to a third embodiment of the invention.

FIG. 5 is a sectional view showing a configuration of a high frequency integrated circuit according to a fourth embodiment of the invention.

FIG. 6 is a sectional view showing a configuration of a high frequency integrated circuit according to a fifth embodiment of the invention.

FIG. 7 is a perspective view showing a configuration of a high frequency integrated circuit according to a sixth embodiment of the invention.

FIG. 8 is a perspective view showing a configuration of a high frequency integrated circuit according to a seventh embodiment of the invention.

FIG. 9 is a sectional view showing a structure of a high frequency integrated circuit according to an eighth embodiment of the invention.

FIG. 10 is a sectional view showing a configuration of a high frequency integrated circuit according to a ninth embodiment of the invention.

FIG. 11 is a perspective view showing a configuration of a conventional high frequency integrated circuit.

FIG. 12 is a perspective view showing the configuration of another conventional high-frequency integrated circuit.

FIG. 13 is a perspective view for explaining a problem of a conventional high frequency integrated circuit.

[Explanation of symbols]

1 dielectric substrate, 2 ground conductor, 3 first gold conductor, 4
Second gold conductor, 5 FET, 6 chip capacitor, 7
Gold wire, 8 solder, 9 SiN layer, 10 gold ribbon,
11 air bridge, 12 base metal layer, 13 resistance layer, 14 metal block.

 ──────────────────────────────────────────────────続 き Continued from the front page (72) Inventor Yoshitada Iyama 2-3-2 Marunouchi, Chiyoda-ku, Tokyo Mitsubishi Electric Corporation

Claims (11)

[Claims] 1. A dielectric substrate, a first component and a second component provided on the dielectric substrate, a conductor formed on the dielectric substrate, and the first component as the conductor. In a high-frequency integrated circuit including a metal wire electrically connected to, the bonding material for fixing the second component on the conductor does not reach the connection point between the metal wire and the conductor. A high-frequency integrated circuit, characterized in that a convex portion that blocks the above-mentioned bonding material is provided. 2. The high frequency integrated circuit according to claim 1, wherein the convex portion is formed of a passivation film. 3. The high frequency integrated circuit according to claim 1, wherein the convex portion is formed by thermocompression bonding a gold ribbon to the conductor. 4. The high frequency integrated circuit according to claim 1, wherein the convex portion is an air bridge formed by separating a part of the conductor from the dielectric substrate. 5. A dielectric substrate, a first component and a second component provided on the dielectric substrate, a conductor formed on the dielectric substrate, and the first component as the conductor. In a high-frequency integrated circuit including a metal wire electrically connected to, the bonding material for fixing the second component on the conductor does not reach the connection point between the metal wire and the conductor. A high-frequency integrated circuit having a recess for blocking the bonding material. 6. The high frequency integrated circuit according to claim 5, further comprising a base metal layer between the dielectric substrate and the conductor, wherein the recess is formed by removing a part of the conductor. . 7. A base metal layer and a resistance layer are provided between the dielectric substrate and the conductor, and the recess is formed by removing a part of the conductor. High frequency integrated circuit. 8. A dielectric substrate, a first component and a second component provided on the dielectric substrate, a conductor formed on the dielectric substrate, and the first component as the conductor. In a high-frequency integrated circuit including a metal wire electrically connected to, the bonding material for fixing the second component on the conductor does not reach the connection point between the metal wire and the conductor. A high-frequency integrated circuit having a narrow portion for blocking the bonding material. 9. The high frequency integrated circuit according to claim 8, wherein the narrow portion is formed by removing a part of the conductor to reduce a width thereof. 10. A dielectric substrate, a first component and a second component provided on the dielectric substrate, a conductor formed on the dielectric substrate, and the first component as the conductor. In a high-frequency integrated circuit including a metal wire electrically connected to, the bonding material for fixing the second component is shielded so that the bonding material does not reach a connection point between the metal wire and the conductor. A high-frequency integrated circuit, comprising: a metal block soldered to the conductor for connecting the metal wire to the metal block. 11. A dielectric substrate, a first component and a second component provided on the dielectric substrate, a conductor formed on the dielectric substrate, and the first component as the conductor. In a high-frequency integrated circuit including a metal wire electrically connected to, the bonding material for fixing the second component is shielded so that the bonding material does not reach a connection point between the metal wire and the conductor. A gold ribbon thermocompression bonded to the conductor,
A high frequency integrated circuit in which the metal wire is connected to the gold ribbon.