JP2000049256A - Structure and manufacture of semiconductor device - Google Patents

Structure and manufacture of semiconductor device

Info

Publication number
JP2000049256A
JP2000049256A JP10214959A JP21495998A JP2000049256A JP 2000049256 A JP2000049256 A JP 2000049256A JP 10214959 A JP10214959 A JP 10214959A JP 21495998 A JP21495998 A JP 21495998A JP 2000049256 A JP2000049256 A JP 2000049256A
Authority
JP
Japan
Prior art keywords
circuit board
semiconductor
semiconductor circuit
semiconductor device
connection electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10214959A
Other languages
Japanese (ja)
Other versions
JP3441974B2 (en
Inventor
Masatomo Hasegawa
長谷川正智
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP21495998A priority Critical patent/JP3441974B2/en
Publication of JP2000049256A publication Critical patent/JP2000049256A/en
Application granted granted Critical
Publication of JP3441974B2 publication Critical patent/JP3441974B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241Disposition
    • H01L2224/24151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24226Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73267Layer and HDI connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • H01L2924/13063Metal-Semiconductor Field-Effect Transistor [MESFET]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Waveguides (AREA)

Abstract

PROBLEM TO BE SOLVED: To improve the yield and high-frequency characteristic of a semiconductor device by forming connection electrodes and transmission lines for high frequency on the side faces of a semiconductor circuit board. SOLUTION: A circuit 2 containing an active element 13 and shallow grooves are respectively formed on the top face and side faces of a semiconductor circuit board 1, and signal connection electrodes 3 and ground connection electrodes 4 are formed in the grooves. The electrodes 3 and 4 are formed in such a way that the electrodes 4 are arranged on both sides of the electrodes 3 in the same plane, so that a coplanar line suitable for high frequency may be constituted and electrically connected to the circuit 2. Therefore, the performance of a semiconductor device can be improved, because the circuit board 1 can be connected to a wiring board in a low-reflection low-loss state even under a high-frequency condition.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、半導体装置、特に
高周波用の半導体装置の接続電極構造とその製造方法に
関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a connection electrode structure of a semiconductor device, particularly a high frequency semiconductor device, and a method of manufacturing the same.

【0002】[0002]

【従来の技術】一般的に高周波部品では、半導体回路基
板と外部の高周波部品等を接続する伝送線路で特性イン
ピーダンスの不整合があった場合、信号の反射や損失に
よって本来の性能を発揮できなくなってしまう。特にパ
ワーアンプ等、能動素子が搭載された大電力用の高周波
部品では信号端子のインピーダンスが低く、伝送線路の
特性インピーダンスの不整合による信号の反射が非常に
大きな影響を与えるので、外部の実装基板へ接続する
際、整合回路を介して高いインピーダンスに変換するこ
とで極力信号の反射か少なくなるようにしている。しか
し、このときも整合回路などが形成された配線基板と半
導体回路基板の接続部分は低いインピーダンスのままな
ので信号の反射が起きやすく、高周波部品を構成する上
で最も重要な部分となっている。つまり、配線基板から
外部の実装基板までの伝送線路に工夫を凝らしても、半
導体回路基板から配線基板までの伝送線路による特性イ
ンピーダンスの不整合のため、高周波信号の反射や損失
が起き、半導体装置の性能を十分に発揮することができ
ないということである。
2. Description of the Related Art Generally, in a high-frequency component, if there is a mismatch in characteristic impedance in a transmission line connecting a semiconductor circuit board to an external high-frequency component or the like, the original performance cannot be exhibited due to signal reflection or loss. Would. In particular, high-frequency components for high power on which active elements are mounted, such as power amplifiers, have low signal terminal impedance and signal reflection due to mismatching of the characteristic impedance of the transmission line has a very large effect. At the time of connection, the signal is converted to a high impedance through a matching circuit so that the reflection of a signal is reduced as much as possible. However, also at this time, since the connection portion between the wiring board on which the matching circuit and the like are formed and the semiconductor circuit board has low impedance, signal reflection easily occurs, which is the most important part in configuring a high-frequency component. In other words, even if the transmission line from the wiring board to the external mounting board is devised, the characteristic impedance of the transmission line from the semiconductor circuit board to the wiring board is mismatched, so that reflection and loss of high-frequency signals occur and the semiconductor device Is not able to exhibit its performance sufficiently.

【0003】半導体回路基板と配線基板の接続は、従来
より金ワイヤー等の金属細線による接続が行われてい
る。しかし、金属細線はインダクタンスとして働いてし
まうので伝送線路としては不適切であり、また、インダ
クタンスの値も十分な再現性が得られない。
Conventionally, a connection between a semiconductor circuit board and a wiring board is made by a thin metal wire such as a gold wire. However, the thin metal wire acts as an inductance and is therefore unsuitable as a transmission line, and sufficient reproducibility of the inductance value cannot be obtained.

【0004】このような問題を解決する為、従来より様
々な工夫がなされている。特開平3−259542号公
報における半導体装置では、半導体基板裏面に形成した
接続用の接続電極をバイアホールによって半導体基板上
の素子領域と接続し、最短の経路で再現性のある接続を
可能にしている。
[0004] In order to solve such a problem, various devices have been conventionally devised. In the semiconductor device disclosed in Japanese Patent Application Laid-Open No. 3-259542, a connection electrode for connection formed on the back surface of a semiconductor substrate is connected to an element region on the semiconductor substrate by a via hole to enable reproducible connection with the shortest path. I have.

【0005】図7を用いて、本従来例を説明する。図7
(a)において1は半導体基板、2は素子領域、4はバ
イアホール、5は外部導出用リード、6はチップマウン
ト用基板、7はマウウント用材料、8はボンディングパ
ットである。半導体基板1は表面に素子領域2を有する
チップであり、ここには不純物の拡散や絶縁膜を堆積す
ることにより、トランジスタ、ダイオード、抵抗、コン
デンサ等のデバイスが集積されている。これらの配線は
バイアホール4を設け、この内側に金属(Al,Au
等)をメッキあるいはスパッタ法により付着させ裏面の
ボンディングパッド8へ導いている。
The conventional example will be described with reference to FIG. FIG.
In FIG. 1A, reference numeral 1 denotes a semiconductor substrate, 2 denotes an element region, 4 denotes a via hole, 5 denotes an external lead, 6 denotes a chip mounting substrate, 7 denotes a mounting material, and 8 denotes a bonding pad. The semiconductor substrate 1 is a chip having an element region 2 on the surface. Devices such as transistors, diodes, resistors, and capacitors are integrated here by diffusing impurities or depositing an insulating film. These wirings have via holes 4 in which metal (Al, Au) is provided.
, Etc.) by plating or sputtering and leading to the bonding pads 8 on the back surface.

【0006】また、特開平6−37202号に示された
マイクロ波IC用パッケージでは、マイクロ波IC用パ
ッケージとパッケージ外部の実装基板までの伝送線路で
も伝送モードの連続性を保持し、特性インピーダンスの
不整合による反射を最小限に抑えるよう工夫がなされて
いる。
In the microwave IC package disclosed in Japanese Patent Application Laid-Open No. 6-37202, continuity of the transmission mode is maintained even in the transmission line between the microwave IC package and the mounting substrate outside the package, and the characteristic impedance is reduced. A device has been devised to minimize reflection due to mismatch.

【0007】[0007]

【発明が解決しようとする課題】しかし、特開平3−2
59542号公報に示された半導体基板に形成されたバ
イアホールは、単に電気的に接続しているだけであり、
特性インピーダンスが整合された高周波用の伝送線路と
はなっていない。そのため半導体基板上の素子領域と外
部導出用リードの間でインピーダンスの不整合がおこ
り、高周波信号の反射や損失が生じ、素子領域に形成さ
れたデバイスの性能を十分に引き出すには至っていな
い。
However, Japanese Patent Laid-Open Publication No. Hei 3-2
The via hole formed in the semiconductor substrate disclosed in Japanese Patent No. 59542 is merely electrically connected,
It is not a transmission line for high frequency whose characteristic impedance is matched. As a result, impedance mismatch occurs between the element region on the semiconductor substrate and the external lead, causing reflection or loss of a high-frequency signal, and the performance of the device formed in the element region has not been sufficiently brought out.

【0008】また、上記半導体装置におけるバイアホー
ルは、半導体基板を切り離すダイシング工程やエッチン
グ工程に干渉しない程度に半導体基板端から内側に形成
してある。つまりは、素子や回路を形成できない領域が
素子領域周辺に必要ということで、半導体基板サイズの
増大によって半導体ウエハ内での半導体基板の取れ数の
低下を招いている。また、上記半導体装置では裏面にボ
ンディングパッドを形成するために裏面プロセスが必要
となっていて製造プロセスを複雑化している。さらに
は、はんだ付けの際にはんだの量が多すぎると、熔けた
はんだが半導体回路基板裏面に広がってショート不良を
招きやすい問題があり、ショートしていることを目視に
よって確認することもできないために歩留まりの低下を
招いており、これらの理由からコストの増大も招いてい
た。
The via hole in the semiconductor device is formed inward from the edge of the semiconductor substrate so as not to interfere with a dicing process or an etching process for separating the semiconductor substrate. In other words, a region where an element or a circuit cannot be formed is required around the element region, and an increase in the size of the semiconductor substrate causes a decrease in the number of semiconductor substrates to be removed in a semiconductor wafer. Further, in the above-mentioned semiconductor device, a back surface process is required to form a bonding pad on the back surface, which complicates the manufacturing process. Furthermore, if the amount of solder is too large at the time of soldering, there is a problem that the molten solder spreads on the back surface of the semiconductor circuit board and short-circuit defects are likely to occur, and it is not possible to visually confirm that the short-circuit has occurred. In this case, the yield is lowered, and for these reasons, the cost is also increased.

【0009】[0009]

【課題を解決するための手段】本発明の請求項1による
半導体回路基板上に形成された回路が少なくとも一つ以
上の接続電極を介して上記半導体基板の外部に接続され
てなる半導体装置において、上記接続電極が半導体回路
基板の側面に形成されていて、かつ、高周波用の伝送線
路を形成することにより半導体装置の高歩留まりと高周
波特性の改善ができる。
According to a first aspect of the present invention, there is provided a semiconductor device in which a circuit formed on a semiconductor circuit board is connected to the outside of the semiconductor substrate via at least one or more connection electrodes. By forming the connection electrode on the side surface of the semiconductor circuit board and forming a high-frequency transmission line, a high yield and improvement of high-frequency characteristics of the semiconductor device can be achieved.

【0010】本発明の請求項2による半導体回路基板の
接続電極がコプレーナ線路を形成することにより半導体
装置の高周波特性の改善ができる。
According to the second aspect of the present invention, the connection electrode of the semiconductor circuit board forms a coplanar line, whereby the high-frequency characteristics of the semiconductor device can be improved.

【0011】本発明の請求項3による半導体回路基板の
接続電極がスロット線路を形成することにより半導体装
置の高周波特性の改善ができる。
According to the third aspect of the present invention, since the connection electrodes of the semiconductor circuit board form a slot line, the high frequency characteristics of the semiconductor device can be improved.

【0012】本発明の請求項4による半導体回路基板上
に能動素子を含む回路が形成することにより半導体装置
の高周波特性の改善ができる。
A high frequency characteristic of a semiconductor device can be improved by forming a circuit including an active element on a semiconductor circuit board according to a fourth aspect of the present invention.

【0013】本発明の請求項5による半導体回路基板に
設けられた接続電極の少なくとも一部は、上記半導体回
路基板側面に設けられた溝の中に形成することにより半
導体装置の高歩留まりが達成できる。
A high yield of the semiconductor device can be achieved by forming at least a part of the connection electrode provided on the semiconductor circuit board according to the fifth aspect of the present invention in a groove provided on a side surface of the semiconductor circuit board. .

【0014】本発明の請求項6による半導体回路基板側
面の溝の深さが溝の幅より浅くすることにより半導体装
置の高歩留まりが達成できる。
According to the sixth aspect of the present invention, a high yield of the semiconductor device can be achieved by making the depth of the groove on the side surface of the semiconductor circuit substrate smaller than the width of the groove.

【0015】本発明の請求項7による半導体回路基板側
面の溝は、深さの深い所ほど幅が狭くすることにより半
導体装置の高歩留まりが達成できる。
According to the seventh aspect of the present invention, the groove on the side surface of the semiconductor circuit substrate is narrowed as the depth increases, so that a high yield of the semiconductor device can be achieved.

【0016】本発明の請求項8による半導体回路基板の
側面に形成された溝の、上記半導体回路基板の側面と接
する部分に金属層が無い、あるいは他の部分の金属層よ
り薄く形成することにより半導体装置の高歩留まりが達
成できる。
According to the eighth aspect of the present invention, the groove formed on the side surface of the semiconductor circuit substrate has no metal layer at a portion in contact with the side surface of the semiconductor circuit substrate, or is formed thinner than the metal layer of another portion. A high yield of semiconductor devices can be achieved.

【0017】本発明の請求項9による半導体回路基板の
接続電極は、上記半導体回路基板に形成された側壁に金
属層を有する貫通孔を分離することによって形成するこ
とにより半導体装置の高歩留まりと高周波特性の改善が
できる。
According to a ninth aspect of the present invention, a connection electrode of a semiconductor circuit board is formed by separating a through hole having a metal layer on a side wall formed on the semiconductor circuit board, so that a high yield and a high frequency of a semiconductor device are obtained. The characteristics can be improved.

【0018】[0018]

【発明の実施の形態】以下、本発明の実施の形態を図1
から図6を用いて説明する。図1は本発明による半導体
装置の概要を示す全体模式図である。図1において1は
半導体回路基板、2は回路、3は信号接続電極、4は接
地接続電極、5は誘電体基板、6は伝送線路、7は接地
金属、8は整合回路、9は外部接続電極および13は能
動素子である。図2は図1のA−A’での断面図であ
る。12ははんだおよび14はダイボンド材である。図
3は信号接続電極3および設置接続電極4部分の詳細拡
大図である。図3において10は溝である。
FIG. 1 is a block diagram showing an embodiment of the present invention.
This will be described with reference to FIG. FIG. 1 is an overall schematic diagram showing an outline of a semiconductor device according to the present invention. In FIG. 1, 1 is a semiconductor circuit board, 2 is a circuit, 3 is a signal connection electrode, 4 is a ground connection electrode, 5 is a dielectric substrate, 6 is a transmission line, 7 is a ground metal, 8 is a matching circuit, and 9 is an external connection. The electrodes and 13 are active elements. FIG. 2 is a sectional view taken along line AA ′ of FIG. 12 is a solder and 14 is a die bond material. FIG. 3 is a detailed enlarged view of the signal connection electrode 3 and the installation connection electrode 4. In FIG. 3, reference numeral 10 denotes a groove.

【0019】図1に示すように半導体回路基板1の上面
には能動素子13を含む回路2を、半導体回路基板1の
側面には図3に示す僅かに窪んだ溝10を形成し、溝1
0の中に信号接続電極3と接地接続電極4を形成してい
る。信号接続電極3と接地接続電極4は同一平面上に形
成してあり、信号接続電極3を両側で挟むように接地接
続電極4を形成することで高周波に適したコプレーナ線
路を形成し、回路2と電気的に接続している。
As shown in FIG. 1, a circuit 2 including an active element 13 is formed on the upper surface of the semiconductor circuit board 1, and a slightly recessed groove 10 shown in FIG.
0, the signal connection electrode 3 and the ground connection electrode 4 are formed. The signal connection electrode 3 and the ground connection electrode 4 are formed on the same plane. By forming the ground connection electrode 4 so as to sandwich the signal connection electrode 3 on both sides, a coplanar line suitable for high frequency is formed. Is electrically connected to

【0020】一方、誘電体基板5には伝送線路6と接地
金属7と整合回路8を形成している。伝送線路6は接地
金属7と共にコプレーナ線路を形成しており、整合回路
8に電気的に接続している。整合回路8は、回路2と外
部接続電極9の間のインピーダンス整合を行い、外部接
続電極9で50Ωとなるようにしている。また、回路2
に搭載しきれないバイアス回路等も誘電体基板5に形成
してもよい。
On the other hand, on the dielectric substrate 5, a transmission line 6, a ground metal 7, and a matching circuit 8 are formed. The transmission line 6 forms a coplanar line together with the ground metal 7, and is electrically connected to the matching circuit 8. The matching circuit 8 performs impedance matching between the circuit 2 and the external connection electrode 9 so that the external connection electrode 9 becomes 50Ω. Circuit 2
A bias circuit or the like that cannot be mounted on the substrate may be formed on the dielectric substrate 5.

【0021】そして、半導体回路基板1の信号接続電極
3と接地接続電極4を、誘電体基板5の上面の伝送線路
6に図2に示すようにはんだ12によって電気的及び機
械的に接続した。コプレーナ線路を形成した信号接続電
極3と接地接続電極4は伝送線路6と接地金属7を介し
て整合回路8に接続されることになり、これによって半
導体回路基板1上の回路2から整合回路8まで全てコプ
レーナ線路によって接続でき、反射や損失の無い接続が
可能となっている。接続の際、機械的強度を増すため
に、図2に示すようにダイボンド剤14を用いてもよ
い。本実施例ではダイボンド剤14に熱伝導の良い絶縁
樹脂を用い、半導体回路基板1で発生した熱を誘電体基
板5に放熱するようにした。
Then, the signal connection electrode 3 and the ground connection electrode 4 of the semiconductor circuit board 1 were electrically and mechanically connected to the transmission line 6 on the upper surface of the dielectric substrate 5 by solder 12 as shown in FIG. The signal connection electrode 3 and the ground connection electrode 4 forming the coplanar line are connected to the matching circuit 8 via the transmission line 6 and the ground metal 7, whereby the circuit 2 on the semiconductor circuit board 1 is connected to the matching circuit 8. All connections can be made by coplanar lines, and connection without reflection or loss is possible. At the time of connection, a die bonding agent 14 may be used as shown in FIG. 2 to increase the mechanical strength. In the present embodiment, an insulating resin having good heat conductivity is used for the die bonding agent 14, and the heat generated in the semiconductor circuit substrate 1 is radiated to the dielectric substrate 5.

【0022】本実施例で半導体回路基板1の材料として
高周波特性の良いGaAs(ガリウム砒素)を用い、能
動素子13にヘテロジャンクションバイポーラトランジ
スタ(HBT)を用い、抵抗、MIMキャパシタ、スパ
イラルインダクタおよびダイオードなどにより高出力ア
ンプ回路2を構成している。半導体回路基板1は、他の
材料(例えばAlGaAs,GaN,Si,SiC,I
nP,Geなど)でも良く、回路2の形成には上記以外
の能動素子(例えばBJT,MESFET,MISFE
T,ガンダイオード,IMPATT,アクティブリアク
タンスなど)を用いても良い。信号接続電極3と接地接
続電極4によって形成されたコプレーナ線路は、信号接
続電極3の幅と信号接続電極3と接地接続電極4の隙間
の幅によって回路2に接続する最適な特性インピーダン
スとなるように調整しているが、回路2の構成によって
は、信号接続電極3を平行に2つ配置し、スロット線路
を形成しても良い。その場合は2つの信号線路3の間隔
を調整することで特性インピーダンスを調整する。信号
接続電極3と接地接続電極4はめっきによって形成した
厚さ10μmの金を用い、高周波での損失を少なくする
と同時に、回路2からの放熱を良くしている。溝10
は、半導体回路基板1をピンセットなどで持った際に信
号接続電極3や接地接続電極4を傷つけないよう、めっ
き厚さ10μmより深く、また、深すぎて線路の特性に
影響が出ないよう、線路幅200μmより浅い最適な深
さである50μmとしている。
In this embodiment, GaAs (gallium arsenide) having good high-frequency characteristics is used as a material of the semiconductor circuit substrate 1, a heterojunction bipolar transistor (HBT) is used as the active element 13, and a resistor, a MIM capacitor, a spiral inductor, a diode, and the like are used. Constitute the high-output amplifier circuit 2. The semiconductor circuit substrate 1 is made of another material (for example, AlGaAs, GaN, Si, SiC, I
nP, Ge, etc., and other active elements (eg, BJT, MESFET, MISFE) for forming the circuit 2
T, Gunn diode, IMPATT, active reactance, etc.). The coplanar line formed by the signal connection electrode 3 and the ground connection electrode 4 has an optimum characteristic impedance to be connected to the circuit 2 depending on the width of the signal connection electrode 3 and the width of the gap between the signal connection electrode 3 and the ground connection electrode 4. However, depending on the configuration of the circuit 2, two signal connection electrodes 3 may be arranged in parallel to form a slot line. In that case, the characteristic impedance is adjusted by adjusting the interval between the two signal lines 3. The signal connection electrode 3 and the ground connection electrode 4 are made of gold having a thickness of 10 μm formed by plating, so that high-frequency loss is reduced and heat radiation from the circuit 2 is improved. Groove 10
In order to prevent the signal connection electrode 3 and the ground connection electrode 4 from being damaged when the semiconductor circuit board 1 is held with tweezers or the like, the plating thickness is deeper than 10 μm, and the plating is not so deep that the characteristics of the line are affected. The optimum depth is 50 μm, which is shallower than the line width of 200 μm.

【0023】以下に信号接続電極3と接地接続電極4の
形成方法について説明する。
Hereinafter, a method for forming the signal connection electrode 3 and the ground connection electrode 4 will be described.

【0024】図4は形成途中の電極部分の図である。1
1は半導体回路基板に形成した穴である。図5(a)、
図5(b)および図5(c)は電極部分の製造方法を示
す図4のB−B’での断面図および図6(a)、図6
(b)、図6(c)および図6(d)は半導体回路基板
に形成した穴の形状を示す図である。
FIG. 4 is a diagram of an electrode part in the process of being formed. 1
Reference numeral 1 denotes a hole formed in the semiconductor circuit board. FIG. 5 (a),
FIGS. 5B and 5C are cross-sectional views taken along the line BB ′ of FIG. 4 showing a method of manufacturing the electrode portion, and FIGS.
6 (b), 6 (c) and 6 (d) are views showing the shapes of holes formed in the semiconductor circuit board.

【0025】まず、図4に示すように、半導体回路基板
1上の回路2を通常の半導体プロセスによって複数個同
時に形成した後、隣接した半導体回路基板の境界部分
(B-B')に穴11をエッチングによって形成する。穴
11は少なくとも必要な接続電極の数だけ半導体回路基
板の境界部分に並んでいる。本実施の形態では穴11の
形成にドライエッチングを用い、最終的な基板厚さと同
じ100μmの深さとした。穴11の形成はウェットエ
ッチングプロセスを用いてもよい。穴11の大きさは境
界線と直行する方向には溝10の深さの2倍となる幅1
00μm、平行な方向に線路幅と同じ長さ200μmの
長方形としている。出来上がった穴11の断面形状は、
図5(a)に示すような順メサになるようにエッチング
ガスの材料や流量、エッチング電力などを調整してい
る。
First, as shown in FIG. 4, after a plurality of circuits 2 on the semiconductor circuit board 1 are simultaneously formed by a normal semiconductor process, holes 11 are formed at the boundary (BB ') between adjacent semiconductor circuit boards. Is formed by etching. The holes 11 are arranged on the boundary portion of the semiconductor circuit board by at least the number of necessary connection electrodes. In this embodiment, the hole 11 is formed by dry etching and has a depth of 100 μm, which is the same as the final substrate thickness. The formation of the hole 11 may use a wet etching process. The size of the hole 11 is twice as large as the depth of the groove 10 in the direction perpendicular to the boundary line.
It is a rectangle having a length of 200 μm, which is the same as the line width in a parallel direction. The sectional shape of the completed hole 11 is
The material and flow rate of the etching gas, the etching power, and the like are adjusted so as to form a forward mesa as shown in FIG.

【0026】次に、通常のフォトプロセスによってパタ
ーンを形成し、給電金属層(図示せず)を蒸着する。本
実施の形態ではフォトレジストを用いてパターンを形成
し、給電金属層にチタン(Ti)を用いた。穴11の断
面形状を順メサにしているので穴11の側面にも問題無
くフォトプロセスができ、蒸着も可能となっている。こ
のとき、穴11の半導体回路基板の境界線(B-B')と
直行する側面には、めっきされないようにレジストのパ
ターンを形成しておく。
Next, a pattern is formed by an ordinary photo process, and a power supply metal layer (not shown) is deposited. In this embodiment mode, a pattern is formed using a photoresist, and titanium (Ti) is used for a power supply metal layer. Since the cross-sectional shape of the hole 11 is a regular mesa, a photo process can be performed on the side surface of the hole 11 without any problem, and vapor deposition can be performed. At this time, a resist pattern is formed on the side surface of the hole 11 perpendicular to the boundary line (BB ′) of the semiconductor circuit board so as not to be plated.

【0027】そして、電解めっきによって10μmの厚
さに金をめっき15した後、レジストと給電金属層を除
去し図5(b)のような形状とし信号接続電極3と接地
接続電極4を形成した。その後、図5(c)に示すよう
に半導体回路基板の厚さが100μmになるまで裏面を
研磨する。最後に、半導体回路基板を境界線(B-B')
で分離すれば図3のような側面に接続電極が形成された
半導体回路基板が出来上がる。
Then, after gold was plated 15 to a thickness of 10 μm by electrolytic plating, the resist and the power supply metal layer were removed to form the shape shown in FIG. 5B, and the signal connection electrode 3 and the ground connection electrode 4 were formed. . Thereafter, as shown in FIG. 5C, the back surface is polished until the thickness of the semiconductor circuit substrate becomes 100 μm. Finally, the semiconductor circuit board is placed on the boundary line (BB ').
Then, a semiconductor circuit substrate having connection electrodes formed on side surfaces as shown in FIG. 3 is completed.

【0028】本実施の形態では半導体回路基板を100
μmまで研磨し半導体回路基板の境界線に穴11を複数
個並べているので、境界線の強度が非常に弱くなってお
り、容易に、かつ確実に半導体回路基板の境界線(B-
B')で劈開することができる。劈開によって穴11は
分離され、溝10となる。本実施の形態では穴11の半
導体回路基板の境界線(図4のB-B')と直行する側面
には、めっきされないようにし、劈開の際に溝10から
金属層がはがれるのを防いでいる。本実施の形態で半導
体回路基板の分離は劈開によって行ったがダイシングに
よって分離してもよい。また、本実施の形態では穴11
の形状を長方形としているが、図6(b)、(c)およ
び(d)に示すように六角形やひし形、楕円などにすれ
ば、劈開位置をより確実にする効果が得られる。
In this embodiment, the semiconductor circuit substrate is 100
Since a plurality of holes 11 are arranged at the boundary of the semiconductor circuit board after polishing to a thickness of μm, the strength of the boundary is very weak, and the boundary of the semiconductor circuit board (B-
B ′). The holes 11 are separated by the cleavage and become the grooves 10. In the present embodiment, the side surface of the hole 11 perpendicular to the boundary line (BB ′ in FIG. 4) of the semiconductor circuit board is not plated to prevent the metal layer from peeling from the groove 10 during cleavage. I have. In this embodiment mode, the semiconductor circuit substrate is separated by cleavage, but may be separated by dicing. In the present embodiment, the hole 11
Is rectangular, but if the shape is hexagonal, rhombic, elliptical, or the like as shown in FIGS. 6B, 6C, and 6D, the effect of further ensuring the cleavage position can be obtained.

【0029】また、本実施の形態で誘電体基板5には熱
伝導の良い窒化アルミ(AlN)を用いて半導体回路基
板1で生じた熱を効率よく放熱している。伝送線路6と
接地金属7は厚膜焼成プロセスによって形成した厚さ1
5μmのタングステン(W)であるが、高周波特性の向
上とはんだの濡れ性を確保する目的で、表面に厚さ1μ
mの金(Au)をめっきによって形成している。また、
金めっきの下地として厚さ1μmのニッケル(Ni)め
っきを用いた。整合回路8は、伝送線路6及び接地金属
7と同時に形成したスタブで形成し、外部接続電極9は
誘電体基板5の側面に形成している。整合回路8は、抵
抗、キャパシタ等のチップ部品で形成してもよい。外部
接続電極9は整合回路8によってインピーダンスが50
Ωになるように整合してあり、他の高周波部品への接続
を容易にしている。
Further, in this embodiment, the heat generated in the semiconductor circuit substrate 1 is efficiently radiated by using aluminum nitride (AlN) having good heat conductivity for the dielectric substrate 5. The transmission line 6 and the ground metal 7 have a thickness 1 formed by a thick film firing process.
5 μm tungsten (W), with a thickness of 1 μm on the surface for the purpose of improving high frequency characteristics and ensuring solder wettability.
m of gold (Au) is formed by plating. Also,
Nickel (Ni) plating having a thickness of 1 μm was used as a base for gold plating. The matching circuit 8 is formed of a stub formed simultaneously with the transmission line 6 and the ground metal 7, and the external connection electrode 9 is formed on a side surface of the dielectric substrate 5. The matching circuit 8 may be formed by chip components such as a resistor and a capacitor. The external connection electrode 9 has an impedance of 50 by the matching circuit 8.
Ω to facilitate connection to other high frequency components.

【0030】[0030]

【発明の効果】以上のように、本発明によれば、接続電
極が高周波に適したコプレーナ線路を形成している為、
半導体回路基板と配線基板を高周波でも低反射・低損失
に接続することが可能となり、性能を向上することが出
来る。
As described above, according to the present invention, since the connection electrode forms a coplanar line suitable for high frequency,
The semiconductor circuit board and the wiring board can be connected with low reflection and low loss even at a high frequency, and the performance can be improved.

【0031】また、表面からのフォトプロセスだけで製
造が可能となり、面倒な裏面プロセスを行う必要がな
く、半導体回路基板を分離する為のダイシング領域やエ
ッチング領域を必要とせず、かつ、接続電極形成の為に
必要な半導体回路基板面積も極めて小さくなるため、飛
躍的に半導体回路基板の小型化ができ、同一ウエハから
の半導体回路基板の取れ数が増加する。さらに、はんだ
付けは半導体回路基板側面の接続電極に行うので、はん
だの量が多すぎても隣の接続電極に広がってショート不
良を起こしにくく、たとえショート不良が起こっても目
視によって容易に発見することが出来、歩留まりの向上
が出来ることから、製造コストを大幅に低下することが
出来る。
Further, it is possible to manufacture the semiconductor device only by a photo process from the front surface, so that it is not necessary to perform a complicated back surface process, to eliminate the need for a dicing region or an etching region for separating the semiconductor circuit board, and to form a connection electrode. Therefore, the area of the semiconductor circuit board required for this purpose is also extremely small, so that the size of the semiconductor circuit board can be dramatically reduced, and the number of semiconductor circuit boards taken from the same wafer increases. Furthermore, since the soldering is performed on the connection electrodes on the side surfaces of the semiconductor circuit board, even if the amount of solder is too large, it spreads to the adjacent connection electrodes and short-circuit failure is unlikely to occur, and even if short-circuiting occurs, it can be easily found visually. Since the yield can be improved, the manufacturing cost can be significantly reduced.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明による半導体装置の概要を示す全体模式
図である。
FIG. 1 is an overall schematic diagram showing an outline of a semiconductor device according to the present invention.

【図2】本発明の図1のA−A’における断面図であ
る。
FIG. 2 is a cross-sectional view taken along line AA ′ of FIG. 1 of the present invention.

【図3】本発明の接続電極部分の拡大図である。FIG. 3 is an enlarged view of a connection electrode portion of the present invention.

【図4】本発明の形成途中の接続電極部分を示す図であ
る。
FIG. 4 is a view showing a connection electrode portion in the course of formation according to the present invention.

【図5】本発明の接続電極の製造方法を示す断面図であ
る。
FIG. 5 is a cross-sectional view illustrating a method for manufacturing a connection electrode according to the present invention.

【図6】本発明の接続電極部分の形状を示す図である。FIG. 6 is a view showing a shape of a connection electrode portion of the present invention.

【図7】従来の半導体装置の概要を示す図である。FIG. 7 is a diagram showing an outline of a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

1 半導体回路基板 2 回路 3 信号接続電極 4 接地接続電極 5 誘電体基板 6 伝送線路 7 接地金属 8 整合回路 9 外部接続電極 10 半導体回路基板の側面に形成された溝 11 半導体回路基板に開けられた穴 12 はんだ 13 能動素子 14 ダイボンド材 15 金メッキ DESCRIPTION OF SYMBOLS 1 Semiconductor circuit board 2 Circuit 3 Signal connection electrode 4 Ground connection electrode 5 Dielectric substrate 6 Transmission line 7 Ground metal 8 Matching circuit 9 External connection electrode 10 Groove formed on the side of semiconductor circuit board 11 Opened on semiconductor circuit board Hole 12 Solder 13 Active element 14 Die bond material 15 Gold plating

Claims (9)

【特許請求の範囲】[Claims] 【請求項1】 半導体回路基板上に形成された回路が少
なくとも一つ以上の接続電極を介して上記半導体基板の
外部に接続されてなる半導体装置において、上記接続電
極が半導体回路基板の側面に形成されていて、かつ、高
周波用の伝送線路を形成していることを特徴とする半導
体装置。
1. A semiconductor device in which a circuit formed on a semiconductor circuit board is connected to the outside of the semiconductor substrate through at least one connection electrode, wherein the connection electrode is formed on a side surface of the semiconductor circuit board. And a transmission line for high frequency is formed.
【請求項2】 上記半導体回路基板の接続電極がコプレ
ーナ線路を形成していることを特徴とする請求項1記載
の半導体装置。
2. The semiconductor device according to claim 1, wherein the connection electrodes of the semiconductor circuit board form a coplanar line.
【請求項3】 上記半導体回路基板の接続電極がスロッ
ト線路を形成していることを特徴とする請求項1記載の
半導体装置。
3. The semiconductor device according to claim 1, wherein said connection electrodes of said semiconductor circuit board form a slot line.
【請求項4】 上記半導体回路基板上に能動素子を含む
回路が形成されていることを特徴とする請求項1乃至3
のいずれかに記載の半導体装置。
4. A circuit including an active element is formed on the semiconductor circuit board.
The semiconductor device according to any one of the above.
【請求項5】 上記半導体回路基板に設けられた接続電
極の少なくとも一部は、上記半導体回路基板側面に設け
られた溝の中に形成されていることを特徴とする請求項
1乃至4のいずれかに記載の半導体装置。
5. The semiconductor device according to claim 1, wherein at least a part of the connection electrode provided on the semiconductor circuit board is formed in a groove provided on a side surface of the semiconductor circuit board. 13. A semiconductor device according to claim 1.
【請求項6】 半導体回路基板側面の溝の深さが溝の幅
より浅いことを特徴とする請求項5記載の半導体装置。
6. The semiconductor device according to claim 5, wherein the depth of the groove on the side surface of the semiconductor circuit board is smaller than the width of the groove.
【請求項7】 上記半導体回路基板側面の溝は、深さの
深い所ほど幅が狭くなっていることを特徴とする請求項
5乃至6のいずれかに記載の半導体装置。
7. The semiconductor device according to claim 5, wherein the width of the groove on the side surface of the semiconductor circuit board is reduced as the depth increases.
【請求項8】 上記半導体回路基板の側面に形成された
溝の、上記半導体回路基板の側面と接する部分に金属層
が無い、あるいは他の部分の金属層より薄く形成された
ことを特徴とする請求項5乃至7のいずれかに記載の半
導体装置。
8. A groove formed on a side surface of the semiconductor circuit board, wherein the metal layer is not formed in a portion in contact with the side surface of the semiconductor circuit board, or formed to be thinner than other metal layers. The semiconductor device according to claim 5.
【請求項9】 上記半導体回路基板の接続電極は、上記
半導体回路基板に形成された側壁に金属層を有する貫通
孔を分離することによって形成されたことを特徴とする
請求項5乃至8のいずれかに記載の半導体装置の製造方
法。
9. The semiconductor circuit substrate according to claim 5, wherein the connection electrode is formed by separating a through hole having a metal layer on a side wall formed on the semiconductor circuit substrate. 13. A method for manufacturing a semiconductor device according to
JP21495998A 1998-07-30 1998-07-30 Structure and manufacturing method of semiconductor device Expired - Fee Related JP3441974B2 (en)

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Application Number Priority Date Filing Date Title
JP21495998A JP3441974B2 (en) 1998-07-30 1998-07-30 Structure and manufacturing method of semiconductor device

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JP2000049256A true JP2000049256A (en) 2000-02-18
JP3441974B2 JP3441974B2 (en) 2003-09-02

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Country Link
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004289590A (en) * 2003-03-24 2004-10-14 Kyocera Corp High-frequency transmission line
JP2008098539A (en) * 2006-10-16 2008-04-24 New Japan Radio Co Ltd Planar circuit board and gunn diode oscillator using planar circuit board
JP2011171649A (en) * 2010-02-22 2011-09-01 Kyocera Corp Electronic component mounting package and electronic device employing the same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004289590A (en) * 2003-03-24 2004-10-14 Kyocera Corp High-frequency transmission line
JP2008098539A (en) * 2006-10-16 2008-04-24 New Japan Radio Co Ltd Planar circuit board and gunn diode oscillator using planar circuit board
JP2011171649A (en) * 2010-02-22 2011-09-01 Kyocera Corp Electronic component mounting package and electronic device employing the same

Also Published As

Publication number Publication date
JP3441974B2 (en) 2003-09-02

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