JPH09252026A - Superconductor device - Google Patents

Superconductor device

Info

Publication number
JPH09252026A
JPH09252026A JP4084228A JP8422892A JPH09252026A JP H09252026 A JPH09252026 A JP H09252026A JP 4084228 A JP4084228 A JP 4084228A JP 8422892 A JP8422892 A JP 8422892A JP H09252026 A JPH09252026 A JP H09252026A
Authority
JP
Japan
Prior art keywords
superconducting
bonding
chip
temp
superconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4084228A
Other languages
Japanese (ja)
Inventor
Tokuo Chiba
徳男 千葉
Nobuhiro Shimizu
信宏 清水
Kazuo Kayane
一夫 茅根
Toshinori Kogashiwa
俊典 小柏
Hideyuki Akimoto
英行 秋元
Hiroyuki Shigyo
裕之 執行
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tanaka Denshi Kogyo KK
Seiko Instruments Inc
Original Assignee
Tanaka Denshi Kogyo KK
Seiko Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tanaka Denshi Kogyo KK, Seiko Instruments Inc filed Critical Tanaka Denshi Kogyo KK
Priority to JP4084228A priority Critical patent/JPH09252026A/en
Publication of JPH09252026A publication Critical patent/JPH09252026A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/4847Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge

Abstract

PURPOSE: To provide a superconductor device using a low-durable temp. Josephson element by mounting its junction by hot compression bonding and reduce the man-hours and enhance the adhesion of the entire chip by a multi- contact connection at once. CONSTITUTION: A chip substrate 2 having bumps is hot compression bonded to a glass-epoxy mounting board 6 having a plated Sn superconductor film 8 on a Cu interconnection base pattern 7 at a bonding temp. of 100 deg. for a bonding time of 2 min, using a flip chip bonder. Though the bonding temp. is set to 100 deg., the durable temp. of an Nb-Al tunnel barrier type Josephson element is 150 deg. and bonding temp. is 150 deg. max. The critical contact of the bonded part is 15mA or more, showing a sufficient superconductor property. The bond strength is 0.2N per bond, and the entire board has a strength of 3.4N with 17 bonded units.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】この発明はジョセフソン素子を応
用した超伝導回路チップを実装した超伝導装置に関し、
特に耐熱温度の低いジョセフソン素子を用いた超伝導装
置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a superconducting device mounted with a superconducting circuit chip to which a Josephson element is applied,
Particularly, the present invention relates to a superconducting device using a Josephson element having a low heat resistance temperature.

【0002】[0002]

【従来の技術】従来、超伝導回路チップと実装基板との
超伝導接続は、例えば特開平3−12941号に示され
るように、超伝導ワイヤーを使用した超伝導ワイヤーボ
ンディングや溶融圧着によるフリップチップボンディン
グが用いられている。図3は従来例による超伝導装置を
表した図で、超伝導ワイヤーボンディングによる超伝導
接続を用いた超伝導装置を示している。12は超伝導回
路チップ、16は実装基板、13はパッド、15はバッ
ファー層、17は超伝導基板電極、11は超伝導ワイヤ
ーで、超伝導回路チップ12は実装基板16に超伝導回
路を形成した面を表にして接着され、パッド13上には
超伝導性を保持したまま接合強度を増加するためのバッ
ファー層15を形成し、超伝導基板電極17とパッド1
3を超伝導ワイヤー11のワイヤーボンディングにより
接続していた。
2. Description of the Related Art Conventionally, superconducting connection between a superconducting circuit chip and a mounting substrate is performed by superconducting wire bonding using a superconducting wire or flip chip by fusion bonding, as disclosed in, for example, JP-A-3-12941. Bonding is used. FIG. 3 is a diagram showing a superconducting device according to a conventional example, and shows a superconducting device using a superconducting connection by superconducting wire bonding. 12 is a superconducting circuit chip, 16 is a mounting substrate, 13 is a pad, 15 is a buffer layer, 17 is a superconducting substrate electrode, 11 is a superconducting wire, and the superconducting circuit chip 12 forms a superconducting circuit on the mounting substrate 16. A buffer layer 15 is formed on the pad 13 to increase the bonding strength while maintaining the superconductivity, and the superconducting substrate electrode 17 and the pad 1 are bonded to each other.
3 was connected by wire bonding of the superconducting wire 11.

【0003】また、超伝導フリップチップボンディング
では、ボールボンディング法により形成した超伝導材料
のバンプを用いて、接合部を温度200度に加熱し溶融
圧着によって超伝導接続していた。
In superconducting flip-chip bonding, bumps made of a superconducting material formed by a ball bonding method are used to heat the joint to a temperature of 200 ° C. and perform superconducting connection by melt-bonding.

【0004】[0004]

【発明が解決しようとする課題】上記従来の超伝導ワイ
ヤーボンディングを用いた超伝導装置では、接合端子数
のワイヤーをボンディングしなければならないため工数
が多く、ボンディングワイヤーがインダクタンスを形成
して回路の特性に影響を与え、ボンディングワイヤーや
チップ表面が露出しているために損傷を受けたり、電気
的に短絡する問題があった。また、上記従来のフリップ
チップボンディングを用いた超伝導装置では、接合部の
温度を約200度に加熱しなければならないため、耐熱
温度が約150度のニオブ(Nb)−アルミ(Al)系
のトンネル障壁型ジョセフソン素子を用いた超伝導装置
では、素子特性が劣化し、実際には実施不可能である問
題があった。
In the conventional superconducting device using the above-mentioned superconducting wire bonding, it is necessary to bond as many wires as the number of bonding terminals, so that the number of steps is large, and the bonding wire forms an inductance to form a circuit. There is a problem that the characteristics are affected and the bonding wire and the surface of the chip are exposed, resulting in damage or electrical short circuit. In the conventional superconducting device using flip chip bonding, the temperature of the joint must be heated to about 200 ° C., so that the heat resistance temperature of the niobium (Nb) -aluminum (Al) system is about 150 ° C. In the superconducting device using the tunnel barrier type Josephson element, there was a problem that the element characteristics were deteriorated and could not be actually implemented.

【0005】[0005]

【課題を解決するための手段】本発明は、上記の課題を
解決するため、ジョセフソン接合を有し、基板接続のた
めの接合部にバッファー層を有する超伝導回路を形成し
たチップを、接合部に配置された超伝導材料からなるバ
ンプを介して、超伝導材料からなる配線パターンを有す
る基板に、接合部を温度150度以下の熱圧着により実
装した。
SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention is to bond a chip having a Josephson junction and a superconducting circuit having a buffer layer at the junction for connecting substrates to each other. The bonding portion was mounted by thermocompression bonding at a temperature of 150 ° C. or less on a substrate having a wiring pattern made of a superconducting material, via a bump made of a superconducting material arranged in the portion.

【0006】[0006]

【作用】上記のような超伝導装置では、耐熱温度の低い
ジョセフソン素子を用いた超伝導装置を可能にし、一度
に多点接続するため、工数を少なくするとともにチップ
全体の接合強度を大きくすることができ、接合部のイン
ダクタンスを小さくし、チップを裏向きに実装するため
チップ表面を保護することができる。
With the superconducting device as described above, a superconducting device using a Josephson element having a low heat resistant temperature can be realized, and since multiple points are connected at one time, the number of steps is reduced and the bonding strength of the entire chip is increased. It is possible to reduce the inductance of the joint and protect the chip surface because the chip is mounted face down.

【0007】[0007]

【実施例】以下に本発明の実施例について図面を参照し
て説明する。図1および図2は本発明の実施例を示す超
伝導装置の部分断面図および平面図である。図1は、超
伝導接合部を表した図である。1は超伝導バンプであ
る。超伝導バンプ1の材料としては鉛錫(Pb−Sn)
合金、鉛インジウム金(Pb−In−Au)合金などの
超伝導材料が用いられ、同材料の線材にアーク放電によ
り形成したボールを用い、ボールボンディング法により
形成される。2はチップ基板、3は超伝導回路パター
ン、4は絶縁層、5はバッファー層で、図2に示す超伝
導回路9の配線を構成する超伝導回路パターン3の外部
回路との接続用パッド部10に、超伝導性を保持したま
ま接合強度を大きくするためのバッファー層5を形成し
たものである。
Embodiments of the present invention will be described below with reference to the drawings. 1 and 2 are a partial sectional view and a plan view of a superconducting device showing an embodiment of the present invention. FIG. 1 is a diagram showing a superconducting junction. 1 is a superconducting bump. The material of the superconducting bump 1 is lead tin (Pb-Sn)
A superconducting material such as an alloy or a lead-indium-gold (Pb-In-Au) alloy is used, and a ball formed by arc discharge is used as a wire rod of the same material, and is formed by a ball bonding method. Reference numeral 2 is a chip substrate, 3 is a superconducting circuit pattern, 4 is an insulating layer, and 5 is a buffer layer, and a pad portion for connecting to an external circuit of the superconducting circuit pattern 3 which constitutes the wiring of the superconducting circuit 9 shown in FIG. 10 is formed with a buffer layer 5 for increasing the bonding strength while maintaining superconductivity.

【0008】超伝導回路9は、例えば直流駆動型量子干
渉素子(DC SQUID)や交流駆動型量子干渉素子
(RF SQUID)、ジョセフソン論理回路素子、ジ
ョセフソンアレイで、シリコン(Si)などの極低温で
絶縁性を示す材料を用いたチップ基板2上に薄膜プロセ
スを用いて形成される。超伝導回路パターン3の材料と
しては、例えばニオブ(Nb)、鉛インジウム合金(P
b−In)、Pb−In−Auなどの超伝導材料の薄膜
が用いられ、絶縁層4の材料としては二酸化珪素(Si
O2)、酸化珪素(SiO)、Siなどの極低温で絶縁
性を示す材料が用いられ、バッファー層5の材料として
は金(Au)、白金(Pt)パラジウム(Pd)、銀
(Ag)、鉛(Pb)、Pbを主要元素とする他の合金
などが用いられる。
The superconducting circuit 9 is, for example, a DC drive type quantum interference device (DC SQUID), an AC drive type quantum interference device (RF SQUID), a Josephson logic circuit device, a Josephson array, and a pole such as silicon (Si). It is formed by a thin film process on the chip substrate 2 using a material exhibiting an insulating property at a low temperature. Examples of the material of the superconducting circuit pattern 3 include niobium (Nb) and lead-indium alloy (P
b-In), Pb-In-Au, or other thin film of a superconducting material is used, and the material of the insulating layer 4 is silicon dioxide (Si).
O2), silicon oxide (SiO), Si, or other material exhibiting an insulating property at an extremely low temperature is used, and the buffer layer 5 is made of gold (Au), platinum (Pt) palladium (Pd), silver (Ag), Lead (Pb), another alloy containing Pb as a main element, or the like is used.

【0009】バッファー層5の膜厚は、例えばAuを材
料として用いた場合5nmから200nmとすれば接合
の超伝導性を保持したまま接合強度を大きくすることが
できる。6は実装基板、7は配線ベースパターン、8は
超伝導膜で、実装基板6上に配線ベースパターン7を形
成し、さらに配線ベースパターン7上に超伝導膜8をメ
ッキで形成したもので、配線ベースパターン7と超伝導
膜8が同一パターンを形成して超伝導配線パターンとし
たものである。実装基板6の材料としては、プラスチッ
ク、FRP、セラミックなどの絶縁材料が用いられる。
配線ベースパターン7は超伝導膜8のメッキのためのバ
ッファー層として機能し、その材料としては、銅(C
u)、パラジウム(Pd)などの抵抗材料が用いられる
が、他の高抵抗材料を用いることもできる。超伝導膜8
の材料としては、例えばPb−Snメッキ膜が用いられ
るが、メッキ可能な他の超伝導材料を用いることもでき
る。
When the thickness of the buffer layer 5 is, for example, 5 nm to 200 nm when Au is used as the material, the bonding strength can be increased while maintaining the superconductivity of the bonding. 6 is a mounting substrate, 7 is a wiring base pattern, and 8 is a superconducting film. The wiring base pattern 7 is formed on the mounting substrate 6, and the superconducting film 8 is further formed on the wiring base pattern 7 by plating. The wiring base pattern 7 and the superconducting film 8 form the same pattern to form a superconducting wiring pattern. As the material of the mounting board 6, an insulating material such as plastic, FRP, or ceramic is used.
The wiring base pattern 7 functions as a buffer layer for plating the superconducting film 8, and its material is copper (C
A resistance material such as u) or palladium (Pd) is used, but another high resistance material can also be used. Superconducting film 8
For example, a Pb-Sn plated film is used as the material of, but another superconductive material that can be plated can also be used.

【0010】また、配線ベースパターン7を廃して、実
装基板6上に直接Nbスパッタ膜配線、Pb−In−A
u蒸着膜配線などの超伝導膜を形成して超伝導配線パタ
ーンとすることもできる。ただし、超伝導配線パターン
の材料としてNbを用いた場合には、接合部にバッファ
ー層5と同様の材料と機能を有する薄膜を配置する必要
がある。
Further, the wiring base pattern 7 is eliminated and the Nb sputtered film wiring, Pb-In-A, is directly formed on the mounting substrate 6.
It is also possible to form a superconducting film such as a u-deposited film wiring to form a superconducting wiring pattern. However, when Nb is used as the material of the superconducting wiring pattern, it is necessary to dispose a thin film having the same material and function as the buffer layer 5 at the junction.

【0011】図2に示した超伝導回路チップの平面図に
おいて、9は超伝導回路、10は接合用のパッドで、5
mm×5mmのチップ基板2上に400μm×400μ
mの接合用のパッド10を電気的接続には関与しない補
強用のパッドを含めて17個配置したものである。Nb
−Al系のトンネル障壁型ジョセフソン素子を有するD
C SQUIDのパッド10を、Nbスパッタ膜を材料
とした超伝導回路パターン3と、30nmの膜厚を有す
るAuスパッタ膜を材料としたバッファー層5により構
成し、直径30μmのPb−Sn合金ワイヤーからアー
ク放電で形成した直径90μmのボールを、ボールボン
ディング法により出力0.6W、発振時間20ms,加
重0.32Nの接合条件でそれぞれのパッドに1個ずつ
直径110μmの超伝導バンプ1として配置した。
In the plan view of the superconducting circuit chip shown in FIG. 2, 9 is a superconducting circuit and 10 is a bonding pad.
400μm × 400μ on the chip substrate 2 of mm × 5mm
Seventeen m bonding pads 10 are arranged, including reinforcing pads not involved in electrical connection. Nb
-Al-based tunnel barrier type Josephson device D
The C SQUID pad 10 is composed of a superconducting circuit pattern 3 made of a Nb sputtered film and a buffer layer 5 made of an Au sputtered film having a thickness of 30 nm. A ball having a diameter of 90 μm formed by arc discharge was placed as a superconducting bump 1 having a diameter of 110 μm on each pad under the bonding conditions of an output of 0.6 W, an oscillation time of 20 ms, and a weight of 0.32 N by a ball bonding method.

【0012】次に、バンプ付けされたチップ基板2をフ
リップチップボンダーを用いて、接合温度100度、接
合時間2min、バンプ1個当りの加重0.7Nの条件
で、Cu配線ベースパターン7上にメッキしたPb−S
n超伝導膜8を有するガラスエポキシ実装基板6に熱圧
着実装した。上記実施例では接合温度を100度とした
が、Nb−Al系のトンネル障壁型ジョセフソン素子の
耐熱温度は150度であり、接合温度は上限150度で
ある。
Next, the bumped chip substrate 2 is placed on the Cu wiring base pattern 7 using a flip chip bonder under the conditions of a bonding temperature of 100 ° C., a bonding time of 2 min, and a weight of 0.7 N per bump. Plated Pb-S
It was thermocompression bonded to the glass epoxy mounting substrate 6 having the n superconducting film 8. Although the junction temperature is set to 100 degrees in the above-mentioned embodiment, the heat resistance temperature of the Nb-Al-based tunnel barrier type Josephson element is 150 degrees, and the junction temperature is the upper limit of 150 degrees.

【0013】上記の超伝導装置を構成した場合、接合部
の臨界電流は15mA以上で、十分な超伝導性を示し、
接合強度は接合1個当り0.2Nで、基板全体では接合
17個分の3.4Nの強度が得られた。また、実装後の
DC SQIUDの特性に劣化は生じなかった。上記の
ような超伝導装置では、耐熱温度の低いジョセフソン素
子を用いた超伝導装置を可能にし、一度に多点接続する
ため、工数を少なくするとともにチップ全体の接合強度
を大きくすることができ、接合部のインダクタンスを小
さくし、チップを裏向きに実装するためチップ表面を保
護することができる。
When the above-mentioned superconducting device is constructed, the critical current of the junction is 15 mA or more, which shows sufficient superconductivity.
The bond strength was 0.2 N per bond, and the strength of 3.4 N for 17 bonds was obtained for the entire substrate. In addition, the characteristics of the DC SQIUD after mounting did not deteriorate. The superconducting device as described above enables a superconducting device using a Josephson element with a low heat resistance temperature, and since multiple points are connected at one time, it is possible to reduce the number of steps and increase the bonding strength of the entire chip. Since the inductance of the joint is reduced and the chip is mounted face down, the chip surface can be protected.

【0014】上記実施例ではパッド1個に超伝導バンプ
1を1個ずつ配置したが、パッド1個に複数個の超伝導
バンプ1を配置し、バンプ1個当りの接合加重を変更し
なければ、基板全体の接合強度を増加することができ
る。パッド1個に複数の超伝導バンプ1を配置しても、
その作用および効果は上記実施例と変わるところはな
い。
In the above embodiment, the superconducting bumps 1 are arranged one by one on each pad, but a plurality of superconducting bumps 1 are arranged on one pad and the bonding weight per bump must be changed. The bonding strength of the entire substrate can be increased. Even if multiple superconducting bumps 1 are placed on one pad,
The action and effect are the same as those in the above-mentioned embodiment.

【0015】[0015]

【発明の効果】以上説明したように本発明によれば、耐
熱温度の低いジョセフソン素子を用いた超伝導装置を可
能にし、一度に多点接続するため、工数を少なくすると
ともにチップ全体の接合強度を大きくすることができ、
接合部のインダクタンスを小さくし、チップを裏向きに
実装するためチップ表面を保護することができる。従っ
て、量産性に優れ、信頼性の高い超伝導装置を提供する
ことが可能である。
As described above, according to the present invention, it is possible to realize a superconducting device using a Josephson element having a low heat resistant temperature, and to connect multiple points at one time. Strength can be increased,
Since the inductance of the joint is reduced and the chip is mounted face down, the chip surface can be protected. Therefore, it is possible to provide a highly reliable superconducting device with excellent mass productivity.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の実施例を示す超伝導装置の部分断面図
である。
FIG. 1 is a partial cross-sectional view of a superconducting device showing an embodiment of the present invention.

【図2】本発明の実施例による超伝導装置を構成する超
伝導回路チップの平面図である。
FIG. 2 is a plan view of a superconducting circuit chip that constitutes a superconducting device according to an embodiment of the present invention.

【図3】従来例による超伝導装置を表した図である。FIG. 3 is a diagram showing a conventional superconducting device.

【符号の説明】[Explanation of symbols]

1 超伝導バンプ 2 チップ基板 3 超伝導回路パターン 4 絶縁層 5 バッファー層 6 実装基板 7 配線ベースパターン 8 超伝導膜 9 超伝導回路 10 パッド 11 超伝導ワイヤー 12 超伝導回路チップ 13 パッド 15 バッファー層 16 実装基板 17 超伝導基板電極 1 superconducting bump 2 chip substrate 3 superconducting circuit pattern 4 insulating layer 5 buffer layer 6 mounting substrate 7 wiring base pattern 8 superconducting film 9 superconducting circuit 10 pad 11 superconducting wire 12 superconducting circuit chip 13 pad 15 buffer layer 16 Mounting board 17 Superconducting board electrode

───────────────────────────────────────────────────── フロントページの続き (72)発明者 茅根 一夫 東京都江東区亀戸6丁目31番1号 セイコ ー電子工業株式会社内 (72)発明者 小柏 俊典 東京都三鷹市下連雀8丁目5番1号 田中 電子工業株式会社内 (72)発明者 秋元 英行 東京都三鷹市下連雀8丁目5番1号 田中 電子工業株式会社内 (72)発明者 執行 裕之 東京都三鷹市下連雀8丁目5番1号 田中 電子工業株式会社内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kazuo Kaya 6-31-1 Kameido, Koto-ku, Tokyo Seiko Denshi Kogyo Co., Ltd. (72) Toshinori Kogashi 8-5-1 Shimonrenjaku, Mitaka-shi, Tokyo Tanaka Denshi Kogyo Co., Ltd. (72) Inventor Hideyuki Akimoto 8-5-1, Shimorenjaku, Mitaka-shi, Tokyo Tanaka Electronics Industry Co., Ltd. (72) Inventor Hiroyuki 8-5-1, Shimorenjaku, Mitaka-shi, Tokyo Tanaka Electronic Industry Co., Ltd.

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 ジョセフソン接合を有し、基板接続のた
めの接合部にバッファー層を有する超伝導回路を形成し
たチップが、接合部に配置された超伝導材料からなるバ
ンプを介して、超伝導材料からなる配線パターンを有す
る基板に実装されている超伝導装置において、前記接合
部は熱圧着で実装されていることを特徴とする超伝導装
置。
1. A chip having a Josephson junction and having a superconducting circuit having a buffer layer at a joint for connecting to a substrate is formed by a superconductor via a bump made of a superconducting material arranged at the joint. A superconducting device mounted on a substrate having a wiring pattern made of a conductive material, wherein the joint is mounted by thermocompression bonding.
【請求項2】 前記接合部は、150℃以下の温度で熱
圧着される請求項1記載の超伝導装置。
2. The superconducting device according to claim 1, wherein the joint portion is thermocompression bonded at a temperature of 150 ° C. or lower.
JP4084228A 1992-04-06 1992-04-06 Superconductor device Pending JPH09252026A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4084228A JPH09252026A (en) 1992-04-06 1992-04-06 Superconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4084228A JPH09252026A (en) 1992-04-06 1992-04-06 Superconductor device

Publications (1)

Publication Number Publication Date
JPH09252026A true JPH09252026A (en) 1997-09-22

Family

ID=13824621

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4084228A Pending JPH09252026A (en) 1992-04-06 1992-04-06 Superconductor device

Country Status (1)

Country Link
JP (1) JPH09252026A (en)

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