JPH0114715B2 - - Google Patents
Info
- Publication number
- JPH0114715B2 JPH0114715B2 JP59013477A JP1347784A JPH0114715B2 JP H0114715 B2 JPH0114715 B2 JP H0114715B2 JP 59013477 A JP59013477 A JP 59013477A JP 1347784 A JP1347784 A JP 1347784A JP H0114715 B2 JPH0114715 B2 JP H0114715B2
- Authority
- JP
- Japan
- Prior art keywords
- superconducting
- film
- electrode
- layer
- lsi
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000010408 film Substances 0.000 claims description 56
- 239000002184 metal Substances 0.000 claims description 14
- 229910052751 metal Inorganic materials 0.000 claims description 14
- 229910052802 copper Inorganic materials 0.000 claims description 6
- 229910052737 gold Inorganic materials 0.000 claims description 6
- 230000004888 barrier function Effects 0.000 claims description 5
- 229910052709 silver Inorganic materials 0.000 claims description 5
- 239000010409 thin film Substances 0.000 claims description 4
- 239000010410 layer Substances 0.000 description 22
- 238000000034 method Methods 0.000 description 10
- 230000000694 effects Effects 0.000 description 8
- 229910000679 solder Inorganic materials 0.000 description 8
- 239000010953 base metal Substances 0.000 description 7
- 239000007772 electrode material Substances 0.000 description 5
- 239000000758 substrate Substances 0.000 description 5
- 239000000853 adhesive Substances 0.000 description 4
- 230000001070 adhesive effect Effects 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 4
- 230000001681 protective effect Effects 0.000 description 4
- 229910001020 Au alloy Inorganic materials 0.000 description 3
- 239000012528 membrane Substances 0.000 description 3
- 230000002265 prevention Effects 0.000 description 3
- 229910052718 tin Inorganic materials 0.000 description 3
- 229910000978 Pb alloy Inorganic materials 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 229910001128 Sn alloy Inorganic materials 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 238000001816 cooling Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- 229910052745 lead Inorganic materials 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- XWROUVVQGRRRMF-UHFFFAOYSA-N F.O[N+]([O-])=O Chemical compound F.O[N+]([O-])=O XWROUVVQGRRRMF-UHFFFAOYSA-N 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 229910000846 In alloy Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910020830 Sn-Bi Inorganic materials 0.000 description 1
- 229910018728 Sn—Bi Inorganic materials 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000007743 anodising Methods 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052797 bismuth Inorganic materials 0.000 description 1
- 239000002826 coolant Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 229910001873 dinitrogen Inorganic materials 0.000 description 1
- 239000006023 eutectic alloy Substances 0.000 description 1
- 230000001747 exhibiting effect Effects 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- 239000006260 foam Substances 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 125000004430 oxygen atom Chemical group O* 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000006104 solid solution Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N60/00—Superconducting devices
- H10N60/80—Constructional details
- H10N60/81—Containers; Mountings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は、超電導集積回路、とくにジヨセフソ
ン接合素子の外部接続に用いる超電導突起電極用
下地金属膜に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a base metal film for a superconducting bump electrode used for external connection of a superconducting integrated circuit, particularly a Josephson junction element.
トンネル型ジヨセフソン接合素子は、２つの超
電導薄膜の間に厚さ数nmの極めて薄い絶縁膜を
狭んだサンドイツチ構造で、極低温（〜4K）に
おける超電導トンネル現象を応用したスイツチン
グ素子である。この素子は、従来の半導体素子に
比べ、スイツチング速度は約１桁早く、消費電力
は約３桁小さいという特長があり、将来の超高速
計算機用の論理演算素子として期待されている。
これらの素子を構成するための超電導薄膜には、
おもにPb−In−Au合金、Pb−Au合金、又はNb
膜、NbN膜などが使用されている。また極薄の
トンネル障壁層にはPb及びInの酸化物あるいは
Nbの酸化物が用いられている。ところでこれら
のジヨセフソン接合素子を超高速計算機用の素子
として用いるためにはそれらをLSIレベルに集積
化したチツプを多数用いて実装し、モジユール化
した論理演算回路、記憶回路を開発する必要があ
る。それらLSIチツプをモジユール基板に実装す
る上で特に留意すべきことは、
(1) 超電導LSIチツプと他の超電導LSIチツプを
配線を介して接続する場合、それらの配線、接
続用電極（入・出力信号の取出し電極）は、全
て超電導金属で構成する必要のあること、
(2) LSIチツプの実装基板へのボンデイングは、
極薄のトンネル障壁層の劣化防止のため極力低
温で行う必要のあること、
などである。
A tunnel-type Josephson junction device has a sandwich structure in which an extremely thin insulating film several nanometers thick is sandwiched between two superconducting thin films, and is a switching device that applies the superconducting tunnel phenomenon at extremely low temperatures (~4K). This device has a switching speed that is about one order of magnitude faster and power consumption that is about three orders of magnitude lower than conventional semiconductor devices, and is expected to be used as a logic operation device for future ultra-high-speed computers.
The superconducting thin films used to construct these devices include
Mainly Pb-In-Au alloy, Pb-Au alloy, or Nb
membrane, NbN membrane, etc. are used. In addition, the ultra-thin tunnel barrier layer is made of Pb and In oxides or
Nb oxide is used. By the way, in order to use these Josephson junction devices as devices for ultra-high-speed computers, it is necessary to implement them using a large number of chips integrated at the LSI level and to develop modular logic operation circuits and memory circuits. The following points should be kept in mind when mounting these LSI chips on a module board: (1) When connecting a superconducting LSI chip and another superconducting LSI chip via wiring, the wiring and connection electrodes (input/output (2) The bonding of the LSI chip to the mounting board must be
The process must be carried out at the lowest temperature possible to prevent deterioration of the ultra-thin tunnel barrier layer.
上記２項目は、従来の半導体プロセスと大きく
異るところである。 The above two items are largely different from conventional semiconductor processes.
従来、LSIチツプと外部電極との接続はAl電極
−Al細線による超音波ワイヤボンデイング、Au
電極−Au細線、Al電極−Au細線による熱圧着ワ
イヤボンデイング、Au電極−Snメツキリードあ
るいは半田電極−半田電極によるリフローボンデ
イングなどが使用されている。これらの方法のう
ち、超電導LSIの組立に適用が可能な方法は半田
電極によるリフローボンデイングである。これは
半田電極自身が超電導特性を示すこと、またチツ
プ実装による配線長は他の方法に比べ短くするこ
とができ、高密度実装に適しているなどによる。
一般にリフローボンデイングに使用される半田の
成分は重量比でPb60％、Snが40％からなるPb−
Sn合金（共晶合金）で、その融点は183℃であ
る。通常半田電極を形成したLSI（Si−LSI）を実
装基板上にリフローボンデイングする場合、LSI
と基板をおよそ200〜300℃に加熱し、半田電極を
溶融させて目的を達成している。本方式を超電導
LSIチツプの実装基板への塔載法として採用した
場合、次のような問題が生ずる。すなわちジヨセ
フソン接合素子は、厚さ20〜40Åの極薄の酸化物
障壁層を使用しているが、リフローボンデイング
時の熱により、それら酸化物層中の酸素原子が上
部あるいは下部にある超電導電極内部に拡散し、
いわゆる超電導の特性が劣化する。Pbを超電導
電極として用いた超電導LSIの場合、前述の如き
劣化を防止するための許容温度限界はおよそ90℃
であり、Nbを用いた場合はおよそ200℃である。
したがつて従来の半田電極の場合は超電導LSIの
組立にそのまま適用することができない。このた
め、90℃以下の温度で溶融し、かつそれ自身超電
導特性を示すような突起電極材料の開発が必要で
ある。それらの代表的な材料はIn−Sn、In−Sn
−Biなどである。また他の一つの問題は、前述
の突起電極を超電導LSIの端子部に形成する場
合、機械的に十分な大きさの接着強度が得られ、
かつ電気的には超電導接続ないしはコンタクト抵
抗の低い接続が要求される。このため突起電極と
超電導LSIの端子部の間に接続用金属膜（突起電
極下地金属膜）を設けている。一般にそれらの金
属膜はAu／Pd膜（上層Au、下層Pd）が用いら
れている。Auは突起電極と下地のPd膜、Pd膜は
超電導LSIチツプに設けた端子電極、（一般にNb
膜を用いる）との接着性及び突起電極材がLSIチ
ツプ端子電極内部に拡散しないようにするための
拡散防止膜の役割を各々担つている。超電導LSI
に使用しているAu／Pd二層膜の厚さは、夫々
1000Åである。この二層膜は極低温（〜4K）で
は超電導特性を示さないため、わずかな抵抗（コ
ンタクト抵抗）を示し、ジユール熱による発熱が
生ずる。このため極低温冷媒の液体Heが気化し
て発泡し、超電導LSIの冷却効果が著しく低下す
る。冷却効果を改善するには、接続用金属膜に超
電導特性を示す金属膜乃至は、コンタクト抵抗の
小さな金属膜を使用する必要がある。 Conventionally, connections between LSI chips and external electrodes were made using ultrasonic wire bonding using Al electrodes and thin Al wires, or using Au.
Used are thermocompression wire bonding using an electrode-Au thin wire, Al electrode-Au thin wire, reflow bonding using an Au electrode-Sn plating lead, or a solder electrode-solder electrode. Among these methods, the method applicable to superconducting LSI assembly is reflow bonding using solder electrodes. This is because the solder electrode itself exhibits superconducting properties, and the length of wiring by chip mounting can be shorter than other methods, making it suitable for high-density mounting.
Generally, the components of solder used in reflow bonding are Pb-, which is composed of 60% Pb and 40% Sn by weight.
It is a Sn alloy (eutectic alloy) and its melting point is 183℃. Normally, when reflow bonding an LSI with solder electrodes (Si-LSI) on a mounting board, the LSI
The purpose is achieved by heating the board to approximately 200 to 300 degrees Celsius and melting the solder electrodes. This method is superconducting
If this method is used to mount an LSI chip on a mounting board, the following problems will occur. In other words, Josephson junction devices use an extremely thin oxide barrier layer with a thickness of 20 to 40 Å, but the heat during reflow bonding causes oxygen atoms in the oxide layer to leak inside the superconducting electrode at the top or bottom. spread to
The so-called superconducting properties deteriorate. In the case of superconducting LSIs that use Pb as superconducting electrodes, the allowable temperature limit to prevent the aforementioned deterioration is approximately 90°C.
When Nb is used, the temperature is approximately 200°C.
Therefore, conventional solder electrodes cannot be directly applied to the assembly of superconducting LSIs. Therefore, it is necessary to develop a protruding electrode material that melts at temperatures below 90°C and exhibits superconducting properties by itself. Their typical materials are In-Sn, In-Sn
−Bi, etc. Another problem is that when forming the aforementioned protruding electrodes on the terminals of superconducting LSIs, mechanically sufficient adhesive strength cannot be obtained.
Additionally, electrically, a superconducting connection or a connection with low contact resistance is required. For this reason, a metal film for connection (a metal film underlying the protruding electrode) is provided between the protruding electrode and the terminal portion of the superconducting LSI. Generally, the metal film used is an Au/Pd film (upper layer Au, lower layer Pd). Au is the protruding electrode and the underlying Pd film, the Pd film is the terminal electrode provided on the superconducting LSI chip (generally Nb
They each play the role of adhesion with the protruding electrode material (using a film) and a diffusion prevention film to prevent the protruding electrode material from diffusing into the inside of the LSI chip terminal electrode. Superconducting LSI
The thickness of the Au/Pd double layer film used for each
It is 1000Å. Since this two-layer film does not exhibit superconducting properties at extremely low temperatures (~4K), it exhibits a slight resistance (contact resistance) and generates heat due to Joule heat. As a result, the cryogenic coolant liquid He vaporizes and foams, significantly reducing the cooling effect of the superconducting LSI. In order to improve the cooling effect, it is necessary to use a metal film exhibiting superconducting properties or a metal film with low contact resistance as the connecting metal film.
本発明は、前述の問題点を解消するためになさ
れたもので、機械的に十分な大きさの接着強度が
得られ、コンタクト抵抗が低く、しかも拡散防止
効果の優れた、突起電極下地金属膜を提供するこ
とを目的としている。
The present invention has been made in order to solve the above-mentioned problems, and has a protruding electrode base metal film that can obtain mechanically sufficient adhesive strength, has low contact resistance, and has an excellent diffusion prevention effect. is intended to provide.
本発明は、最下層にTiを上層にAu、Ag、Cu
のいずれか一つの金属膜で構成された二層膜を、
超電導接続用突起電極の下地金属膜として、超電
導LSIチツプ内に設けた外部接続用端子電極上に
形成するものである。
The present invention uses Ti as the bottom layer and Au, Ag, and Cu as the upper layer.
A two-layer film composed of one of the metal films,
It is formed as a base metal film of the protruding electrode for superconducting connection on the terminal electrode for external connection provided in the superconducting LSI chip.
Ti膜は、超電導LSIチツプの外部接続用端子電
極のNbと低温成膜下でも十分な接着性が得られ
ること、また上層に形成するAu、Ag、Cuとの接
着性も優れている。さらにTi膜はAu、Ag、Cu
との金属的な拡散に対しても極めて安定である。
その反面Ti膜は従来のPd膜に比べ比抵抗が大き
いため、コンタクト抵抗が大きくなる。これらの
欠点に対しては、Tiの膜厚を300〜500Åとする
ことによりコンタクト抵抗の影響を軽減でき、か
つそのように薄くしても前述の接着性、拡散防止
効果が得られ、超電導LSIチツプ接続用突起電極
の下地金属膜に使用できることが判明した。 The Ti film has sufficient adhesion to the Nb of the external connection terminal electrodes of the superconducting LSI chip even under low-temperature film formation, and also has excellent adhesion to the Au, Ag, and Cu formed in the upper layer. Furthermore, the Ti film is Au, Ag, Cu
It is also extremely stable against metallic diffusion.
On the other hand, since the Ti film has a higher specific resistance than the conventional Pd film, the contact resistance increases. To address these drawbacks, the influence of contact resistance can be reduced by making the Ti film thickness 300 to 500 Å, and even with such a thin film, the aforementioned adhesion and diffusion prevention effects can be obtained, making superconducting LSI It has been found that it can be used as a base metal film for protruding electrodes for chip connections.
一方、Ti膜の上層に形成するAu、Ag、Cuの
いずれも膜の厚さは800〜1500Åである。それら
の膜はいずれも突起電極材であるIn−Sn合金、
In−Sn−Bi合金と溶融性（固溶）を有し、しか
も突起電極材自身の超電導遷移温度Tcに影響す
ることなく十分な接着性が得られ、前述のTi膜
と組合せて使用することにより安定な下地金属膜
として使用できることが判明した。 On the other hand, the thickness of the Au, Ag, and Cu films formed on the Ti film is 800 to 1500 Å. In-Sn alloy, which is the protruding electrode material,
It has meltability (solid solution) with the In-Sn-Bi alloy, and has sufficient adhesion without affecting the superconducting transition temperature Tc of the protruding electrode material itself, and can be used in combination with the Ti film mentioned above. It was found that it can be used as a stable base metal film.
以下、本発明の実施例につき図面を参照して詳
細に説明する。第１図に示すように、あらかじめ
清浄化処理したシリコン単結晶基板１上に熱酸化
により厚さ約6000ÅのSiO2層２を形成する。再
び基板を清浄化処理したのち、１×10-7Torr以
下の高真空中でNbを約3000Åの厚さに蒸着する。
なおNb膜の形成は前述の蒸着法のほかにスパツ
タ法によつても良い。つぎにフオトレジストと弗
酸−硝酸水溶液を用いてNbを所望のパターンに
エツチングし、グランドプレーン３を形成する。
このグランドプレーンは、超電導LSIの能動素子
部に形成したジヨセフソン接合のための外部磁気
遮へいの効果及び制御線から発生する磁束のミラ
ー効果のほか、LSI内のアース端子ならびに突起
電極用の端子電極４の役割を担う。つぎに前述の
アース端子及び突起電極用の端子電極に使用する
Nb膜部分を除いた他のNb膜部分表面を陽極酸化
し、グランドプレーン保護膜５を形成したのち
SiOからなる第１層間絶縁膜６を形成する。つぎ
にAuIn2からなる抵抗、さらにPb、In、Au合金
膜からなる配線接続層７及び下部電極膜を形成す
る。つぎにSiOからなる第２層間絶縁膜を形成し
たのち、プラズマ酸化法により所望の下部電極表
面にトンネル障壁層を、つづいて上部電極膜を形
成する。さらに第３層間絶縁膜を、ついで制御線
および配線層８を、さらに保護膜９を形成する。
つぎに突起電極用の端子電極４のNb表面をArガ
スの10-3Torrの減圧下でスパツタクリーニング
したのち、Ti膜１０を500Åの厚さに蒸着し、引
続きAu膜１１を1000Åの厚さに蒸着する。その
後リフトオフを行い、所望のパターン形状とし
た。なおTiおよびAuの蒸着中においては基板の
温度を50℃程度に維持した。また前記端子電極４
の寸法（開口部）は60μｍ□とした。つぎにあら
かじめ準備したメタルマスクを用い、前述の端子
電極４とメタルマスクの開口部とを位置したのち
In、Sn、Biを約40μｍの厚さに蒸着しメタルマス
クを取はずしたのち、基板１を５％の水素ガスを
含む窒素ガス雰気中で90℃に加熱し、In、Sn、
Biリフローレ半球状の突起電極１２を形成した。
以上述べた方法により作製した突起電極下地金属
膜のコンタクト抵抗は0.001〜0.005Ωであり、従
来の下地金属膜の1/2〜1/3程度に低減することが
できた。また突起電極の接着強度も45〜65ｇ（１
個当りの剪断強度）が得られ、機械的的に十分な
強度が得られていることを確認した。
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. As shown in FIG. 1, a SiO 2 layer 2 having a thickness of approximately 6000 Å is formed by thermal oxidation on a silicon single crystal substrate 1 that has been previously cleaned. After cleaning the substrate again, Nb is deposited to a thickness of about 3000 Å in a high vacuum of 1×10 -7 Torr or less.
Note that the Nb film may be formed by a sputtering method in addition to the above-mentioned vapor deposition method. Next, the Nb is etched into a desired pattern using a photoresist and a hydrofluoric acid-nitric acid aqueous solution to form a ground plane 3.
This ground plane serves as an external magnetic shielding effect for the Josephson junction formed in the active element part of the superconducting LSI and a mirror effect of the magnetic flux generated from the control line. take on the role of Next, use the above-mentioned earth terminal and terminal electrode for the protruding electrode.
After anodizing the surface of the other Nb film parts except for the Nb film part and forming the ground plane protective film 5,
A first interlayer insulating film 6 made of SiO is formed. Next, a resistor made of AuIn 2 , a wiring connection layer 7 made of a Pb, In, and Au alloy film, and a lower electrode film are formed. Next, after forming a second interlayer insulating film made of SiO, a tunnel barrier layer is formed on a desired lower electrode surface by a plasma oxidation method, and then an upper electrode film is formed. Furthermore, a third interlayer insulating film, a control line and wiring layer 8, and a protective film 9 are formed.
Next, after sputter cleaning the Nb surface of the terminal electrode 4 for the protruding electrode under a reduced pressure of 10 -3 Torr with Ar gas, a Ti film 10 was deposited to a thickness of 500 Å, and then an Au film 11 was deposited to a thickness of 1000 Å. Deposit on the surface. After that, lift-off was performed to obtain a desired pattern shape. Note that during the deposition of Ti and Au, the temperature of the substrate was maintained at approximately 50°C. Further, the terminal electrode 4
The dimension (opening) was 60 μm□. Next, using a metal mask prepared in advance, position the terminal electrode 4 and the opening of the metal mask.
After depositing In, Sn, and Bi to a thickness of about 40 μm and removing the metal mask, the substrate 1 was heated to 90°C in a nitrogen gas atmosphere containing 5% hydrogen gas, and
Bi reflow hemispherical protruding electrodes 12 were formed.
The contact resistance of the protrusion electrode base metal film produced by the method described above was 0.001 to 0.005Ω, which was able to be reduced to about 1/2 to 1/3 of that of the conventional base metal film. In addition, the adhesive strength of the protruding electrode is 45 to 65 g (1
It was confirmed that sufficient mechanical strength was obtained.
また本実施例ではAu／Tiの二層膜について述
べたが、Ag／TiおよびCu／Ti夫々の二層膜につ
いても前記実施例と同様の結果が得られた。さら
に本実施例ではPb合金を用いた超電導LSIの場合
について述べたが、Nb系材料を用いた超電導
LSIを用いた場合にも、同様な効果を有すること
を確認している。その場合、突起電極のリフロー
温度を200℃迄引き上げることができる。 Further, in this example, a two-layer film of Au/Ti was described, but results similar to those of the above-mentioned example were obtained with two-layer films of Ag/Ti and Cu/Ti. Furthermore, in this example, the case of superconducting LSI using Pb alloy was described, but superconducting LSI using Nb-based material
It has been confirmed that similar effects can be obtained when using LSI. In that case, the reflow temperature of the protruding electrode can be raised to 200°C.
以上説明したごとく本発明によれば、超電導
LSIの外部接続用突起電極の下地金属膜が安定に
形成できるようになり、接着強度が大きく、コン
タクト抵抗の低い電極構造が再現性よく作製でき
るようになつた。
As explained above, according to the present invention, superconducting
It has become possible to stably form the underlying metal film of the protruding electrodes for external connections in LSIs, and it has become possible to fabricate electrode structures with high adhesive strength and low contact resistance with good reproducibility.
第１図は、本発明の一実施例になる超電導LSI
の外部接続用突起電極部の断面構造を示す図であ
る。
図中、１……基板、２……絶縁層（SiO2層）、
３……グランドプレーン、４……超電導LSIの端
子電極、５……グランドプレーン保護膜、６……
第１層間絶縁膜、７……配線接続層、８……配線
層、９……保護膜、１０……Ti膜、１１……Au
膜、１２……超電導突起電極。
Figure 1 shows a superconducting LSI that is an embodiment of the present invention.
FIG. 3 is a diagram showing a cross-sectional structure of an external connection protrusion electrode portion of FIG. In the figure, 1... substrate, 2... insulating layer (SiO 2 layer),
3...Ground plane, 4...Terminal electrode of superconducting LSI, 5...Ground plane protective film, 6...
First interlayer insulating film, 7... Wiring connection layer, 8... Wiring layer, 9... Protective film, 10... Ti film, 11... Au
Membrane, 12... superconducting protruding electrode.
Claims (1)
層を狭んだサンドイツチ構造を主要素子とし、該
素子に超電導性の突起電極を接続してなる超電導
集積回路において、突起電極の下地金属膜として
最下層にTiを、上層にAu、Ag、Cuのいずれか
一つの金属膜で構成された二層膜を用いたことを
特徴とする超電導集積回路の端子電極。1. In a superconducting integrated circuit in which the main element is a Sanderch structure in which an ultra-thin tunnel barrier layer is sandwiched between two superconducting thin films, and a superconducting protruding electrode is connected to the element, the metal film as the underlying metal film of the protruding electrode is used. A terminal electrode for a superconducting integrated circuit characterized by using a two-layer film composed of Ti in the bottom layer and a metal film of one of Au, Ag, and Cu in the upper layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59013477A JPS60160186A (en) | 1984-01-30 | 1984-01-30 | Terminal electrode of superconductive integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59013477A JPS60160186A (en) | 1984-01-30 | 1984-01-30 | Terminal electrode of superconductive integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60160186A JPS60160186A (en) | 1985-08-21 |
| JPH0114715B2 true JPH0114715B2 (en) | 1989-03-14 |
Family
ID=11834201
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59013477A Granted JPS60160186A (en) | 1984-01-30 | 1984-01-30 | Terminal electrode of superconductive integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60160186A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5843520A (en) * | 1997-01-13 | 1998-12-01 | Vanguard International Semiconductor Corporation | Substrate clamp design for minimizing substrate to clamp sticking during thermal processing of thermally flowable layers |
| CN111969102B (en) * | 2020-09-11 | 2023-10-27 | 中国科学院紫金山天文台 | Preparation method for improving superconducting titanium-niobium film contact electrode |
-
1984
- 1984-01-30 JP JP59013477A patent/JPS60160186A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60160186A (en) | 1985-08-21 |
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