JPS60160186A - Terminal electrode of superconductive integrated circuit - Google Patents

Terminal electrode of superconductive integrated circuit

Info

Publication number
JPS60160186A
JPS60160186A JP59013477A JP1347784A JPS60160186A JP S60160186 A JPS60160186 A JP S60160186A JP 59013477 A JP59013477 A JP 59013477A JP 1347784 A JP1347784 A JP 1347784A JP S60160186 A JPS60160186 A JP S60160186A
Authority
JP
Japan
Prior art keywords
electrode
superconducting
film
layer
lsi
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59013477A
Other languages
Japanese (ja)
Other versions
JPH0114715B2 (en
Inventor
Mikio Hirano
幹夫 平野
Hideaki Nakane
中根 英章
Ushio Kawabe
川辺 潮
Shinichiro Yano
振一郎 矢野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Institute of Advanced Industrial Science and Technology AIST
Original Assignee
Agency of Industrial Science and Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agency of Industrial Science and Technology filed Critical Agency of Industrial Science and Technology
Priority to JP59013477A priority Critical patent/JPS60160186A/en
Publication of JPS60160186A publication Critical patent/JPS60160186A/en
Publication of JPH0114715B2 publication Critical patent/JPH0114715B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00Superconducting devices
    • H10N60/80Constructional details
    • H10N60/81Containers; Mountings
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods

Landscapes

  • Superconductor Devices And Manufacturing Methods Thereof (AREA)

Abstract

PURPOSE:To obtain the electrode structure of strong adhesive strength and low contact resistance by using two-layer film composed of Ti as the bottom layer and a metallic film of one of Au, Ag and Cu as the upper layer for a base metallic film of a projecting electrode. CONSTITUTION:A Ti film 10 is vapor-deposited on a surface of a terminal electrode 4 for a projecting electrode and subsequently an Au film 11 is vapor-deposited. After that, liftoff is performed to form the desired pattern shape. Next, by using a metal mask prepared previously, positions of the electrode 4 and an aperture part of the mask are adjusted and then In, Sn and Bi are vapor deposited. After removing the metallic mask, a substrate 1 is heated under the predetermined conditions and In, Sn and Bi are reflown to form a hemispherical projection electrode 12. The projecting electrode base metallic film thus fabricated has the low contact resistance and the adhesive property which is enough mechanically.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は、超電導集積回路、とくにジ蓼セフノン接合素
子の外S接続に用いる超電導突起電極用下地金属膜に関
するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a base metal film for a superconducting protrusion electrode used for an external S connection of a superconducting integrated circuit, particularly a di-Cefnon junction element.

〔発明の背景〕[Background of the invention]

トンネル臘ジ田セフノン接合素子は、2つの超電導w#
膜の間に厚さ数nmの極めて薄いII!3縁膜を狭んだ
サンドイッチ構造で、極低温(〜4K)における超電導
トンネル現象を応用したスイ、チ/グ素子である0との
素子は、従来の半導体系子に比べ、スイッチング速度は
約1桁早く、消費電、力は約3桁小さいという特長があ
如、将来の超高速計算機用の論理演算素子として期待さ
れている。
Tunnel Kajita Cefnon junction element has two superconductors w#
Extremely thin II with a thickness of several nm between the films! 0, which is a switch/ch/g device that uses superconducting tunneling at extremely low temperatures (~4K) and has a sandwich structure with three edge films, has a switching speed of approximately Because it is one order of magnitude faster and consumes about three orders of magnitude less power and power, it is expected to be used as a logic operation element for future ultra-high-speed computers.

これらの素子を構成するための超電導薄膜に社。The company develops superconducting thin films to construct these devices.

おもにPb−In−Au合金、Pb−Au合金、又はN
b膜、Nb膜瞑などが使用されている@また極薄のトン
ネル障壁層にはpb及びInの酸化物あるいはNbの酸
化瞼が用いられでいる。ところでこれらのジ1セフソン
接合素子を超高速計算機用の素子として用いるためには
七nらをL8ルベルに集積化したチップを多数用いて実
装し、七ジーール化した論理演算回路、記憶回路を開発
する必要がある0それらLSIチップをモジュール基板
に実装する上で特に留意すべきことは。
Mainly Pb-In-Au alloy, Pb-Au alloy, or N
In addition, oxides of PB and In or oxides of Nb are used for the ultra-thin tunnel barrier layer. By the way, in order to use these D1Sefson junction devices as elements for ultra-high-speed computers, we implemented a large number of chips that were integrated into the L8 level by Nana et al., and developed logic operation circuits and memory circuits that were integrated into the L8 Lebel. 0 Things to be especially careful about when mounting these LSI chips on a module board.

(1) 超電導LSIチップと他の超電導LSIチ。(1) Superconducting LSI chips and other superconducting LSI chips.

プを配線を介して接続する場合、それらの配線。If you connect the pools via wires, those wires.

接続用電極(入・出力信号の取出し#IL4Iii)は
The connection electrode (input/output signal extraction #IL4Iii) is.

全て超電導金属で構成する必要のあることV。V. Everything must be made of superconducting metal.

グ (2)]L8Iチップの実装基板へのボンデイン貴など
である。
(2)] bonding the L8I chip to the mounting board.

上記2項目は、従来の半導体プロセスと大龜〈異るとこ
ろである。
The above two items are major differences from conventional semiconductor processes.

Aui[極−Au細線、AI電極−Au細線による献圧
着ワイヤボンディング、人U電極−anメッキリードあ
るいは半田電極−半田電極によるり)四−ボンディング
などが使用さnて・いる。これらの方法のうち、超電導
LSIの組立に適用が可能な方法は半田電極によるリフ
ローボンディングである。
Aui (polar-Au wire bonding, AI electrode-an plated lead or solder electrode-solder electrode) four-bonding, etc. are used. Among these methods, the method applicable to superconducting LSI assembly is reflow bonding using solder electrodes.

これは半田電極自身が超電導特性を示すこと、またチッ
プ実装による配線長拡他の方法に比べ短くすることがで
き、高密度実装に適していゐなどによる。一般にリフロ
ーボンディングに使用される半田の成分紘亀量比でPb
が60係、8nが40憾からなるpb−8n合金 (共
晶合金)で、その融点は183℃である◎通常半田電唾
を形成したLSI(8i−LSI)を実装基板上にリフ
ローボンディングする場合、 LSIと基板をおよそ2
00〜300℃に加熱し、半田IE極を溶融させて目的
を達成している。本方式を超電導LSIチ、プの実装基
板への搭載法として採用した場合。
This is because the solder electrode itself exhibits superconducting properties, and it is suitable for high-density packaging because the wiring length can be shortened compared to other methods of expanding the wiring length by chip mounting. Pb is the component ratio of solder generally used for reflow bonding.
It is a pb-8n alloy (eutectic alloy) consisting of 60 parts of 8n and 40 parts of 8n, and its melting point is 183°C. ◎Usually, an LSI (8i-LSI) with solder deposits formed is reflow bonded onto a mounting board. In this case, the LSI and board are approximately 2
The purpose is achieved by heating to 00-300°C and melting the solder IE electrode. When this method is adopted as a mounting method for a superconducting LSI chip on a mounting board.

次のような問題が生ずる◎すなわちジョセフソン接合素
子は、厚さ20〜40λの極薄の酸化物障壁層を使用し
ているが、リフローボンディング時の熱に19、それら
酸化物l−中の酸素メ子が下部あるいは下部にある超電
導電極内部に拡散し、いわゆる超電導の特性が劣化する
OPbを超電導電極としで用いた超電導LSIの場合、
前述の如き劣化を防止するための許容温度限界はおよそ
90℃でtr)fi、Nbを用いた場合はおよそ200
℃である。したがって従来の半田電極の場合は超電導L
SIの組立にそのtま適用することができない。
The following problems arise: ◎In other words, Josephson junction elements use an extremely thin oxide barrier layer with a thickness of 20 to 40λ, but due to the heat during reflow bonding, the oxide l- In the case of a superconducting LSI using OPb as a superconducting electrode, oxygen molecules diffuse into the lower part or inside the superconducting electrode, deteriorating the so-called superconducting properties.
The permissible temperature limit for preventing the above-mentioned deterioration is approximately 90°C, and when Nb is used, the temperature limit is approximately 200°C.
It is ℃. Therefore, in the case of conventional solder electrodes, superconducting L
It cannot be applied to the assembly of SI.

このため、90℃以下の温度でS融し、かつ七n自身超
電導時性を示すような突起電極材料の開発が必要である
◎それらの代表的な材料はI n−8n #1m−8n
−Bi などである。ま九他の一つの問題は、前述の突
起電極を超電導LSIの端子部に形成する場合1機械的
に十分な大きさの接着強度が得られ、かつ電気的には超
電導接続ないしはコンタクト抵抗の低い接続が要求され
る口このため突起vt極と超電導LSIの端子部の間に
接続用金属膜(突起電極下地金属膜)を設けている。一
般にそれらの金属膜はAu / P d 814 (上
層Au、下層Pd )が用いられているoAuは突起電
極と下地のPd機、Pd機は超電導LSIチ、プに設け
た4 端子電極、(一般にNb膜を用いる)との接着性
及び突起IE電極材LSIチ、プ端子*極内部に拡散し
ないようにするための拡散防止膜の投射をf示さないた
め、わずかな抵抗(コンタクト抵抗)を示し、ジ鳳−ル
熱による発熱が生ずる。このため極低温冷媒の液体kL
eが気化して発泡し、超電導LI91の冷却効果が着し
く低下する。冷却効果を改番するには、接続用命l14
−に超電導特性を示す金Mll乃至は、コンタクト抵抗
の小さな金属膜を使用する必要がある。
For this reason, it is necessary to develop protruding electrode materials that melt S at temperatures below 90°C and exhibit superconducting properties themselves. Typical materials for these are I n-8n #1m-8n
-Bi etc. Another problem is that when forming the above-mentioned protruding electrodes on the terminals of superconducting LSIs, 1. mechanically sufficient adhesive strength is obtained, and electrically superconducting connection or contact resistance is low. Since connection is required, a metal film for connection (metal film underlying the protruding electrode) is provided between the protruding VT pole and the terminal portion of the superconducting LSI. Generally, these metal films are made of Au/Pd 814 (upper layer Au, lower layer Pd). oAu is a protruding electrode and an underlying Pd device, and a Pd device is a 4-terminal electrode provided on a superconducting LSI chip (generally (Nb film is used) and protruding IE electrode material LSI chip * Since there is no projection of a diffusion prevention film to prevent diffusion inside the electrode, a slight resistance (contact resistance) is exhibited. , a fever due to dill fever occurs. Therefore, liquid kL of cryogenic refrigerant
e vaporizes and foams, and the cooling effect of the superconducting LI 91 is severely reduced. To change the cooling effect, use the connection command l14.
It is necessary to use gold Mll, which exhibits superconducting properties, or a metal film with low contact resistance.

〔発明の目的〕[Purpose of the invention]

本発明は、前述の問題点を解消するためになされたもの
で1機械的に十分な大きさの接着強度が得られ、コンタ
クト抵抗が低く、シかも拡散防止効果の憂れた、突起電
極下地金j14−を提供することを目的としている。
The present invention has been made in order to solve the above-mentioned problems. 1) A protruding electrode base which has a mechanically sufficient adhesive strength, has low contact resistance, and has a poor diffusion prevention effect. The purpose is to provide gold j14-.

〔発明のg喪〕[Mourning of invention]

本発明は、最下層にTiを上層にAu、Ag。 In the present invention, the bottom layer is Ti and the upper layers are Au and Ag.

Cuのいずれか一つの金属膜で構成された二層膜を、超
電導I!続用突起電極の下咄金属暎として。
A two-layer film composed of one of the metal films of Cu is superconducting I! As a metal base for continuous protruding electrodes.

超電導LSIチップ内に設けた外部接続用端子電極上に
形成するものである。
It is formed on the external connection terminal electrode provided inside the superconducting LSI chip.

Ti膜は、超電導LSIチ、プの外部接続用端子電極の
Nbと低温成膜下でも十分な接着性が得られること、ま
た上層に形成するAu、ムg、Cuとの接着性も優nて
いる。さらICTImはAu。
The Ti film has sufficient adhesion to Nb, which is the external connection terminal electrode of the superconducting LSI chip, even under low-temperature film formation, and also has excellent adhesion to Au, Mug, and Cu formed in the upper layer. ing. Moreover, ICTIm is Au.

Ag、Cu との金属的な拡散に対しても極めて安定で
ある。その反面Ti機は従来のPd瞑に比べ比抵抗が大
きいため、コンタクト抵抗が大きくなる。これらの欠点
に対しては、Tiの膜厚を300〜500λとすること
によυコンタクト抵抗の影響を軽減でき、かつそのよう
に薄くしても前述の接着性、拡散防止効果が得られ、超
電導LSIチ、プ接続用突起電極の下地金属膜に使用で
きることが判明した。
It is also extremely stable against metallic diffusion with Ag and Cu. On the other hand, since the specific resistance of the Ti machine is higher than that of the conventional Pd machine, the contact resistance becomes large. To address these drawbacks, the influence of υ contact resistance can be reduced by setting the Ti film thickness to 300 to 500λ, and even with such a thin film, the aforementioned adhesion and diffusion prevention effects can be obtained. It has been found that it can be used as a base metal film for protruding electrodes for connecting superconducting LSI chips.

それらの膜はいずれも突起電極材であるi n −!1
t−=:’合金、In−8n−Bi金合金溶融性(同浴
)を有し、しかも突起電極材自身の超電導遷移温度Tc
に影響することなく十分な接着性が得られ、前述のTi
1l[と組合せて使用することによ多安定な下地金属膜
として使用できることが判明した。
All of those films are protruding electrode materials. 1
t-=:' alloy, In-8n-Bi gold alloy has meltability (same bath), and the superconducting transition temperature Tc of the protruding electrode material itself
Sufficient adhesion was obtained without affecting the Ti
It has been found that it can be used as a multistable base metal film by using it in combination with 1l [.

〔発明の実施例〕[Embodiments of the invention]

以下1本発明の実施例につき図面な参照して詳細に説明
する。第1図に示すように、あらかじめ清浄化処理した
シリコン単結晶基板1上に熱酸化によp嗅さ約6000
λの8i0. 層2を形成する。再び基板を清浄化処理
したのち、1×10Torr以下の高真空中でNbを約
3000λの5厚さに、@看する・なおNb膜の形成は
前述の蒸着法のほかにスパッタ法によっても艮い。つぎ
に7オトレジストと弗酸−硝酸水溶液を用いてNbを所
望のパターンに工、チングし、グランドプレーン3を形
成する。このグランドプレーンは、超電導LSIの能動
素子部に形成したジロセフソン接合のための外部磁気遮
へいの効果及び制aSから発生する磁束のミラー効果の
ほかに、LSI内のアース端子ならびに突起’IIC他
用の端子電極4の役割を担う。つぎに前述のアース端子
及び突起電極用の端子電極に使用するNb膜部分を除い
た他のNb換換部衣表面陽極酸化し、グランドプレーン
保護膜5を形成したのち840からなる第1層間絶縁f
ull!6を形成する。つぎIIc A u l n 
2からなる抵抗。
Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings. As shown in FIG. 1, approximately 6,000 p.p.
8i0 of λ. Form layer 2. After cleaning the substrate again, apply Nb to a thickness of about 3000λ in a high vacuum of 1 x 10 Torr or less.The Nb film can also be formed by sputtering in addition to the evaporation method described above. stomach. Next, a ground plane 3 is formed by etching and etching Nb into a desired pattern using a No. 7 photoresist and a hydrofluoric acid-nitric acid aqueous solution. In addition to the external magnetic shielding effect for the Girosefson junction formed in the active element part of the superconducting LSI and the mirroring effect of the magnetic flux generated from the control aS, this ground plane is used for the ground terminal and protrusion IIC inside the LSI. It plays the role of the terminal electrode 4. Next, the surface of the Nb exchange layer other than the Nb film used for the ground terminal and the terminal electrode for the protruding electrode is anodized to form the ground plane protective film 5, and then the first interlayer insulation made of 840 is formed. f
Ull! form 6. Next IIc A u l n
Resistance consisting of 2.

さらにPb−In−Au合金−からなる配線接続層7及
び下部1ilc極暎を形成する。つぎにSiOからなる
第3M間絶縁暎を形成したのち、プラズマ酸化法によ)
所望の下部電極表面にトンネル障壁層釦、つづいて上部
電極膜を形成する0さらに第3M間絶縁編を、ついで制
御?Isおよび配線層8を、さらに保護膜9を形成する
0つぎに突起電極用の痛子・電極40M表面をArガス
の10−” Tolrの減圧下でスパッタクリーニング
したのち、TIIrO2500λの厚さに蒸着し、引続
きAu膜11を1000λの厚さに蒸着する0その後リ
フトオフを行い、所望のパターン形状とした。なおTi
−F6よびAyuのM層中においては基板の温度を50
℃程度に維持した・また前記端子電極4の寸法(開口部
)は60μm とした。つぎにあらかじめ準備したメタ
ルマスクを用い、@述の端子電極4とメタルマスクの開
口部とを位置したのちIn、sn、Biを約40μmの
厚さに蒸着しメとルマスクを取はずしたのち、基板lを
5慢の水−を形成した。以上述べた方法により作製し九
央起電極下地・、−換のコンタクト抵抗は0.001〜
0.0050であシ、従来の下地金属膜の1/2〜1/
3橿kに低減することができた。また突起電極の接着強
就も45〜155 g (1個当シの剪断強度)が得ら
れ1機械的的に十分な強度が得られてしることを確認し
友。
Further, a wiring connection layer 7 made of a Pb-In-Au alloy and a lower layer 11c are formed. Next, after forming the third M insulating layer made of SiO, using the plasma oxidation method)
The tunnel barrier layer button is then formed on the desired lower electrode surface, and then the upper electrode film is formed. Furthermore, the third M insulation layer is then controlled? Is and wiring layer 8 are further formed to form a protective film 9.Next, the surface of the Itako electrode 40M for the protruding electrode is sputter-cleaned under a reduced pressure of 10" Tolr of Ar gas, and then evaporated to a thickness of TIIrO2500λ. Subsequently, an Au film 11 was deposited to a thickness of 1000λ, and then lift-off was performed to obtain the desired pattern shape.
- In the M layer of F6 and Ayu, the temperature of the substrate is 50°C.
The temperature was maintained at about 0.degree. C. and the dimension (opening) of the terminal electrode 4 was 60 .mu.m. Next, using a metal mask prepared in advance, the terminal electrode 4 described in @ and the opening of the metal mask were positioned, and then In, Sn, and Bi were evaporated to a thickness of about 40 μm, and the metal mask was removed. The substrate was coated with water for 5 hours. The contact resistance of the base electrode for the nine electrodes produced by the method described above is 0.001~
0.0050 mm, 1/2 to 1/2 that of conventional base metal film
We were able to reduce it to 3k. We also confirmed that the adhesion strength of the protruding electrodes was 45 to 155 g (shear strength per piece), and that sufficient mechanical strength was obtained.

1また本実施例では、Au/Ti の二層膜について鴎
べたが、Ag/TiおよびCu/Ti夫々の二層膜につ
いても前記実施例と同様の結果が得ら扛た。
1. In this example, the results were obtained using a two-layer film of Au/Ti, but the same results as in the previous example were also obtained for two-layer films of Ag/Ti and Cu/Ti.

さらに本実施例ではPb合金を用いた超−導LSIの場
合について述べたが、Nb系材料を用いた超電導LSI
を用いた場合にも、同様な効果を有することを確認して
いる。その場合、突起tiのり70一温度を200℃迄
引き上げることができる。
Furthermore, in this example, the case of a superconducting LSI using a Pb alloy was described, but a superconducting LSI using a Nb-based material
It has been confirmed that similar effects can be obtained when using In that case, the temperature of the protrusion ti glue 70 can be raised to 200°C.

〔発明の効果〕〔Effect of the invention〕

以上説明したごとく本発明によれば、超′遁導LSIの
外部接続用突起1に極の下地金禰換が安定に形成できる
ようになり、接着強度が大きく、コンタクト抵抗の低い
電極構造が再現性よく作製できるようになった。
As explained above, according to the present invention, it is possible to stably form the electrode base metal replacement on the external connection protrusion 1 of the super-conducting LSI, and an electrode structure with high adhesive strength and low contact resistance can be reproduced. Now it can be easily manufactured.

【図面の簡単な説明】[Brief explanation of drawings]

41図は1本発明の一実施例になる超電導LSIの外部
接続用突起電極部の断面構造を示す図である。 図中、l・・・基板、2・・・絶縁層(Siへ層)、3
・−・グランドプレーン、462.超電導L81の端子
、電極、5・・・グランドブレーン保護膜、6・・・w
41層間絶縁映、7・・・配線接続層、8・・・配線層
、9・・・保護膜。 10 ・Ti MIA、11 ・Au1ll!、12−
・・超電導突起−@1極。 特許出願人 工業技術院長用田裕部 第 1 図
FIG. 41 is a diagram showing a cross-sectional structure of a protruding electrode portion for external connection of a superconducting LSI according to an embodiment of the present invention. In the figure, l...substrate, 2... insulating layer (layer to Si), 3
--Ground plane, 462. Superconducting L81 terminal, electrode, 5...ground brain protective film, 6...w
41 Interlayer insulation film, 7... Wiring connection layer, 8... Wiring layer, 9... Protective film. 10 ・Ti MIA, 11 ・Au1ll! , 12-
...Superconducting protrusion - @1 pole. Patent applicant Hirobe Yoda, Director of the Agency of Industrial Science and Technology Figure 1

Claims (1)

【特許請求の範囲】 1、二つの超電導薄膜の間に極薄のトンネル障壁層を挾
んだサントイ、チ構造を主要素子とし。 該素子に超電導性の突起電極を接続してなる超電導果槓
11路において、突起電極の下地金属膜として最下層に
TIを、上層にAu、Ag、Cuのいずれか一つの金属
膜で構成された二層機を用いたことを特徴とする超電導
集積回路の端子電極。
[Claims] 1. The main element is a Santoichi structure in which an extremely thin tunnel barrier layer is sandwiched between two superconducting thin films. In the 11-way superconducting device in which superconducting protruding electrodes are connected to the element, the lowermost layer is made of TI and the upper layer is made of one of Au, Ag, and Cu metal films as the base metal film for the protruding electrodes. A terminal electrode for a superconducting integrated circuit characterized by using a two-layer device.
JP59013477A 1984-01-30 1984-01-30 Terminal electrode of superconductive integrated circuit Granted JPS60160186A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59013477A JPS60160186A (en) 1984-01-30 1984-01-30 Terminal electrode of superconductive integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59013477A JPS60160186A (en) 1984-01-30 1984-01-30 Terminal electrode of superconductive integrated circuit

Publications (2)

Publication Number Publication Date
JPS60160186A true JPS60160186A (en) 1985-08-21
JPH0114715B2 JPH0114715B2 (en) 1989-03-14

Family

ID=11834201

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59013477A Granted JPS60160186A (en) 1984-01-30 1984-01-30 Terminal electrode of superconductive integrated circuit

Country Status (1)

Country Link
JP (1) JPS60160186A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5843520A (en) * 1997-01-13 1998-12-01 Vanguard International Semiconductor Corporation Substrate clamp design for minimizing substrate to clamp sticking during thermal processing of thermally flowable layers
CN111969102A (en) * 2020-09-11 2020-11-20 中国科学院紫金山天文台 Preparation method for improving superconducting titanium-niobium film contact electrode

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5843520A (en) * 1997-01-13 1998-12-01 Vanguard International Semiconductor Corporation Substrate clamp design for minimizing substrate to clamp sticking during thermal processing of thermally flowable layers
CN111969102A (en) * 2020-09-11 2020-11-20 中国科学院紫金山天文台 Preparation method for improving superconducting titanium-niobium film contact electrode
CN111969102B (en) * 2020-09-11 2023-10-27 中国科学院紫金山天文台 Preparation method for improving superconducting titanium-niobium film contact electrode

Also Published As

Publication number Publication date
JPH0114715B2 (en) 1989-03-14

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