JPS5877266A - Bump electrode for connection terminal of superconductive thin film functional element and manufacture thereof - Google Patents
Bump electrode for connection terminal of superconductive thin film functional element and manufacture thereofInfo
- Publication number
- JPS5877266A JPS5877266A JP56175655A JP17565581A JPS5877266A JP S5877266 A JPS5877266 A JP S5877266A JP 56175655 A JP56175655 A JP 56175655A JP 17565581 A JP17565581 A JP 17565581A JP S5877266 A JPS5877266 A JP S5877266A
- Authority
- JP
- Japan
- Prior art keywords
- functional element
- thin film
- electrode
- superconducting thin
- film functional
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims description 10
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 238000000034 method Methods 0.000 claims abstract description 30
- 229910052738 indium Inorganic materials 0.000 claims abstract description 4
- 230000004888 barrier function Effects 0.000 claims description 8
- 239000010931 gold Substances 0.000 claims description 7
- 239000002184 metal Substances 0.000 claims description 7
- 229910052751 metal Inorganic materials 0.000 claims description 7
- 229910001020 Au alloy Inorganic materials 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 2
- 150000002739 metals Chemical class 0.000 claims description 2
- 241000208140 Acer Species 0.000 claims 1
- 206010011224 Cough Diseases 0.000 claims 1
- 239000002131 composite material Substances 0.000 claims 1
- 239000004020 conductor Substances 0.000 claims 1
- 239000003353 gold alloy Substances 0.000 claims 1
- 239000004576 sand Substances 0.000 claims 1
- 238000004904 shortening Methods 0.000 claims 1
- 238000007747 plating Methods 0.000 abstract description 15
- 229910045601 alloy Inorganic materials 0.000 abstract description 6
- 239000000956 alloy Substances 0.000 abstract description 6
- 230000008018 melting Effects 0.000 abstract description 5
- 238000002844 melting Methods 0.000 abstract description 5
- 239000000758 substrate Substances 0.000 abstract description 3
- JHXKRIRFYBPWGE-UHFFFAOYSA-K bismuth chloride Chemical compound Cl[Bi](Cl)Cl JHXKRIRFYBPWGE-UHFFFAOYSA-K 0.000 abstract description 2
- 229910052718 tin Inorganic materials 0.000 abstract description 2
- HPGGPRDJHPYFRM-UHFFFAOYSA-J tin(iv) chloride Chemical compound Cl[Sn](Cl)(Cl)Cl HPGGPRDJHPYFRM-UHFFFAOYSA-J 0.000 abstract description 2
- 229910052745 lead Inorganic materials 0.000 abstract 2
- 238000002791 soaking Methods 0.000 abstract 2
- 229910052797 bismuth Inorganic materials 0.000 abstract 1
- 229910052793 cadmium Inorganic materials 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 16
- 239000010955 niobium Substances 0.000 description 11
- 239000010408 film Substances 0.000 description 9
- 229910000679 solder Inorganic materials 0.000 description 8
- 229910052758 niobium Inorganic materials 0.000 description 5
- GUCVJGMIXFAOAE-UHFFFAOYSA-N niobium atom Chemical compound [Nb] GUCVJGMIXFAOAE-UHFFFAOYSA-N 0.000 description 5
- 239000006023 eutectic alloy Substances 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 4
- 239000010953 base metal Substances 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 238000009713 electroplating Methods 0.000 description 3
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 3
- 229910016338 Bi—Sn Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- YKYOUMDCQGMQQO-UHFFFAOYSA-L cadmium dichloride Chemical compound Cl[Cd]Cl YKYOUMDCQGMQQO-UHFFFAOYSA-L 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 229910015900 BF3 Inorganic materials 0.000 description 1
- 235000017166 Bambusa arundinacea Nutrition 0.000 description 1
- 235000017491 Bambusa tulda Nutrition 0.000 description 1
- 241001330002 Bambuseae Species 0.000 description 1
- 229910001152 Bi alloy Inorganic materials 0.000 description 1
- XWROUVVQGRRRMF-UHFFFAOYSA-N F.O[N+]([O-])=O Chemical compound F.O[N+]([O-])=O XWROUVVQGRRRMF-UHFFFAOYSA-N 0.000 description 1
- 206010028980 Neoplasm Diseases 0.000 description 1
- 235000015334 Phyllostachys viridis Nutrition 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910001128 Sn alloy Inorganic materials 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 239000011425 bamboo Substances 0.000 description 1
- WTEOIRVLGSZEPR-UHFFFAOYSA-N boron trifluoride Chemical compound FB(F)F WTEOIRVLGSZEPR-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- PSCMQHVBLHHWTO-UHFFFAOYSA-K indium(iii) chloride Chemical compound Cl[In](Cl)Cl PSCMQHVBLHHWTO-UHFFFAOYSA-K 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910000484 niobium oxide Inorganic materials 0.000 description 1
- URLJKFSTXLNXLG-UHFFFAOYSA-N niobium(5+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Nb+5].[Nb+5] URLJKFSTXLNXLG-UHFFFAOYSA-N 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000002887 superconductor Substances 0.000 description 1
- 229910002058 ternary alloy Inorganic materials 0.000 description 1
- 238000001771 vacuum deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N60/00—Superconducting devices
- H10N60/80—Constructional details
- H10N60/805—Constructional details for Josephson-effect devices
Landscapes
- Superconductor Devices And Manufacturing Methods Thereof (AREA)
- Containers, Films, And Cooling For Superconductive Devices (AREA)
Abstract
Description
【発明の詳細な説明】
(1) 発明の利用分野
本発明は、超電導薄膜機能素子、とくにジョセフンン接
合素子の外11[絖に用いる突起%憾とその製造方法に
関するものでるる。DETAILED DESCRIPTION OF THE INVENTION (1) Field of Application of the Invention The present invention relates to a superconducting thin film functional device, particularly a protrusion used in a wire of a Josephson junction device and a method for manufacturing the same.
(2) 従来技術
トンネル製ジョセフソン振付素子は、2つの超電導薄膜
の闇に厚さ数nmの惚めて博い絶猷膜を挾んにサンドイ
ンチ構造で、極低温(〜4K)における超電導トンネル
1m壁を応用したスイッチング素子でめる。この素子は
、従来の半導体索子に比べ、スイッチング速度はfJ1
桁、消費゛屯力は約3桁小さいという臀似がるり、将来
の超尚速耐鼻機用の論理演IJI索子、記憶素子として
期待されている。それらの素子を構成するための超亀導
博腺には、おもにpb−4n−Au合金、Pb−Au合
金、おるいはNbが使用されている。筐た惚博のトンネ
ル障壁層にはpbの酸化物あるいはNbの酸化物が用い
られている。ところでこれらのジョセフソン振付素子を
Miiii6速酊鼻慎用の素子として用いるためにはそ
れらをLSIレベルに集積化した論理is回路、記憶回
lNrを開発する必要がある。これらの回路を作製する
上で、臀に留意すべきことは
(11ジョセフソン素子と他のジョセフソン素子を配f
tMを介してftc絖する場合、七れらの配線、嵌絖用
電憔(入出力JrFi号の取出し゛亀億)は全て、超′
WIIL導金属で構成する必貴のろること。(2) Conventional technology The Josephson choreography element made by Tunnel has a sandwich structure with two superconducting thin films several nanometers thick sandwiched between them. A switching element using a 1m tunnel wall is used. This element has a switching speed of fJ1 compared to conventional semiconductor wires.
The power consumption is about 3 orders of magnitude lower, and it is expected to be used as a logical IJI cable and memory element for future ultra-fast nose-resistant aircraft. A pb-4n-Au alloy, a Pb-Au alloy, or Nb is mainly used in the superconductor for constructing these elements. Pb oxide or Nb oxide is used in the tunnel barrier layer of the Kakitabakuhiro. By the way, in order to use these Josephson choreography elements as elements for Miii 6-speed drunkenness control, it is necessary to develop a logic is circuit and a memory circuit lNr that integrate them at the LSI level. When creating these circuits, the following points should be kept in mind: (11) Josephson elements and other Josephson elements
When installing FTC via tM, all seven wirings and electric screws (input/output JrFi connection) are super
WIIL An essential curse made of conductive metal.
(2) 果槓回路チップの実装基板へのボンディング
は、極薄のトンネル障壁層の劣化防止のため極力低温(
100C以下)で行う必景があること。(2) The bonding of the circuit chip to the mounting board is carried out at the lowest possible temperature to prevent deterioration of the ultra-thin tunnel barrier layer.
(100C or less) must have a must-see view.
上記2項目は従来の牛導坏プロセスとは’t′)7′c
く異なるところの一つでるる。The above two items are different from the conventional gyudou process.'t')7'c
This is one of the things that is very different.
従来、L81チップと外部電極との接続はAt電m−h
tm庫による超音波ワイヤボンディング、Au1を極−
Au#1Ml!、AjKm−Aua線Kjる 、。Conventionally, the connection between the L81 chip and the external electrode was At electric m-h.
Ultrasonic wire bonding by tm warehouse, Au1 to pole-
Au#1Ml! , AjKm-Aua line Kjru ,.
熱圧層ワイヤボンディング%Au’[極−8nメツキリ
ード、あるいはハンダ11L他−ハンダ電極によるリフ
ローボンディングなどが使用されている。Thermopressure layer wire bonding %Au' [pole - 8n plated lead, or solder 11L etc. - reflow bonding with solder electrodes, etc. are used.
これらの方法のうちジョセフソンLSIの組立に適用が
可能な方法はハンダ電極によるす70−ボンディングで
める。これはハンダ電極自冴が超電導特性を示すことに
よる。一般にリフローボンディングに使用されるハンダ
の成分は夏賞比でpbが60%、Snが40%からなる
p b −Sn盆金(共晶合金)でその一点は183C
である。通常ハンダz億t−形成し*Lsr (st−
LSI)を夫ai板上K リフローボンディングする場
合、LSIと基板をおよそ200C〜230Cに加熱し
、ハンダ11IL極を浴融させて目的を達成している。Among these methods, the method applicable to the assembly of the Josephson LSI is 70-bonding using solder electrodes. This is because the solder electrode material exhibits superconducting properties. Generally, the components of the solder used for reflow bonding are PB-Sn alloy (eutectic alloy), which is composed of 60% PB and 40% Sn, and one of them is 183C.
It is. Normally solder is formed by z billion tons of *Lsr (st-
When reflow bonding an LSI (LSI) onto an AI board, the purpose is achieved by heating the LSI and the board to about 200C to 230C and melting the solder 11IL poles in a bath.
本方式をジョセフソンLSIチップの実装基板のマウン
ト法として採用した場会次のような問題が生ずる。すな
わちジョセフソン接合素子は、厚さ20〜30Aの惚博
の酸化物層障壁層上、使用しているが、リフローボンデ
ィング時の熱によりそれら酸化物層中の0原子が上部る
るいは下Sにめる超′wL尋電極に拡散し、いわゆる超
電導の特性が劣化する。Nbを超電導電極として用いた
ジョセフソンLSIの場合、前述の如き劣化を防止する
ための許容温度限界はおよそ120C以下である。When this method is adopted as a mounting method for a mounting board of a Josephson LSI chip, the following problem occurs. In other words, the Josephson junction element is used on a 20-30A thick oxide layer barrier layer, but the heat during reflow bonding causes zero atoms in the oxide layer to form on top or bottom S. It diffuses into the superconducting electrode, deteriorating its so-called superconducting properties. In the case of a Josephson LSI using Nb as a superconducting electrode, the allowable temperature limit for preventing the above-mentioned deterioration is about 120C or less.
したがって従来のノ1ンダ電他の場合、ジョセフソンL
SIの組立にそのまま適用することは不可能でめった。Therefore, in the case of the conventional No. 1
It is rarely possible to apply it directly to SI assembly.
(3)発明の目的
本発明は、前述の問題点を解消するために′4iI&さ
れたもので、超電導特性を示しかつ100C以下ノ温匿
でリフローボンディングが可能な突起電極を提供するた
めになされたものでめる。(3) Purpose of the Invention The present invention has been made in order to solve the above-mentioned problems, and has been made in order to provide a protruding electrode that exhibits superconducting properties and is capable of reflow bonding at temperatures below 100C. I can buy things.
(4)発明の詳細説明
金にs 8 ” * In t C dから選択した少
なくとも一つの金属を縫加して,超電導臨界温度6.5
に以上で且つ溶融温[100C以下の三元共晶合金を作
製し、これをジョセフソンLSIのりフローボンディン
グ用の突起電極として用いるものである。(4) Detailed description of the invention At least one metal selected from S8''*IntCd is sewn onto gold to achieve a superconducting critical temperature of 6.5.
A ternary eutectic alloy with a melting temperature of 100 C or higher and a melting temperature of 100 C or lower is prepared, and this is used as a bump electrode for Josephson LSI glue flow bonding.
上記の超tIIL尋臨界温旋と浴M温度を満足する三元
会合の組成は以下のとおシである。The composition of the ternary association that satisfies the above-mentioned ultra-tIIL supercritical temperature and bath M temperature is as follows.
すなわちpb−Bi−Sn系三元共晶合金の場合,Bi
12 〜25%、Sn20 〜25%(wt%)残シP
b%p b − f3 i − In系三元共晶合金の
場合、Bi12 〜25%* In20〜aO%(wt
%)残シpb,さらにpb−BiQd系三元合金の場合
、at1s〜25%.Cdl5〜25%(wt%)、残
1pbからなる合金群である。さらに上記各々の突起電
極の作製は,蒸着法、積層形メッキ法,合金メッキ法、
などが用いられている。いずれの方法によっても突起電
極の作製は容易である。In other words, in the case of pb-Bi-Sn ternary eutectic alloy, Bi
12 ~ 25%, Sn20 ~ 25% (wt%) remaining P
b% p b - f3 i - In the case of In-based ternary eutectic alloy, Bi12 ~ 25% * In20 ~ aO% (wt
%) residue pb, and in the case of pb-BiQd ternary alloy, at1s~25%. This is an alloy group consisting of 5 to 25% (wt%) Cdl and the balance 1 pb. Furthermore, each of the protruding electrodes mentioned above can be manufactured by vapor deposition method, laminated plating method, alloy plating method,
etc. are used. Protruding electrodes can be easily produced by either method.
一方、上記突起電極はLSIチップ内に形成されたNb
′IIt極只パット部に.Nblft他とハンダ電極と
の相互拡散が生じないよう拡散障at−を設けておる。On the other hand, the protruding electrodes are Nb formed inside the LSI chip.
'IIt to the extreme putting part. A diffusion barrier at- is provided to prevent mutual diffusion between Nblft and the solder electrode.
一般にはPb−Auが多く用いられている。Generally, Pb-Au is often used.
(5) 実施例
以下、本発明を実施例を参照して詳細に説明する。第1
図に示すように、あらかじめ清浄化処理したシリコン単
結晶基板上1に熱酸化法により厚さ約6000人の二酸
化シリコン層2を形成する。(5) Examples Hereinafter, the present invention will be explained in detail with reference to examples. 1st
As shown in the figure, a silicon dioxide layer 2 having a thickness of approximately 6,000 layers is formed on a silicon single crystal substrate 1 which has been previously cleaned by thermal oxidation.
再び基板を清浄化処理したのち16”’1 ’1’or
r以下の高真空中でニオブを約3000人の厚さに蒸着
する。つぎにフォトレジストと弗酸−硝酸水浴液を用い
て所望のパターンにエツチングし、下部電極(3,3’
)を形成する。つぎに前記ニオブ電極面上に層間絶縁
膜4として一酸化シリコンを形成する。その際リフトオ
フプロセスを用い−て前記ニオブ電極の一部が露出する
ように開口部を設ける。つぎに前記開口部に露出したニ
オブ電極表面を5×10″′5TOrrに減圧しfch
r雰囲気中でスパッタクリーニングしたのち、引続いて
5×10″Torrに減圧し、Arガスを放出したのち
0.ガスを導入してから10−” Torrに減圧し、
高周波出力20Wで発生した@素プラズマ中にNbを約
10分晒す。After cleaning the board again, 16”'1'1'or
Niobium is deposited to a thickness of approximately 3000 nm in a high vacuum below r. Next, a desired pattern is etched using a photoresist and a hydrofluoric acid-nitric acid bath solution, and the lower electrodes (3, 3'
) to form. Next, silicon monoxide is formed as an interlayer insulating film 4 on the surface of the niobium electrode. At that time, a lift-off process is used to provide an opening so that a portion of the niobium electrode is exposed. Next, the pressure on the niobium electrode surface exposed in the opening was reduced to 5×10'''5 TOrr, and fch
After sputter cleaning in an r atmosphere, the pressure was subsequently reduced to 5 x 10" Torr, Ar gas was released, 0.0" gas was introduced, and the pressure was reduced to 10" Torr.
Nb is exposed for about 10 minutes to @ elemental plasma generated with a high frequency output of 20W.
以上の方法によシ、前記露出したニオブ電極表面に厚さ
約40人の酸化ニオブ膜からなるトンネル障壁層5を生
成させる。ついでNbを約4000人の厚さに蒸着して
上部電極6を形成する。つぎに3t□を蒸着して前記1
億表面に層間絶縁層あるいは保腫膜7を形成する。なお
これら層間絶縁層はsio以外に810.あるいは8i
aN4、ポリイミド樹脂等を用いてもよい。ついでウェ
ハ全面に拡散防止用@壁金属と接着性向上のためのバン
プ下地金属9を蒸着する。このバンプ下地金属には一般
に厚さ約100OAのPd/Auの積層膜が用いられて
いる。このバンプ下地金属膜は、゛電気メッキ法によシ
バンプを形成する場合の電極として使用する。つぎにウ
ェハ全面にホトレジストを塗布したのち、バンプを形成
するため、所望の個所に開口部を設け、バンプ下地金属
を露出させたメッキ用レジストパターンを形成する。つ
ぎに該ウェハをホウ弗化を主成分としたpbメッキ液に
浸漬し、該電気メツキ法によりレジストの一口部上に厚
さ約40μmのpbを形成する。ついで塩化ビスマスを
主成分とするBiメッキ液に該ウェハを浸漬し、Pbと
同様′#!L気メッキ法によりpbの上部に厚さ約40
μmoB1を形成する。According to the above method, a tunnel barrier layer 5 made of a niobium oxide film having a thickness of about 40 nm is formed on the exposed surface of the niobium electrode. Next, Nb is deposited to a thickness of approximately 4000 nm to form the upper electrode 6. Next, 3t□ was vapor-deposited and
An interlayer insulating layer or a tumor film 7 is formed on the surface. In addition to sio, these interlayer insulating layers are 810. Or 8i
aN4, polyimide resin, etc. may also be used. Next, a wall metal for preventing diffusion and a bump base metal 9 for improving adhesion are deposited on the entire surface of the wafer. Generally, a Pd/Au laminated film with a thickness of about 100 OA is used as the bump base metal. This bump base metal film is used as an electrode when forming bumps by electroplating. Next, a photoresist is applied to the entire surface of the wafer, and in order to form bumps, openings are provided at desired locations to form a plating resist pattern that exposes the bump underlying metal. Next, the wafer is immersed in a PB plating solution containing boron fluoride as a main component, and a PB film with a thickness of about 40 μm is formed on the mouth of the resist by the electroplating method. Next, the wafer is immersed in a Bi plating solution containing bismuth chloride as the main component, and the same process as Pb is performed. Approximately 40mm thick is applied to the top of the PB using the L-air plating method.
Form μmoB1.
さいごに塩化錫を主成分とするBnメッキ液に該ウェハ
を浸漬し、厚さ約20μmのBnを形成する。その後該
ウェハをあらかじめ加熱しておる電気炉内に押入し、約
120Cで前記積層メッキ層を瞬時に溶融させ、半球状
のp b−Bi−Snの超電導突起電極(バンプ)10
を形成する。一般にメッキを行うためのバンプ下地層の
開口窓の寸法を60μm口とした場合、前述の方法によ
れば高さ約130μm径の半球状のt憶を作成すること
ができる。つぎにメツキレシストt−味去したのち、半
球状の突起電極をマスクにして不用な/<ンプ下地膜(
Au/Pd)を除去する。以上述べた方法によればpb
−ai−snからなる低一点の超電導突起電極を作成す
ることができる。Finally, the wafer is immersed in a Bn plating solution containing tin chloride as a main component to form a Bn layer with a thickness of approximately 20 μm. Thereafter, the wafer is pushed into a preheated electric furnace, and the laminated plating layer is instantly melted at about 120C, and a hemispherical pb-Bi-Sn superconducting bump electrode (bump) 10 is formed.
form. In general, if the size of the opening window in the bump underlayer for plating is 60 μm, the above-mentioned method can create a hemispherical memory with a height of about 130 μm in diameter. Next, after removing the Metsuki Resistant, use the hemispherical protruding electrode as a mask to remove unnecessary /
Au/Pd) is removed. According to the method described above, pb
A low single point superconducting protrusion electrode made of -ai-sn can be created.
なお実施例にはp b−Bi −f3 n合金からなる
接続端子用突起電極の作成法について述べたが、pb−
j3i−In、あるいはpb−Bi−cdについても同
様な方法によ多接続端子用突起電極の作成ができる。そ
の場合、Inまたはcdのメッキ液は、それぞれ塩化イ
ンジウムまたは塩化カドミウムを主成分とした酸性メッ
キ液を使用すれば良い。In addition, in the example, a method for making a protruding electrode for a connection terminal made of pb-Bi-f3n alloy was described, but pb-Bi-f3n alloy
For j3i-In or pb-Bi-cd, protruding electrodes for multi-connection terminals can be created in the same manner. In that case, an acid plating solution containing indium chloride or cadmium chloride as a main component may be used as the In or CD plating solution, respectively.
さらに本実施例ではp b−Bi−8n、p b −B
i−In、あるイFiP b−B 1−Cdty)積層
膜の形成法として電気メツキ法について詳述したが、前
記方法以外に真空蒸着法によってもまったく同様の結果
が得られ九。Furthermore, in this example, p b -Bi-8n, p b -B
Although the electroplating method has been described in detail as a method for forming the laminated film (i-In, FiP b-B 1-Cdty), exactly the same results can be obtained by using a vacuum evaporation method in addition to the above method.
また本発明の実施例においては、突起電極を構成する各
々の金属を積層したのち、瞬時に溶融させて半球状の電
極を得る方法について述べたが、本発明の主成分の金属
であるpb−i3i合金層を。Furthermore, in the embodiments of the present invention, a method was described in which a hemispherical electrode was obtained by laminating the respective metals constituting the protruding electrode and then instantaneously melting them. i3i alloy layer.
pb、 Biの合金メッキ法あるいは同時蒸着法によ)
作成しても前記実施例と同様の結果が得られた。PB, Bi alloy plating method or simultaneous vapor deposition method)
The same results as in the above example were obtained.
(6)まとめ
以上説明したごとく本発明によればトンネル接合形ジョ
セフソンLSIの外部接続用突起電極が再現よく作成で
きるようになシ、しかも100C以下の低い温度で前記
LSIを実装用基板にリフローボンディングが行えるよ
うになシ、ジョセフソンLSIの組立ての歩留り、信頼
性の向上が着しく向上した。(6) Summary As explained above, according to the present invention, protruding electrodes for external connection of a tunnel junction type Josephson LSI can be produced with good reproducibility, and the LSI can be reflowed onto a mounting board at a low temperature of 100C or less. Since bonding has become possible, the assembly yield and reliability of Josephson LSIs have improved significantly.
第1図は、トンネル接合型ジョセフソン接合素子の断面
図を示す。
1・・・基板、2・・・絶縁層、3および3′・・・下
部電極、4・・・層間絶縁膜、5・・・トン坏ル障壁層
、6・・・上部電極、7・・・保護層、8および9・・
・バンプ下地電極膜、10・・・接続端子用突起電極(
バンブ)。
代理人 弁理士 博田利幸FIG. 1 shows a cross-sectional view of a tunnel junction type Josephson junction device. DESCRIPTION OF SYMBOLS 1... Substrate, 2... Insulating layer, 3 and 3'... Lower electrode, 4... Interlayer insulating film, 5... Thon barrier layer, 6... Upper electrode, 7... ...Protective layer, 8 and 9...
・Bump base electrode film, 10...Protruding electrode for connection terminal (
Bamboo). Agent Patent Attorney Toshiyuki Hakata
Claims (1)
んだサンドインチ構造からなる超電導薄膜機能素子にお
いて、咳al!能素子の外部接続用端子電極がpb−B
i金合金gn、Jnおよびcdからなる群より選択され
た少なくとも1元素を姫加してなるM’tlL4合強で
構成されたことを特徴とする超電導薄膜機能素子の接続
端子用突起電極。 2、二つの超電導薄膜の間に極薄のトンネル1m壁層を
挾んだサンドインチ構造からなる超電導薄膜機能素子の
外S接続用端子%惚の製造方法において、所建の位置に
pbを、ついでBit−順次形成したのら、−′tの上
にBn、 Inおよびcdからなる群より選択した少な
くとも1金楓を順次積層してから、これらの積層金属を
#g融せしめて半球状としたことを特徴とする超電導薄
膜機能素子の接続端子用突起電極の製造方法。 3、二つの超’[4博膜の間に惚傳のトンネル障壁層を
洸んだサンドインチ構造からなる超篭導博Ill憬能累
子の外S撤絖用端子電惚の製造方法において、縮短の位
置にPb−B1貧釡膚を形成したのち、−tの上にsn
、(nおよび(’aからなる群より選択した少なくとも
l釡JrIを唄次槓ノーシてから、これらの積層金属を
浴融せしめて半31!状としたことを特徴とする超電導
薄膜機能素子の接続端子用突起電極の製造方法。[Claims] 1. In a superconducting thin film functional element having a sandwich structure in which an ultra-thin tunnel barrier layer is placed between two superconducting thin films, cough al! The terminal electrode for external connection of the functional element is pb-B.
1. A protruding electrode for a connection terminal of a superconducting thin film functional element, characterized in that it is composed of a M'tlL4 composite formed by adding at least one element selected from the group consisting of gold alloys gn, Jn and cd. 2. In the method for manufacturing a terminal for external S connection of a superconducting thin film functional element consisting of a sandwich structure in which an ultra-thin 1 m tunnel wall layer is sandwiched between two superconducting thin films, PB is placed at the specified position, Then, after sequentially forming Bit-'t, at least one gold maple selected from the group consisting of Bn, In, and CD is sequentially laminated on -'t, and these laminated metals are melted to form a hemispherical shape. A method for manufacturing a protruding electrode for a connecting terminal of a superconducting thin film functional element, characterized in that: 3. In a method for manufacturing a terminal electric wire for removing the outer S wire of a super wire conductor consisting of a sand inch structure with a tunnel barrier layer between the two wires. , after forming a Pb-B1 skin at the shortening position, sn
A superconducting thin film functional element characterized in that at least one metal selected from the group consisting of A method for manufacturing a protruding electrode for a connection terminal.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56175655A JPS5877266A (en) | 1981-11-04 | 1981-11-04 | Bump electrode for connection terminal of superconductive thin film functional element and manufacture thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56175655A JPS5877266A (en) | 1981-11-04 | 1981-11-04 | Bump electrode for connection terminal of superconductive thin film functional element and manufacture thereof |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5877266A true JPS5877266A (en) | 1983-05-10 |
Family
ID=15999891
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56175655A Pending JPS5877266A (en) | 1981-11-04 | 1981-11-04 | Bump electrode for connection terminal of superconductive thin film functional element and manufacture thereof |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5877266A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04236469A (en) * | 1991-01-21 | 1992-08-25 | Nec Corp | Method of forming solder bump for mounting superconducting integrated-circuit |
-
1981
- 1981-11-04 JP JP56175655A patent/JPS5877266A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04236469A (en) * | 1991-01-21 | 1992-08-25 | Nec Corp | Method of forming solder bump for mounting superconducting integrated-circuit |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5208186A (en) | Process for reflow bonding of bumps in IC devices | |
US3663184A (en) | Solder bump metallization system using a titanium-nickel barrier layer | |
EP0382080B1 (en) | Bump structure for reflow bonding of IC devices | |
JP3210547B2 (en) | Electroplating solder terminal and method of manufacturing the same | |
US5492235A (en) | Process for single mask C4 solder bump fabrication | |
US4840302A (en) | Chromium-titanium alloy | |
JPH11340265A (en) | Semiconductor device and its manufacture | |
CA1142264A (en) | Contact technique for electrical circuitry | |
JPH09129647A (en) | Semiconductor element | |
JPH04133330A (en) | Semiconductor device and its connecting method | |
US6742248B2 (en) | Method of forming a soldered electrical connection | |
JPS5877266A (en) | Bump electrode for connection terminal of superconductive thin film functional element and manufacture thereof | |
JP3297177B2 (en) | Method for manufacturing semiconductor device | |
WO2001056081A1 (en) | Flip-chip bonding arrangement | |
JPH09205096A (en) | Semiconductor element and fabrication method thereof, semiconductor device and fabrication method thereof | |
JPH0158875B2 (en) | ||
JPH0137876B2 (en) | ||
Salonen et al. | A flip chip process based on electroplated solder bumps | |
JPH08204244A (en) | Superconductive unit | |
JPS59107586A (en) | Superconductive flip chip bonding method | |
JPH04236469A (en) | Method of forming solder bump for mounting superconducting integrated-circuit | |
JPS6260836B2 (en) | ||
JPH0845938A (en) | Semiconductor device and its manufacture | |
JPS5897880A (en) | Projecting electrode for connecting terminal of superconducting thin-film function element | |
US5592732A (en) | Method of making super conducting bonds for thin film devices |