JPH09129681A - Electric connection structure between semiconductor chip and printed circuit substrate and its connection method - Google Patents
Electric connection structure between semiconductor chip and printed circuit substrate and its connection methodInfo
- Publication number
- JPH09129681A JPH09129681A JP8002100A JP210096A JPH09129681A JP H09129681 A JPH09129681 A JP H09129681A JP 8002100 A JP8002100 A JP 8002100A JP 210096 A JP210096 A JP 210096A JP H09129681 A JPH09129681 A JP H09129681A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- printed circuit
- circuit board
- conductive
- epoxy
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体チップを印
刷回路基板上に実装する場合、電気的に連結される構造
物とその連結方法に係るもので、詳しくは、半導体パッ
ケージの構造をコンパクト化し、実装の工程を簡便に行
い得る半導体チップと印刷回路基板間の電気的連結構造
物及びその連結方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure which is electrically connected when a semiconductor chip is mounted on a printed circuit board and a method of connecting the same. More specifically, the structure of a semiconductor package is made compact. The present invention relates to an electrical connection structure between a semiconductor chip and a printed circuit board, which can easily perform a mounting process, and a connection method thereof.
【０００２】[0002]
【従来の技術】従来、半導体チップと印刷回路基板間の
電気的連結構造及びその連結方法においては、図３
（Ａ）い示したように、先ず、半導体チップ１０上に形
成されたパッド１２を開放し、該パッド１２に所定高さ
のマスク１４を密接させる。次いで、図３（Ｂ）に示し
たように、該パッド１２上に導電性バンプ１６を蒸着
し、図３（Ｃ）に示したように、前記マスク１４を食刻
して電導性バンプ１６のみを半導体チップ上に付着形成
する。次いで、図３（Ｄ）に示したように、該半導体チ
ップ１０を覆えて印刷回路基板２０上の付け段１８に合
致させた後、図３（Ｅ）に示したように、リフロー（re
flow）のような接合工程を施し、それら半導体チップ１
０と印刷回路基板２０とを導電性バンプ１８により電気
的連結させていた。2. Description of the Related Art Conventionally, an electrical connection structure between a semiconductor chip and a printed circuit board and a connection method therefor have been described in FIG.
As shown in (A), first, the pad 12 formed on the semiconductor chip 10 is opened, and the mask 14 having a predetermined height is brought into close contact with the pad 12. Next, as shown in FIG. 3B, a conductive bump 16 is deposited on the pad 12, and the mask 14 is etched to form only the conductive bump 16 as shown in FIG. 3C. Are deposited on the semiconductor chip. Next, as shown in FIG. 3D, after covering the semiconductor chip 10 and matching it with the mounting step 18 on the printed circuit board 20, as shown in FIG.
flow) and a semiconductor chip 1
0 and the printed circuit board 20 were electrically connected by the conductive bumps 18.
【０００３】[0003]
【発明が解決しようとする課題】然るに、このような従
来半導体チップと印刷回路基板間の電気的連結構造物及
びその連結方法においては、次のような不都合な点があ
った。、先ず、バンプを半導体チップのパッド上に一
体に形成するため、半導体チップの不良品が発生した場
合は、該バンプも一緒に交替するようになって、該バン
プの製造原価が浪費されるという不都合な点があった。
、バンプを形成するとき、マスクを形成して除去する
ため、汚染が発生するという不都合な点があった。、
バンプを形成するとき、高価な装備を用いるので原価が
上昇し、精密度が要求されて煩雑であるという不都合な
点があった。、不良品が発生した時は、部分的な補修
が全然不可能であるという不都合な点があった。However, the conventional electrical connection structure between the semiconductor chip and the printed circuit board and the method for connecting the same have the following disadvantages. First, since the bumps are integrally formed on the pads of the semiconductor chip, when a defective semiconductor chip occurs, the bumps are also replaced together, which wastes the manufacturing cost of the bumps. There was a disadvantage.
When forming the bumps, a mask is formed and removed, which causes a disadvantage that contamination occurs. ,
Since expensive equipment is used when forming the bumps, the cost is increased and precision is required, which is inconvenient. However, when a defective product occurs, there is a disadvantage that partial repair is impossible at all.
【０００４】[0004]
【課題を解決するための手段】本発明の目的は、マスク
の不必要な導電性ボールを用いる半導体チップと印刷回
路基板間の電気的連結構造物及びその連結方法を提供し
ようとするものである。SUMMARY OF THE INVENTION It is an object of the present invention to provide an electrical connection structure between a semiconductor chip and a printed circuit board using a conductive ball which does not require a mask, and a method for connecting the same. .
【０００５】そして、このような本発明の目的は、半導
体チップ上両方側辺部位に複数のパッドが夫々形成さ
れ、それらバッド上に金、銀及びそれらの混合物中何れ
一つを包含した導電性エポキシが所定量ずつ注入され、
それら導電性エポキシ上に錫、鉛及びそれらの混合物中
何れ一つにてなる導電性ボールが夫々付着され、それら
導電性エポキシを硬化した後、前記半導体チップを覆え
てそれら導電性ボール３６を印刷回路基板上の各付け段
に夫々合致させ、リフロー接合工程を施してそれら半導
体チップと印刷回路基板とを導電性エポキシ及び導電性
ボールにより電気的連結させる半導体チップと印刷回路
基板間の電気的連結構造及びその連結方法を提供するこ
とにより達成される。The object of the present invention is to form a plurality of pads on both sides of the semiconductor chip, and to provide a conductive material containing gold, silver or a mixture thereof on the pads. Epoxy is injected by a predetermined amount,
Conductive balls made of any one of tin, lead and a mixture thereof are attached on the conductive epoxy, and after curing the conductive epoxy, the conductive balls 36 are printed by covering the semiconductor chip. Electrical connection between the semiconductor chip and the printed circuit board is performed by matching each mounting step on the circuit board and performing a reflow bonding process to electrically connect the semiconductor chip and the printed circuit board with conductive epoxy and conductive balls. This is accomplished by providing a structure and a method of connecting the same.
【０００６】[0006]
【発明の実施の形態】以下、本発明の実施の形態に対し
図面を用いて説明する。本発明に係る半導体チップと印
刷回路基板間の電気的連結構造物においては、図２に示
したように、半導体チップ３０上両方側辺部位に複数の
パッド３２が所定間隔を置いて夫々直線状に形成され
る。次いで、図１（Ａ）に示したように、それらパッド
３２上に金Ａｕ、銀Ａｇ及びそれらの混合物中何れ一つ
を包含した導電性エポキシ３４が夫々所定量ずつ注入さ
れ、それら導電性エポキシ３４上に錫Ｓｎ、鉛Ｐｂ及び
それらの混合物中何れ一つにてなる導電性ボール３６が
夫々付着される。このとき、該導電性ボール３６は、錫
Ｓｎ６０ー９５％、鉛Ｐｂ４０ー５％にて形成すること
が好ましい。次いで、それら導電性エポキシ３４を１２
５ー１７５℃の温度で硬化させ、半導体チップ３０上に
導電性エポキシ３４と導電性ボール３６とでなる電気的
連結構造物を形成する。そして、このように達成された
本発明に係る電気的連結構造物を用い、半導体チップを
印刷回路基板上に連結させる方法を説明すると次のよう
である。即ち、半導体チップ３０上両方側辺部位に複数
のパッド３２を所定間隔を置いて夫々直線状に形成する
段階と、それらパッド３２上に導電性エポキシ３４を所
定量ずつ点状に注入する段階と、それら導電性エポキシ
３４上に導電性ボール３５を夫々付着する段階と、前記
各導電性エポキシ３４を１２５ー１７５℃の温度で硬化
させる段階と、それら導電性ボール３６の付着された半
導体チップ３０を覆えてそれら導電性ボール３６を印刷
回路基板４０上の各付け段３８に夫々合致させリフロー
の接合工程を施してそれら半導体チップ３０と印刷回路
基板４０とを導電性ボール３６により電気的連結させる
段階と、を順次行う。Embodiments of the present invention will be described below with reference to the drawings. In the electrical connection structure between the semiconductor chip and the printed circuit board according to the present invention, as shown in FIG. 2, a plurality of pads 32 are linearly formed on both sides of the semiconductor chip 30 at predetermined intervals. Is formed. Then, as shown in FIG. 1 (A), a conductive epoxy 34 containing any one of gold Au, silver Ag and a mixture thereof is injected on the pads 32 by a predetermined amount, respectively, and the conductive epoxy 34 is filled with the conductive epoxy 34. Conductive balls 36 made of any one of tin Sn, lead Pb, and a mixture thereof are deposited on 34. At this time, the conductive balls 36 are preferably formed of tin Sn 60-95% and lead Pb 40-5%. Then, the conductive epoxy 34
Curing is performed at a temperature of 5-175 ° C. to form an electrically connected structure composed of the conductive epoxy 34 and the conductive balls 36 on the semiconductor chip 30. A method of connecting a semiconductor chip to a printed circuit board using the electrical connection structure according to the present invention thus achieved will be described below. That is, a step of linearly forming a plurality of pads 32 on both sides of the semiconductor chip 30 at predetermined intervals, and a step of injecting a predetermined amount of a conductive epoxy 34 on the pads 32 in a dot shape. A step of attaching the conductive balls 35 on the conductive epoxy 34, a step of curing the conductive epoxy 34 at a temperature of 125-175 ° C., and a semiconductor chip 30 having the conductive balls 36 attached. And the conductive balls 36 are respectively fitted to the mounting steps 38 on the printed circuit board 40, and a reflow bonding process is performed to electrically connect the semiconductor chip 30 and the printed circuit board 40 by the conductive balls 36. And step are sequentially performed.
【０００７】[0007]
【発明の効果】以上説明したように本発明に係る半導体
チップと印刷回路基板間の電気的連結構造物及びその連
結方法においては、マスクの不必要な導電性ボールを用
いて半導体チップを印刷回路基板上に電気的連結するよ
うになっているため、従来のマスクを利用する場合の汚
染を無くし、原価を低廉化し得るという効果がある。As described above, in the electrical connection structure between the semiconductor chip and the printed circuit board and the connecting method according to the present invention, the semiconductor chip is printed by using the conductive balls which do not need a mask. Since it is electrically connected on the substrate, there is an effect that the contamination can be eliminated and the cost can be reduced when the conventional mask is used.
【図１】（Ａ）−（Ｃ）本発明に係る半導体チップと印
刷回路基板間の電気的連結構造物及びその連結方法を示
した断面図である。1A to 1C are cross-sectional views illustrating an electrical connection structure between a semiconductor chip and a printed circuit board according to the present invention and a connection method thereof.
【図２】本発明に係る半導体チップを示した概略斜視図
である。FIG. 2 is a schematic perspective view showing a semiconductor chip according to the present invention.
【図３】（Ａ）−（Ｅ）従来半導体チップと印刷回路基
板間の電気的連結構造物及びその連結方法を示した断面
図である。3A to 3E are cross-sectional views showing a conventional electrical connection structure between a semiconductor chip and a printed circuit board and a method of connecting the same.
１０、３０：半導体チップ １２、３２：パッド １４：マスク １６：電導性バンプ １８、３８：付け段 ２０、４０：印刷回路基板 ３４：導電性エポキシ ３６：導電性ボール 10, 30: Semiconductor chip 12, 32: Pad 14: Mask 16: Conductive bump 18, 38: Mounting step 20, 40: Printed circuit board 34: Conductive epoxy 36: Conductive ball
Claims (6)
結させる構造物であって、 半導体チップ上両方側辺部位に複数のパッドが所定間隔
を有して夫々直線状に形成され、それらパッド上に導電
性エポキシが夫々所定量ずつ注入され、それら導電性エ
ポキシ上に導電性ボールが夫々付着され、前記導電性エ
ポキシが硬化された後、それら導電性エポキシ上に付着
された導電性ボールを有する半導体チップが覆えられそ
れら導電線ボールが印刷回路基板上の各付け段に夫々連
結されるように構成される半導体チップと印刷回路基板
間の電気的連結構造物。1. A structure for electrically connecting a semiconductor chip to a printed circuit board, wherein a plurality of pads are linearly formed on both sides of the semiconductor chip at predetermined intervals, and the pads are formed linearly. A predetermined amount of conductive epoxy is injected onto the conductive epoxy, conductive balls are adhered onto the conductive epoxy, and the conductive epoxy is cured, and then the conductive balls attached onto the conductive epoxy are removed. An electrical connection structure between a semiconductor chip and a printed circuit board, which is configured to cover the semiconductor chip and have the conductive wire balls connected to each step on the printed circuit board.
びそれら混合物中何れ一つを含有してなるエポキシであ
る請求項１記載の半導体チップと印刷回路基板間の電気
的連結構造物。2. The electrical connection structure between a semiconductor chip and a printed circuit board according to claim 1, wherein the conductive epoxy is an epoxy containing any one of gold Au, silver Ag and a mixture thereof.
７５℃の温度で行われる請求項１記載の半導体チップと
印刷回路基板間の電気的連結構造物。3. Curing of the conductive epoxy is 125-1
The electrical connection structure between the semiconductor chip and the printed circuit board according to claim 1, which is performed at a temperature of 75 ° C.
それら混合物中何れ一つにてなる請求項１記載の半導体
チップと印刷回路基板間の電気的連結構造物。4. The electrical connection structure between a semiconductor chip and a printed circuit board according to claim 1, wherein the conductive ball is made of any one of tin Sn, lead Pb and a mixture thereof.
％、鉛Ｐｂ４０ー５％を包含して形成される請求項１記
載の半導体チップと印刷回路基板間の電気的連結構造
物。5. The conductive ball is tin Sn: 60-95.
%, And lead Pb 40-5%, the electrical connection structure between the semiconductor chip and the printed circuit board according to claim 1.
る方法であって、 半導体チップ上面両方側辺部位に複数のパッドを所定間
隔を有して形成する段階と、それらパッド上に導電性エ
ポキシ上を点状に所定量ずつ注入する段階と、それら導
電性エポキシに導電性ボールを夫々付着する段階と、前
記各導電性エポキシを所定温度下で硬化させる段階と、
それら導電性ボールの付着された半導体チップを覆えて
それら導電性ボールを印刷回路基板上の各付け段に夫々
合致させリフロー接合を施して半導体チップと印刷回路
基板とを導電性ボールにより電気的連結させる段階と、
を順次行う半導体チップと印刷回路基板間の電気的連結
方法。6. A method of connecting a semiconductor chip to a printed circuit board, the method comprising: forming a plurality of pads on both sides of the upper surface of the semiconductor chip with predetermined intervals; and a conductive epoxy on the pads. A step of injecting a predetermined amount in a dotted manner on the top, a step of attaching conductive balls to the conductive epoxy, and a step of curing the conductive epoxy at a predetermined temperature,
The semiconductor chips to which the conductive balls are attached are covered, and the conductive balls are respectively matched with the respective mounting steps on the printed circuit board and reflow bonding is performed to electrically connect the semiconductor chip and the printed circuit board with the conductive balls. And the stage
A method of electrically connecting a semiconductor chip and a printed circuit board to sequentially perform the steps.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950036168A KR100201385B1 (en) | 1995-10-19 | 1995-10-19 | Attaching method of conductive ball, for chip size package |
| KR95P36168 | 1995-10-19 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH09129681A true JPH09129681A (en) | 1997-05-16 |
| JP2691891B2 JP2691891B2 (en) | 1997-12-17 |
Family
ID=19430681
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8002100A Expired - Fee Related JP2691891B2 (en) | 1995-10-19 | 1996-01-10 | Electrical connection structure between semiconductor chip and printed circuit board and method for connecting the same |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JP2691891B2 (en) |
| KR (1) | KR100201385B1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113168501A (en) * | 2019-02-19 | 2021-07-23 | 西部数据技术公司 | Socket interconnect with compressible ball contacts for high pad count memory cards |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100445296B1 (en) * | 2002-07-22 | 2004-08-21 | 주식회사 플렉시스 | Flip Chip On Film And The Fabricating Method Thereof |
-
1995
- 1995-10-19 KR KR1019950036168A patent/KR100201385B1/en not_active IP Right Cessation
-
1996
- 1996-01-10 JP JP8002100A patent/JP2691891B2/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113168501A (en) * | 2019-02-19 | 2021-07-23 | 西部数据技术公司 | Socket interconnect with compressible ball contacts for high pad count memory cards |
Also Published As
| Publication number | Publication date |
|---|---|
| KR970024034A (en) | 1997-05-30 |
| JP2691891B2 (en) | 1997-12-17 |
| KR100201385B1 (en) | 1999-06-15 |
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