JPH09252009A - Semiconductor device and method for manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a semiconductor device provided with a gate which has a low resistance in spite of miniaturization. SOLUTION: This semiconductor device is provided with a semiconductor substrate 1, a conductive film 5 formed on the surface of the semiconductor substrate which comprises a gate electrode, side wall conductive films 6 formed on the side walls of the conductive film, impurities areas 3a and 3b formed on the surface area of the semiconductor device which sandwiches the conductive film from both sides and a film 12 made of precious metals comprising the gate electrode which extends on the insulating film and at least a part of the side wall conductive films.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

[0002]

2. Description of the Related Art Generally, as a means for improving the performance of Schottky gate type field effect transistors, the gate length has been reduced. However, when the film thickness of the gate electrode is constant, the gate resistance increases with the miniaturization, the high-frequency transconductance is lowered, and the high-frequency noise characteristic is directly adversely affected. Therefore, in the above case, the method of increasing the film thickness of the gate electrode to reduce the resistance is adopted. However, since it is generally difficult to finely process a thick metal film, there is a method in which a Schottky gate is first formed on a semiconductor substrate by using an ordinary method and then metal is further stacked on the gate by, for example, a plating method. To be

A manufacturing process of a conventional semiconductor device having a structure in which a metal layer is stacked on a Schottky gate as described above will be described with reference to FIG.

First, as shown in FIG. 3A, the channel layer 22 is formed in the surface region of the semiconductor substrate 21 by ion implantation or the like.
Then, a tungsten nitride film is formed on the entire surface of the substrate 21, and then the tungsten nitride film is patterned by using a photolithography technique to form a gate electrode 25. Next, impurity ions are implanted into the surface regions of the substrate 21 on both sides of the gate electrode 25 to form low-concentration impurity regions 23a. Subsequently, an insulator (for example, a film (not shown) made of SiO ₂ ) is deposited on the entire surface of the substrate 21 and anisotropic etching such as RIE is performed to form a sidewall (not shown) of the gate electrode 25. Impurity ions are implanted using this side wall as a mask to form a high-concentration impurity region 23b adjacent to the impurity region 23a in the surface region of the substrate 21, and then the side wall is removed (see FIG. 3A).

Next, annealing is performed to make the impurity regions 23.
After activating a and 23b, a metal film 27 having a thickness of, for example, 500 Å or more, which is a base electrode during plating, is formed on the entire surface of the substrate 21 by vapor deposition (FIG. 3B).
reference). Gold or copper is used as the material of the metal film 27.

Next, a resist is applied thickly on the entire surface of the substrate 21 and then exposed and developed to form a resist pattern 30 having an opening on the gate electrode 25 (FIG. 3).
(C)). Then, a metal layer 32 made of, for example, gold is formed on the metal film 27 on the gate electrode 25 in the opening of the resist pattern 30 by plating (see FIG. 3C).

Next, after removing the resist pattern 30 with a removing solution, ion milling is performed to leave the metal film under the metal layer 32 and remove the metal film 27 in other regions (see FIG. 3D). ). Then, on the impurity region 23b, the source
After forming a drain electrode (not shown), the semiconductor device is completed by covering it with a passivation film.

[0008]

In the semiconductor device manufactured by the above-described conventional manufacturing method, the size of the gate electrode 25 is limited by the opening size of the plating mask resist 30 and the alignment accuracy, and the size of the gate electrode 25 is 1 μm or less. There is a problem that it is not possible to form a low resistance gate.

For example, the minimum size of the gate length that can be formed when a stepper using the g-line is formed is such that the resolution limit of the resist pattern 30 is about 0.7 μm and the variation is ±.
Since it is 0.1 μm, 0.8 under the worst conditions
μm (see FIG. 4A). Considering the pattern alignment accuracy of ± 0.2 μm, the minimum gate length is 1.2 μm (see FIG. 4A). Therefore, when it is attempted to form the gate electrode 25 having a gate length of 1.0 μm or less, the laminated metal layers 27 and 32 are formed on the side portions of the gate electrode 25 as shown in FIG. There is a problem that the electrodes are electrically connected to the source / drain regions.

The present invention has been made in consideration of the above circumstances, and an object of the present invention is to provide a semiconductor device having a gate electrode which has a low resistance even when miniaturized, and a manufacturing method thereof.

[0011]

[Means for Solving the Problems]

[Summary] A first aspect of a semiconductor device according to the present invention is a semiconductor substrate, a conductive film formed on a surface of the semiconductor substrate, a sidewall insulating film formed on a sidewall of the conductive film, and the conductive film. An impurity region formed in a surface region of the semiconductor substrate so as to sandwich the film from both sides, and a film made of a noble metal material extending on a partial region of the conductive film and at least the sidewall insulating film are provided. Is characterized by.

A second aspect of the semiconductor device according to the present invention is the semiconductor device according to the first aspect, wherein the impurity region is a first impurity region formed in self-alignment with the conductive film, and the sidewall insulating film. And a second impurity region formed in a self-aligned manner.

A first aspect of the method for manufacturing a semiconductor device according to the present invention is the step of forming a conductive film on the surface of a semiconductor substrate, the step of forming a side wall insulating film on the side wall of the conductive film, and plating. Or a lift-off method, a step of forming a film made of a noble metal material on the conductive film and the sidewall conductive film. [Operation] According to the semiconductor device and the method for manufacturing a semiconductor device of the present invention configured as described above, the film made of a noble metal material forming the gate electrode is the conductive film forming the gate electrode and at least the gate electrode. Since it extends over the partial region of the side wall insulating film, there is no characteristic abnormality due to misalignment, and a low resistance gate can be obtained even if the gate length is miniaturized.

[0014]

DETAILED DESCRIPTION OF THE INVENTION A first embodiment of a method of manufacturing a semiconductor device according to the present invention will be described with reference to FIG. First, as shown in FIG. 1A, a channel layer 2 is formed in a surface region of a semiconductor substrate 1 by an ion implantation method or the like, and then a film of tungsten nitride having a thickness of 0.5 μm, for example, is formed on the entire surface of the substrate 1. After that, the gate electrode 5 is formed by patterning the tungsten nitride film using a photolithography technique. Then, impurity ions are implanted into the substrate 1 to form low-concentration impurity regions 3a (LDD structure) sandwiching the gate electrode 5 from both sides. Subsequently, an insulator, for example, a film (not shown) made of SiO ₂ is deposited on the entire surface of the substrate 1 and anisotropic etching such as RIE is performed to form a sidewall insulating film of the gate electrode 5. Impurity ions are implanted using this sidewall insulating film as a mask to form a high-concentration impurity region 3b, and then the sidewall insulating film is removed and an annealing process is performed to activate the impurity regions 3a and 3b ( See FIG. 1 (a). This annealing treatment is performed after ion implantation of impurities, but considering the influence of the annealing of the sidewall insulating film on the crystalline state of the substrate and the influence of a noble metal film to be formed later, it is preferable to perform after the sidewall insulating film is removed. .

Next, an insulating film such as SiO ₂ is formed on the entire surface of the substrate 1.
A film is deposited and anisotropic etching such as RIE is performed to form a sidewall insulating film 6 of the gate electrode 5 adjacent to the impurity region 3a (see FIG. 1B).

Next, a metal film 7 made of gold, for example, having a thickness of 500 angstroms or more is formed on the entire surface of the substrate 1 to serve as a base electrode during plating (see FIG. 1C).

Next, a resist (thickness: 3 μm, for example) is applied over the entire surface of the substrate 1 and then exposed and developed to cover an area on the gate electrode 5 and have an opening extending on the sidewall insulating film 6. A resist pattern 10 is formed (FIG. 1
(D)). Then, the opening of the resist pattern 10 is plated with a noble metal material such as gold having a thickness of 2 μm by plating to cover a part of the gate electrode 5 and the side wall insulating film 6.
The metal layer 12 having a certain degree is formed (see FIG. 1D).

Next, after the resist pattern 10 is stripped with a stripping solution, ion milling is performed to remove the noble metal film under the metal layer 12 and remove the metal film 7 in other regions (FIG. 1).
(E)). Then, after forming source / drain electrodes (not shown) which make ohmic contact with the substrate on the impurity regions 3b, a semiconductor device is completed by covering with a interlayer insulating film (not shown) and a passivation film (not shown).

As described above, according to the present embodiment, it is possible to form the metal layer 12 that covers the gate electrode 5 and extends over a part of the region on the sidewall insulating film 6.
There is no characteristic abnormality due to misalignment, and a low resistance gate can be obtained even if the gate length is miniaturized.

Although gold is used as the material of the metal layer 12 in the above-mentioned embodiment, the present invention is applicable to the case of using a noble metal material which has a low resistance but is difficult to remove by etching and is formed by a plating method. There is no problem due to misalignment,
In addition, a low resistance gate electrode can be obtained. Examples of such precious metals include copper and platinum.

Next, a second embodiment of the method of manufacturing a semiconductor device according to the present invention will be described with reference to FIG. The manufacturing method of this embodiment is the same as that of the first embodiment shown in FIGS. 1A to 1B until the sidewall insulating film 6 of the gate electrode 5 shown in FIG. 2B is formed. To do.

After that, a resist is thickly applied to the entire surface of the substrate 1 and then exposed and developed to form a gate electrode 5.
Then, a resist pattern 11 having an inversely tapered opening exposing the sidewall insulating film 6 is formed (see FIG. 2C). Then, using the resist pattern 11 as a mask, the metal films 13, 13 having a sufficient film thickness for reducing the resistance are formed.
a is deposited. If the material of the metal film 13 is gold, 1 μm
The above film thickness is used.

After that, the resist pattern is removed by a lift-off method with a stripping solution to remove unnecessary portions of the metal film 1.
3a is removed (see FIG. 2 (d)). Subsequently, as in the case of the first embodiment, after forming source / drain electrodes (not shown) for forming ohmic junctions on the impurity regions 3b, an interlayer insulating film (not shown) and a passivation film (see FIG. (Not shown) to complete the semiconductor device.

In the second embodiment as well, similar to the first embodiment, the metal layer 13 which covers the gate electrode 5 and extends over a part of the region on the sidewall insulating film 6 can be formed. Therefore, a gate having low resistance can be obtained even if the gate length is reduced.

The metal layer 1 is used in the above embodiment.
Although gold was used as the material of No. 3, it is possible to use even a metal that has a low resistance but cannot be plated and is difficult to etch if it can be formed by the lift-off method.

In the first or second embodiment,
Since the metal layers 7, 12, 13 to be laminated generally have poor heat resistance, the annealing for activation is performed by the metal layers 7, 12,
It is better to go before 13 is laminated.

[0027]

As described above, according to the semiconductor device and the method for manufacturing the semiconductor device of the present invention, it is possible to obtain a semiconductor device having a gate with a low resistance even if it is miniaturized without causing characteristic abnormality due to misalignment. .

[Brief description of drawings]

FIG. 1 is a manufacturing step sectional view of a first embodiment of a method of manufacturing a semiconductor device according to the present invention.

FIG. 2 is a sectional view of a manufacturing process of the second embodiment of the method of manufacturing a semiconductor device according to the present invention.

FIG. 3 is a sectional view of a conventional semiconductor device manufacturing process.

FIG. 4 is an explanatory diagram illustrating a problem of a conventional method for manufacturing a semiconductor device.

[Explanation of symbols]

 1 Semiconductor Substrate 2 Channel Layer 3a Low Concentration Impurity Region 3b High Concentration Impurity Region 5 Gate Electrode (Stem) 6 Sidewall Insulation Film 7 Base Electrode Film (Metal Film) 10 Resist Pattern 11 Resist Pattern 12 Metal Layer 13 Metal Layer 13a Excess metal layer 14 Metal film (capsule) 21 Semiconductor substrate 22 Channel layer 23a Low concentration impurity layer 23b High concentration impurity layer 25 Gate electrode 27 Base electrode film 30 Resist pattern 32 Metal layer

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H01L 29/772

Claims (3)

[Claims] 1. A semiconductor substrate, a conductive film formed on a surface of the semiconductor substrate, a sidewall insulating film formed on a sidewall portion of the conductive film, and a semiconductor film of the semiconductor substrate sandwiching the conductive film from both sides. A semiconductor device comprising: an impurity region formed in a surface region; and a film made of a noble metal material extending over the conductive film and at least a partial region of the sidewall insulating film. 2. The impurity region includes a first impurity region formed in the conductive film in a self-aligned manner and a second impurity region formed in the sidewall insulating film in a self-aligned manner. The semiconductor device according to claim 1. 3. A step of forming a conductive film on a surface of a semiconductor substrate, a step of forming a sidewall insulating film on a sidewall portion of the conductive film, and a plating method or a lift-off method on the conductive film and the sidewall conductive film. And a step of forming a film made of a noble metal material that extends on the film.