JPH09246998A - Error correction device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate useless power consumption by an external code decoder in the case that error correction by an external code is not required by specifying which one of internal code and external code error flags is to be outputted by the flag of 1 byte that is Sel EF. SOLUTION: The error correction by an internal code is performed to video data in an internal code decoder 23. A flag corresponding to the result is put in the internal code error flag of a bit 7 in an EF. Then, the Sel EF is defined as '1'. They are sent to a write processing to an SDRAM 30. When the video data for one error correction block are accumulated, they are sent to an external code decoder and corrected when a block internal code error is not present at all. Than, corresponding to the Sel EF, whether it is internal code error flag or the external code error flag is judged, the error corrected video data, the external code error flag and the Sel EF are sent to the write processing to the SDRAM 30 and the data written in the SDRAM 30 are read and outputted as digital video data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error correction device used for decoding digital data error-correction-encoded using a product code.

[0002]

2. Description of the Related Art Currently, A / V (audio / video) such as DVCR (digital video cassette recorder)
In an apparatus which digitally records / reproduces a signal on / from a recording medium such as a magnetic tape, encoding by a product code is often used for error correction.

In the coding by the product code, the data arranged in a matrix in units of 1 symbol (for example, 1 byte) is coded in the column direction, for example, by the Reed-Solomon code. Code parity is generated. Then, the data and outer code parity are encoded in the row direction to generate inner code parity. As described above, the outer code parity is generated in the column direction and the inner code parity is generated in the row direction, so that the error correction coding by the product code is performed. At this time, the time-series order of the data coincides with, for example, the row direction.

FIG. 16 shows an example of the configuration of a digital recording / reproducing apparatus according to the prior art, which uses this product code encoding. For example, digital video data is recorded as BRR (Bit R
ate Reduction) is supplied to the encoder 101. This B
The RR encoder 101 compresses the supplied recording data. The compressed recording data is
It is supplied to the error correction encoder 102 which performs the error correction encoding by the above product code.

The error correction encoder 102 has an RA
M (not shown), and the supplied recording data is written to the RAM. Then, as described above, the outer code parity and the inner code parity are generated with respect to the recording data supplied and written in the RAM memory, and the error correction encoding of the product code is performed.
The encoded recording data is read from the RAM according to the row direction described above, supplied to the recording drive unit 103 including an amplifier for recording, and recorded on the magnetic tape 105 by the magnetic head 104.

Recording at this time is performed by, for example, the magnetic head 1.
The magnetic head 104 is provided on a rotating drum.
Is performed by a helical scan method in which tracks are formed obliquely with respect to the magnetic tape 105.

The data recorded on the magnetic tape 105 is read by the magnetic head 106 to be reproduced data. This reproduced data is supplied to the inner code decoder 108 via the equalizer 107, and error correction by the inner code is performed. That is, error correction is performed for each row based on the inner code parity allocated to each row of data. Then, as an error correction result, an error flag is attached to the symbols in each row. This is because, for example, if the number of errors exceeds the error correction capability of the code and the errors remain uncorrected, an error flag is attached to all symbols in the line to indicate that there is an error. To be done.

This reproduced data in which the inner code is error-corrected is written in the RAM 109. The inner code decoder 108 can control the address of the RAM 109, and the reproduction data written in the RAM 109 is address-controlled by the inner code decoder 108 and arranged in the address space of the RAM 109.

When the error correction by the inner code is performed in the inner code decoder 108 in this way, the error-corrected reproduced data is read from the RAM 109. At this time, the reproduction data is read out in the column direction of the product code of the RAM 109 by the address control by the decoder 108. Therefore, this RAM 109
In, the order of data is read in the direction of the outer code.

The reproduced data read in the outer code direction is supplied to the outer code decoder 110, and the outer code decoder 110 corrects the error by the outer code. That is, error correction is performed for each column based on the outer code parity allocated to each column of data. In the error correction using the outer code, an error flag attached to each symbol at the time of decoding in the inner code decoder 108 is used together with the outer code.

The reproduced data which has been error-corrected in the outer code decoder 110 is written in the RAM 111. The outer code decoder 110 can control the address of the RAM 111.
The reproduction data written in 111 is the outer code decoder 1
The address is controlled by 10 and is arranged in the address space in the RAM 109.

Then, as an error correction result, an error flag is attached to each symbol. This is, for example,
If the number of errors exceeds the error correction capability of the code and no error correction has been performed, this is added to indicate that an error exists.

When the outer code decoder 110 corrects the error by the outer code, the error-corrected reproduced data is read from the RAM 111. At this time, the reproduced data is read out in the row direction in the address space of the RAM 111 by the address control by the decoder 110. Therefore, in the RAM 111, the read direction read at the time of reading from the RAM 109 is read again, and the original read direction, that is, the original data order is returned.

The reproduced data subjected to the error correction by the inner code and the outer code is supplied to the BRR decoder 112. In the BRR decoder 112, the data compression applied to the data at the time of recording is released. This decompressed reproduction data is output to the outside as digital video data via the interface 113.

Incidentally, with respect to the data to which the error code is not completely corrected in the outer code decoder 110, the error correction is thereafter performed by using a method such as interpolation.

In the digital recording / reproducing apparatus as described above, the BRR encoder 101 on the recording side is practically used.
Each of the error correction encoder 102 and the error correction encoder 102 is configured by one integrated circuit. Also, on the reproduction side, the inner code decoder 108, the outer code decoder 110, and the BRR
Each decoder 112 is composed of one integrated circuit.

[0017]

By the way, a DVC for recording data on a magnetic tape by a helical scan method.
In the case of R, the head traverses a plurality of tracks formed on the tape at the time of high-speed reproduction in which the tape speed is made several to several tens of times faster than the tape speed at the time of recording. Then, the reproduction processing is performed by using the data of the plurality of tracks as data for one field. Therefore, error correction by the inner code that performs error correction in the row direction of the product code is performed, but error correction by the outer code that performs error correction in the column direction is not performed.

Conventionally, even in the case of this high-speed reproduction, since the reproduction data has to be supplied from the inner code decoder 108 to the outer code decoder 110 although it is not necessary, wasteful processing is unnecessary. This is performed in the decoder 110, and as a result, useless power is consumed.

Similarly, the first inner code decoder 10
Even if there is no error in the error correction by 8 or all the errors are corrected, and as a result, the error correction in the outer code decoder 110 is unnecessary, the reproduction data from the inner code decoder 108 to the outer code decoder 110 is reproduced. However, even in this case, there is a problem that useless power is consumed.

Further, in the above-mentioned conventional technique, in the outer code decoder 110, in order to perform error correction on the data sent from the inner code decoder 108 by the outer code as it is, an error flag is attached to all the symbols of the data. The inner code decoder 108 to the outer code decoder 110.
Was sending data to. However, since the inner code decoder 108 only outputs an error flag for each sync, adding an error flag for each symbol to all symbols in this way is wasteful.

Further, since an error flag is added to each symbol in the inner code decoder 108, if the reproduced data is, for example, 8 bits, data of 8 bits + error flag 1 bit = 9 bits is stored in the RAMs 109 and 11.
It was written in 1. Therefore, there is a problem that the data bus width is 9 bits, which lacks versatility. Therefore, the cost was also increased.

Therefore, an object of the present invention is to provide an error correction device which eliminates unnecessary power consumption by the outer code decoder when the error correction by the outer code is unnecessary.

Another object of the present invention is to provide an error correction device capable of performing internal processing with a versatile data bus width such as 8 bits.

[0024]

SUMMARY OF THE INVENTION In order to solve the above problems, the present invention provides an inner code decoder for performing error correction by an inner code and an error correction by an outer code after the error correction by the inner code decoder. In the data format in the error correction device, an outer code decoder for performing an internal code error flag indicating whether or not an error exists as a result of error correction by the inner code, and an inner code An error flag selection flag indicating which of the inner code error flag obtained by performing the error correction and the outer code error flag obtained by performing the error correction by the outer code is effective is set. An error correction device characterized in that a storage area is provided.

As described above, according to the present invention, the flag indicating whether or not an error exists as a result of the error correction by the inner code, and which of the inner code and the outer code the error flag by which the error correction is effective is effective. Since the flag indicating is stored in the data format, the error correction by the outer code can be canceled if necessary.

[0026]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 schematically shows an example of the configuration of a digital video recording / reproducing device to which an error correction device according to the present invention is applied. In the present invention, an inner code decoder that performs error correction by an inner code when decoding data encoded by a product code,
In addition, an outer code decoder for performing error correction using an outer code is formed in one integrated circuit. Also,
The RAM for data replacement, which was conventionally required for the inner code decoder and the outer code decoder, is shared by controlling access to the RAM in a time division manner.

In FIG. 1, recording data including, for example, video data and 4-channel audio data is supplied to a BRR encoder 2 via an interface 1. In the BRR encoder 2, the supplied recording data is subjected to data compression. This compression is
For example, the data supplied to the BRR encoder 2 is converted into blocks, DCT-transformed, quantized, and variable-length coded. The recording data compressed in this way is supplied to the error correction encoder 3.

The error correction encoder 3 is a RAM
(Not shown), and the supplied recording data is written to the RAM. And supplied R
For this recording data written in the AM memory, an outer code parity and an inner code parity are generated and error correction coding of a product code is performed, as described in the above-described related art. The size of the data in which the product code of the inner code and the outer code is completed is called an error correction block.

The encoded data from the error correction encoder is read from the RAM according to the row direction described above, supplied to the recording drive unit 4 including an amplifier for recording, and recorded on the magnetic tape 6 by the magnetic head 5. It This recording is performed by a helical scan method in which tracks are formed obliquely with respect to the magnetic tape 6 by a magnetic head 5 provided on a rotating drum, and further, a set of magnetic heads having different angles from each other. The azimuth method is used in which different azimuths are recorded in adjacent tracks.

As an example of this recording method, when four magnetic heads 5 are provided on a rotary drum and channels corresponding to the heads are A, B, C and D, these four magnetic heads 4 are used. Tracks are formed in the order of A, B, C, and D. Of these, A and C and B and D are tracks whose azimuths match. At this time, a segment is composed of two adjacent tracks (A and B channels and C and D channels) having different azimuths. Also, the audio data having four channels is arranged, for example, in the center of the track so as to be sandwiched between the video data.

The data recorded on the magnetic tape 6 is read by the magnetic head 7 in the order in which the recording data is recorded, and is used as reproduction data. The read reproduction data is supplied to an error correction decoder 9 via an equalizer 8. This error correction decoder 9
Is configured such that an inner code decoder and an outer code decoder are configured as one integrated circuit, and can perform address control for the connected RAM 10.

The reproduced data supplied to the error correction decoder 9 is error-corrected by the inner code, and is address-controlled and written in the RAM 10. When the data for one error correction block accumulates in the RAM 10 in this manner, the data is read in the outer code direction and supplied to the error correction decoder 9 in order to perform error correction using the outer code. The supplied data is subjected to error correction using an outer code, and is written into the RAM 10 again. In this way 1
When the error correction for the error correction block is completed, the data is read out from the RAM 10 in the inner code direction (the order of the original data) under the control of the error correction decoder 9 and output. At this time, if an error exists beyond the error correction capability of the code, an error flag is attached to a predetermined position with respect to the data and output.

At the time of data input / output at the time of error correction by the inner code and the outer code in the RAM 10,
There is a difference in processing unit between video data and audio data in A / V data.
Since the data for the error correction by the outer code and the output for the error-corrected output occur in one RAM, the timing of writing and reading the data to and from the RAM 10 intersects. Therefore, this RAM 10
The control of the timing of writing and reading data to and from is performed in a time division manner under the control of the error correction decoder 9. Details of this control will be described later.

The reproduced data output from the error correction decoder 9 is supplied to the BRR decoder 11. In the BRR decoder 11, the data compression applied to the data at the time of recording is released. For example, the BRR decoder 11
The data supplied to is variable-length decoded and dequantized,
The compression is released by inverse DCT and inverse block transform. The reproduced data thus decompressed is output to the outside as digital video data via the interface 12.

Incidentally, with respect to the data to which the error correction decoder 9 cannot correct the error and the error flag is added, thereafter, the error correction is performed by using a method such as interpolation.

2 and 3 schematically show an example of the configuration of the above-mentioned error correction block. In this example, one frame of data is composed of 12 tracks formed on a magnetic tape. Further, as described above, a segment is formed by setting two adjacent tracks having different azimuths as one set, and one frame consists of 12 tracks = 6 segments. These segments include 0-
Segment numbers up to 5 are assigned.

In the example of the video data shown in FIG. 2, one track in these 12 frames forms one error correction block shown in FIG. 2B as in FIG. 2A. For example, for video data having a data array of 217 bytes × 226 bytes, data in each column is encoded by, for example, a (250,226) Reed-Solomon code in the direction of arrow b to generate a 24-byte outer code parity. Is done. Further, with respect to the video data and the outer code parity, the data of each row is, for example, (2
29, 217) Reed-Solomon code is used to generate 12-byte inner code parity. Also,
Sync data and ID each having a size of 2 bytes are arranged at the head of each data row.

FIG. 3 shows an example of the structure of an error correction block in audio data. As shown in FIG. 3A, audio data forms one error correction block in 6 tracks out of 12 tracks for one frame. For example, audio data composed of a data array of 217 bytes × 12 bytes is encoded in the direction of arrow b by, for example, a (24,12) Reed-Solomon code to generate a 12-byte outer code parity. Further, the video data and the outer code parity are encoded in the direction of arrow a by, for example, a (229,217) Reed-Solomon code, and a 12-byte inner code parity is generated. Sync data and ID are arranged at the head of each data line.

FIG. 4 schematically shows the structure of one sync block in these error correction blocks, taking video data as an example. The first two bytes are sync data. The subsequent 2 bytes are an ID, and the number (segment number) in one track of this one sync block, the sync block number, etc. are described. This ID is followed by 217 bytes of video data (or outer code parity) and inner code parity. The recording data on the magnetic tape is a sequence of the sync blocks.

FIG. 5 shows an example of the configuration of the error correction decoder 9 described above. This error correction decoder 9 is configured as one integrated circuit. This error correction decoder 9
Corresponds to one azimuth of the two azimuths of the magnetic head. That is, one error correction decoder 9
Is supplied with data of the A and C channels, for example. Therefore, in the above-described digital video recording / reproducing apparatus, an error correction decoder for processing the data of the B and D channels is provided. Since the other error correction decoder has the same configuration as the error correction decoder 9 shown in FIG. 5, the description thereof is omitted.

Reproduction data consisting of audio data and video data is supplied from the equalizer 8 to a serial / parallel conversion circuit (hereinafter referred to as S / P) 20.
The reproduced data output from the equalizer 8 as bit serial data at a bit rate of 94 MHz, for example, is converted into 8-bit parallel data at 11.7 MHz at the S / P 20. The parallel data is supplied to the sync detection circuit 21 to detect the sync data, and is supplied to the rate converter 22.

The rate converter 22 has a memory therein and converts the data rate by accumulating the supplied data and changing the clock.
In this example, the data rate of the reproduced data is 11.7 MHz.
Is converted to a higher rate, for example, 46.4 MHz. The conversion to such a high rate is performed so that writing and reading of data are performed by time-division processing in a memory controller described later.

The reproduced data whose rate has been increased by the rate converter 22 is supplied to the inner code decoder 23. Then, the inner code decoder 23 performs error correction by the inner code for each sync block. At this time, when an error exceeding the error correction capability of the code is included in the data, error correction is not performed, and a flag indicating that there is an error is added to the data.

Further, the error correction information at this time is supplied to the error counter 24. The error counter 24 counts the number of errors in the inner code error correction decoder 23, and supplies the count result to the interface 26 via the bus 25. On the other hand, the reproduced data that has been error-corrected by the inner code error correction decoder 23 is supplied to the ID interpolation circuit 27.

The reproduced data supplied to the ID interpolating circuit 27 is subjected to ID reassignment for internal processing, and the descramble circuit 28 performs a process reverse to the scrambling by the scrambling circuit on the encoder side. For example, continuous signals of the same level such as '1111' and '0000' are prevented. The output of the descramble circuit 28 is supplied to a memory controller 29.

This memory controller 29 has an SDR
AM 30 is connected. The memory controller 29 performs address control and data write / read control with respect to the SDRAM 30. Note that SD
The RAM 30 is a clock synchronous RAM, and has a capacity of, for example, 16 Mbit.

Further, in the memory controller 29, it is judged whether the supplied reproduction data is written in the SDRAM 30, supplied to the video outer code decoder 31 or outputted as it is. This decision
For example, it may be performed based on information added to the reproduction data inside the error correction decoder. Further, it can be performed based on information supplied from outside via the interface 26.

When the reproduced data needs to be error-corrected by the outer code, the supplied data is written in the SDRAM 30 under the control of the memory controller 29, and is read in the outer code direction to be read out in the video outer code decoder 31. Is supplied to. The supplied data is subjected to error correction by an outer code by a video outer code decoder 31, and an outer code error flag is added as an error correction result. The error-corrected reproduction data is written to the SDRAM 30 via the memory controller 29. Then, data is read from the SDRAM 30 in the time-series direction, and output to the outside via the memory controller 29.

If error correction is not necessary for the reproduced data, this data is stored in the memory controller 2
9 is output to the outside without being sent to the video outer code decoder 31. In this case, data may be read out from the SDRAM 30 and output, or may be output directly from the memory controller 29. The control of the data error correction will be described later.

The read audio data is supplied to the audio outer code error correction decoder 32. Then, the decoder 32 performs error correction using an outer code. At this time, only one azimuth data such as the A and C channels is supplied to the one error correction decoder 9. Unlike the video data described above,
With regard to audio data in which one error correction block is formed by six tracks, an error correction block cannot be formed only by data of one azimuth and error correction cannot be performed. Therefore, for example, B and D channel data is supplied from the other error correction decoder (not shown) to the audio outer code decoder 32 of the error correction decoder 9. On the other hand, the reproduced audio data of the A and C channels is supplied to the outer audio code decoder of the other error correction decoder.

Even when the error correction is performed on the audio data by the outer code, if an error exists beyond the error correction capability of the code, the error flag is added to the audio reproduction data. .

The reproduced audio data whose error has been corrected in this way is supplied to the rate converter 33.
For example, a clock of an audio signal of 256 fs (12.3 MHz) is used. Rate converter 3
3 is supplied to the deshuffling circuit 34.
In the time axis direction, the data is properly rearranged and supplied to the conceal circuit 35. In the concealing circuit 35, data correction is performed based on an error flag added to the data. Then, the modified reproduced audio data is output to the outside.

The video VAUX circuit 36 extracts VAUX data from the video data supplied to the memory controller 29. Audio AU
AAUX data is extracted from the output of the audio outer code decoder 32 by the X circuit 37. The extracted VAUX data and AAUX data are sent to an external device via the bus 25 and the interface 26. Here, VAUX data and AAUX data are auxiliary data related to video data and audio data, respectively.

The various timing signals used in the error correction decoder 9 are generated by the timing signal generation circuit 38. The error counter 24
As described above, the inner code error correction decoder 23
Further, the number of errors at the time of decoding in the outer video code decoder 31 is supplied. The number of errors counted by the error counter 24 based on these supplied signals is sent to the outside via the bus 25 and the interface 26. This makes it possible to measure an error rate and the like.

Inside the error correction decoder 9, one sync block of data is treated as one packet. FIG. 6 shows an example of the data structure of this one packet. Here, 8 bits of data are treated as one symbol. ID0 and ID1 are more detailed IDs in the data structure of one sync block shown in FIG. An example of the contents of this data is given below.

ID0 ... Sync block number ID1 ... Segment number, video / audio identification information, etc. Data0-Data216 ... Video data or audio data ID2 ... Tape running direction, normal playback, high-speed playback, etc. Auxiliary information such as driving mode EF ... Information about error in sync block unit Rcount ... During high-speed playback such as fast-forward playback
Information indicating how many times the video data was output without updating the data due to an error or the like PID0 ... Sync block number predicted based on the head switching signal of the magnetic head Outer code error flag ... Outer An error flag added with 1 bit for each symbol after error correction by code

Among these, in the inner code decoder 23, when the number of error symbols exceeds the error correction capability of the code and the error cannot be corrected, that is, when there is an error in the output of the decoder 23, the EF is compared with the EF. Error flag is set. FIG. 7 shows the bit configuration of this EF. Bit 7 is an inner code error flag corresponding to the error correction result of the inner code. Bit 6 Sel EF
Indicates which of the inner code error flag and the outer code error flag is valid in the video data finally output from the error correction decoder 9. This means that, for example, if Sel EF = '1', the inner code error flag is valid, and if it is '0', the outer code error flag is valid. Bit 0 to bit 5 are undefined.

FIG. 8 shows an example of a format in which reproduction data for one sync block is written in the SDRAM 30. Since this SDRAM 30 has a data width of 16 bits, the data format of the 8-bit width shown in FIG. 6 is 16 bits as one word, and the number of words is also halved to 112 words. It

When this reproduced data is written in the SDRAM 30, the timing of the data is controlled by the control of the memory controller 29. The reproduction data is divided into video data and audio data for each segment and written into the SDRAM 30, and the address control at this time is also performed by the memory controller 2.
9 is performed.

9 and 10 show an example of address allocation in the SDRAM 30 by this address control. FIG. 9 shows row (column) address allocation.
In bits 8 to 10, video data is divided into segments 0 to 5, and audio data is fixed to "6". Like this bit 8
In 10 to 10, video data and audio data are prevented from colliding in address assignment. Also,
In the video data, bits 6 and 7 indicate the tape running direction, which is "0" for normal running and "1" for reverse running.
It is said. Further, bits 0 to 5 are B7 when the sync block number is represented by 8 bits B7 to B0.
6 bits of B2 are inserted.

In audio data, bit 6,
7 is fixed to "0". Also, bits 4 and 5
, The fields 0 to 3 are entered. Bits 2 and 3 are assigned to each of the four audio channels. Bits 0 and 1 contain a few bits (B2, B3) of the sync block number.

FIG. 10 shows the allocation of column (row) addresses. This column address allocation is common to audio data and video data. This SDR
The AM 30 has a two-bank configuration including a bank A and a bank B, and data is assigned to the bank A and the bank B. Also, in the column,
Bits 0 and 1 (B0, B1) of the sync block number are allocated so that data of four sync blocks 0, 1, 2, and 3 are mixed. S0 and S marked in the figure
1, S2 and S3 represent sync block data in which bits 0 and 1 (B0, B1) of these sync block numbers are 0, 1, 2, and 3, respectively.

Bits 0 and 1 in this column address
By combining the sync block allocation according to (4) and the sync block number allocation in the row address described above, address allocation can be performed for all sync blocks.

Column addresses 0 to 3 in bank A are assigned ID0 and ID1 shown in FIG. The column addresses 4 to 223 have data 0 to
109 is allocated. On the other hand, the data 110 to 215 are assigned to the column addresses 0 to 222 of the bank B. Data 216 and ID2 are assigned to the column address 223 of bank B.

Further, the column addresses 224 to
251 and the column address 224 to 251 of the bank B
Is written with an error flag as a result of error correction using an outer code. This error flag is assigned to 1 bit for 1 data, so 1 word is 16
An error flag for data can be stored. Therefore, the error flags for the data 0 to 111 are stored in the column addresses 224 to 251 of the bank A, and the data 1 is stored in the column addresses 224 to 251 of the bank B.
Error flags for 12 to 216 are stored.

SDRA shown in FIGS. 9 and 10 described above.
The row address and column address of M30 are assigned to the SD after data has been error-corrected by the inner code.
It does not change until the data is read from the SDRAM 30 after being written in the RAM 30 and subjected to error correction by an outer code described later.

FIG. 11 schematically shows an address space in the SDRAM 30 composed of these row addresses and column addresses. Each of the bank A and the bank B used by switching is provided with 11 bits of row address. For each of the 11-bit row addresses, a column address composed of 252 words is arranged with 16 bits as one word. Therefore, in this example, the data capacity of the SDRAM 30 is 16
(Bits) × 252 × 2048 × 2 = 16 Mbits.

The EF and the like in the one-packet data format shown in FIG.
It is written to a predetermined area of 30 or another memory.

Next, the error processing control performed by the above configuration will be described. In this example, the control differs depending on whether or not the reproduction data supplied to the memory controller 29 is obtained by reproduction at the normal speed. That is, in the case of high speed reproduction, the magnetic head traces over a plurality of tracks formed on the magnetic tape. As described above, one error correction block of video data is formed by video data of one track. Therefore, at the time of this high speed reproduction, error correction by the inner code is performed, but error correction by the outer code is not performed. Therefore, during this high-speed reproduction, the error correction by the outer code is canceled.

Further, in the error correction by the inner code in the inner code decoder 23, the control differs depending on whether or not all the errors are corrected. That is, if all the errors are corrected by the error correction using the inner code,
The need for error correction with outer codes is eliminated. for that reason,
Even in this case, the error correction by the outer code is canceled.

Whether or not the supplied reproduction data is reproduction at normal speed can be known by sending a control signal from the outside to the error correction decoder 9 via the interface 26, for example. Also, data indicating the reproduction speed may be added to the reproduction data.

FIG. 12 schematically shows an example of this error processing control. In step S50, the inner code decoder 23
In, error correction by the inner code is performed on the video data. A flag corresponding to the result of this error correction is put in the inner code error flag of bit 7 in EF shown in FIG. 7 described above. Then, Sel EF is set to a value ('1' in this example) indicating that the inner code error flag is valid. The error-corrected video data, inner code error flag, and Sel EF are sent to the writing process to the SDRAM 30 in step S51.

If the error-corrected video data is obtained by reproduction at the normal speed, then in step S51, the video data, the inner code error flag,
And Sel EF are written to the SDRAM 30.
When the video data for one error correction block is accumulated in the SDRAM 30, it is determined whether or not all the inner code error flags for this one error correction block are error free. If there is no error, error correction by the video outer code decoder 31 is unnecessary, so the video data, inner code error flag, and Sel
The EF is not sent to the error correction process using the outer code in step S52.

In such a case where the reproduced data is output from the memory controller 29 as it is to the outside of the error correction decoder 9 without the error correction being performed in the video outer code decoder 31, the reproduction code of the video outer code decoder 31 is used. The movement is stopped. This is done, for example, by stopping the clock supplied to this decoder 31. When the error correction decoder 9 is a CMOS IC, by stopping the clock in this way,
The circuit can be made to consume no power.

On the other hand, when this video data is obtained by high speed reproduction, error correction by the outer code is not performed as described above. Therefore, the video data, inner code error flag, and Sel EF are not sent to the error correction process using the outer code in step S52. At the same time, the operation of the outer video code decoder 31 is stopped by stopping the supply of the clock.

On the other hand, if it is determined that there is even one error, the video data, the inner code error flag, and the S
el EF is sent to the process of step S52, and error correction is performed using the outer code. Then, Sel EF is set to a value ('0' in this example) indicating that the outer code error flag is valid. Error-corrected video data,
Outer code error flag, and Sel EF is step S
51 is sent to the writing process to the SDRAM 30.

The output of the data written in the SDRAM 30 is performed in step S53. The data obtained by the reproduction at the normal speed is read from the SDRAM 30 in the row direction and output. The data obtained by the high speed reproduction is output from the memory controller 29 as it is. At this time, an error flag is also output, but this is due to the Sel EF written in the SDRAM 30.
Is performed based on the value of That is, Sel EF =
If it is "1", the inner code error flag is output and Sel
If EF = '0', the outer code error flag is output. In the subsequent conceal circuit, this Sel EF
Based on the value of, the data is concealed by the inner code error flag or the outer code error flag.

As described above, according to the present invention, by providing the 1-bit flag Sel EF, the error correction processing by the outer code can be easily skipped.

Next, SD by the memory controller 29
The control of the RAM 30 will be described. 13, 14,
FIG. 15 is a time chart showing an example of control of the SDRAM 30. FIG. 13 shows SDR during normal speed reproduction.
The access control to AM30 is shown. In the figure, segments 0 to 5 indicate areas in the SDRAM 30 provided for each segment, and audios 0 to 3 indicate areas in the SDRAM 30 provided for one error correction block of each audio data. Indicates.

Video data of segments 0 to 5 is supplied and written in the video data write cycle after error correction by the inner code to the SDRAM 30 of FIG. 13A. Then, these written data are read and written by the video outer code decoder 31 for error correction processing by the outer code. After that, the reading for outputting the video data is performed based on the reading cycle of the video data in FIG. 13B. As shown in FIG. 13D, writing and reading of these video data with respect to the SDRAM 30 are performed for each segment. Also, the audio data is
As shown in FIG. 13C, one field is a write and read cycle. Then, as shown in FIG. 13E, writing and reading of data with respect to the SDRAM 30 are performed for each channel.

As described above, during reproduction at normal speed, video data writing after error correction by the inner code, reading and writing for error correction processing by the outer code, reading for outputting video data, and audio data A plurality of processes of writing and reading are performed in parallel. This is because the clock rate inside the error correction decoder 9 is converted to a sufficiently high value of 46.4 MHz by the rate converter 22 as described above, so that these processes can be performed in a time division manner. It is realized by being done.

Of these processes, the timing of video data writing after error correction by the inner code is defined by the outside, but the other processes are controlled by the memory controller 29.

FIG. 14 shows access control to the SDRAM 30 during high speed reproduction. Timing of writing video data after error correction by inner code and SDRAM
The timing of reading the video data from 30 is the same as in the case of the reproduction at the normal speed described above. In the case of this high-speed reproduction, since there is no error correction by the outer code and the output of the audio data, the control is simple as shown in FIG. 14C. Also, during this high-speed playback, the tape speed is different from that during normal speed playback.
The relative speed between the data recorded on the tape and the magnetic head 5 changes. Therefore, the cycle of the data writing process after the error correction by the inner code shown in FIG.
It differs from the period shown in 3A.

FIG. 15 shows an example of a time division process of writing and reading data in the SDRAM 30. If 30 frames / second, 1 frame is 4
The 6.4 MHz clock corresponds to 1,546,872 clocks. The time division processing of the above-described plurality of processings is performed on this clock in units of 1008 clocks.

Time division processing is performed by pre-allocating clocks necessary for each processing to the 1008 clock. For example, as shown in FIG. 15B, 154 clocks are allocated to the video data output after the error correction processing by the inner code and the outer code. Sixteen clocks are allocated to audio data reading for error correction by the outer audio code decoder 32. 256 clocks are allocated to writing and reading of video data for error correction by the outer video code decoder 31. Further, 582 clocks are allocated to writing of A / V data to the SDRAM 30 after error correction by the inner code.

For such clock allocation, first, the video data output after the error correction processing by the inner code and the outer code and the audio data read by the audio outer code decoder 32 for the error correction are respectively 154 clocks and 16 clocks. Will be done in time. Then, in the following 256 clocks, video data for error correction is written and read by the outer video code decoder 31, and finally, A / V data is written to the SDRAM 30 after error correction by the inner code. The written data is read out in the next cycle, and the same processing is performed.

[0087]

As described above, according to the present invention, which of the inner code error flag and the outer code error flag is to be output is designated by the 1-byte flag Sel EF. Therefore, it is not necessary to provide a dedicated circuit for skipping the processing of the outer code decoder for high-speed reproduction that does not require error correction by the outer code, for example. Therefore, even when the error correction by the outer code is skipped, it is possible to use the same error flag output circuit as in the normal reproduction.

Similarly, even when there is no error as a result of error correction by the inner code, the error correction process by the outer code can be skipped by using the normal error flag output circuit. . Therefore, there is an effect that power saving can be easily realized.

Further, error information can be transmitted by a 1-byte flag called Sel EF, and since it is not necessary to attach an error flag to all symbols, the data width can be internally handled as 8 bits and can be output. Therefore, it is possible to use a versatile RAM such that the data bus width of the RAM is an integral multiple of 8 bits. In addition, this has the effect of reducing costs.

[Brief description of drawings]

FIG. 1 is a block diagram showing an example of a configuration of a digital video recording / reproducing apparatus to which an error correcting apparatus according to an embodiment of the present invention is applied.

FIG. 2 is a schematic diagram showing an example of the configuration of an error correction block in video data.

FIG. 3 is a schematic diagram showing an example of a configuration of an error correction block in audio data.

FIG. 4 is a schematic diagram schematically showing an example of the configuration of one sync block in an error correction block in video data.

FIG. 5 is a schematic diagram showing an example of a configuration of an error correction decoder.

FIG. 6 is a schematic diagram showing an example of a data structure in one packet.

FIG. 7 is a schematic diagram showing a bit configuration of EF.

FIG. 8 is a schematic diagram showing an example of a format when one sync block worth of reproduction data is written to the SDRAM.

FIG. 9 is a schematic diagram showing row address allocation in an SDRAM.

FIG. 10 is a schematic diagram showing column address assignment in an SDRAM.

FIG. 11 is a schematic diagram schematically showing an address space in an SDRAM.

FIG. 12 is a schematic diagram schematically showing processing of data and error flags.

FIG. 13 is a time chart showing access control for SDRAM.

FIG. 14 is a time chart showing access control for SDRAM.

FIG. 15 is a time chart showing access control to SDRAM.

FIG. 16 is a block diagram showing an example of the configuration of a digital recording / reproducing apparatus according to the related art, which uses encoding by product code.

[Explanation of symbols]

9 ... Error correction decoder, 22 ... Rate converter, 23 ... Inner code decoder, 29 ... Memory controller, 30 ... SDRAM, 31 ... Video outer code decoder, 32 ... Audio Outer code decoder

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code Agency reference number FI Technical display location H04N 5/92 H04N 5/92 H

Claims (2)

[Claims] 1. An error correction device for decoding data that has been error correction coded by a product code, wherein an inner code decoder for error correction by an inner code and an error correction by the inner code decoder are performed. An outer code decoder for performing error correction by an outer code later, and an internal data format, as a result of the error correction by the inner code, an area for storing an inner code error flag indicating whether or not an error exists, Indicates which of the inner code error flag obtained by the error correction by the inner code and the outer code error flag obtained by the error correction by the outer code is effective. An error correction device having an area for storing an error flag selection flag. 2. The error correction device according to claim 1, wherein the operation of the outer code decoder is stopped when the error correction by the outer code is not necessary.