JP3744134B2 - Error correction apparatus and method, and digital signal reproduction apparatus and method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an error correction apparatus and method for decoding digital data that has been error correction encoded using a product code using a single external RAM, and a digital signal reproducing apparatus and Regarding the method.
[0002]
[Prior art]
At present, in an apparatus for digitally recording / reproducing an A / V (audio / video) signal on a recording medium such as a magnetic tape such as a DVCR (digital video cassette recorder), a product code is used for error correction. Encoding is often used.
[0003]
In this product code encoding, data arranged in a matrix in units of one symbol (for example, 1 byte) is encoded by, for example, Reed-Solomon code in the column direction, and the outer code parity is set. Generated. Then, the data and outer code parity are encoded in the row direction to generate an inner code parity. As described above, the outer code parity is generated in the column direction and the inner code parity is generated in the row direction, whereby error correction coding using a product code is performed. At this time, the time-series order of the data matches, for example, the row direction.
[0004]
FIG. 19 shows an example of the configuration of a conventional digital recording / reproducing apparatus using this product code encoding. For example, digital video data is supplied as recording data to a BRR (Bit Rate Reduction) encoder 101 via the interface 100. In the BRR encoder 101, data compression is performed on the supplied recording data. The compressed recording data is supplied to an error correction encoder 102 that performs error correction coding using the product code described above.
[0005]
The error correction encoder 102 is connected to a RAM (not shown), and the supplied recording data is written into the RAM. Then, as described above, the outer code parity and the inner code parity are generated for the recording data supplied and written in the RAM memory, and product code error correction coding is performed. The encoded recording data is read from the RAM in accordance with the row direction described above, supplied to the recording drive unit 103 including an amplifier for recording, and recorded on the magnetic tape 105 by the magnetic head 104.
[0006]
The recording at this time is performed by a helical scan system in which, for example, a magnetic head 104 is provided on a rotating drum and a track is formed obliquely with respect to the magnetic tape 105 by the magnetic head 104.
[0007]
Data recorded on the magnetic tape 105 is read by the magnetic head 106 to be reproduced data. This reproduced data is supplied to the inner code decoder 108 via the equalizer 107, and error correction by the inner code (hereinafter referred to as “inner code correction”. Similarly, error correction by the outer code is referred to as “outer code correction”. Is performed). That is, error correction is performed for each row based on the inner code parity arranged for each row of data. Then, as an error correction result, an error flag is attached to the symbol in each row. For example, if the number of errors exceeds the error correction capability of the code and the error remains uncorrected, an error flag is attached to all symbols in the row to indicate that an error exists. Is done.
[0008]
The reproduced data that has been subjected to the inner code error correction is written into the RAM 109. The inner code decoder 108 can perform address control on the RAM 109, and reproduction data written to the RAM 109 is address-controlled by the inner code decoder 108 and arranged in an address space in the RAM 109.
[0009]
In this way, when the inner code correction is performed in the inner code decoder 108, the error-corrected reproduction data is read from the RAM 109. At this time, the reproduction data is read out in the column direction of the product code of the RAM 109 by address control by the decoder 108. Therefore, in the RAM 109, the order of data is read in the direction of the outer code.
[0010]
The reproduction data read in the outer code direction in this way is supplied to the outer code decoder 110, and the outer code decoder 110 corrects the outer code. In other words, error correction is performed for each column based on the outer code parity arranged for each column of data. In this outer code correction, an error flag attached to each symbol at the time of decoding in the inner code decoder 108 is used together with the outer code.
[0011]
The reproduced data that has been error-corrected by the outer code decoder 110 is written into the RAM 111. The outer code decoder 110 can perform address control on the RAM 111, and reproduction data written to the RAM 111 is address-controlled by the outer code decoder 110 and arranged in an address space in the RAM 109.
[0012]
An error flag is added to each symbol as an error correction result. This is added, for example, to indicate that an error exists when the number of errors exceeds the error correction capability of the code and no error correction is performed.
[0013]
When outer code correction is performed in the outer code decoder 110, the error-corrected reproduction data is read from the RAM 111. At this time, the reproduction data is read in the row direction in the address space of the RAM 111 by the address control by the decoder 110. Therefore, in the RAM 111, the reading direction read at the time of reading from the RAM 109 is read again, and the first reading direction, that is, the original data order is returned.
[0014]
The reproduction data that has been subjected to the inner code and outer code correction in this way is supplied to the BRR decoder 112. In this BRR decoder 112, the data compression applied to the data at the time of recording is released. The reproduction data that has been decompressed is output to the outside as digital video data via the interface 113.
[0015]
In addition, regarding the data to which the outer code decoder 110 cannot complete the error correction and the error flag is added, the error correction is performed using a technique such as interpolation thereafter.
[0016]
In the digital recording / reproducing apparatus as described above, the recording-side BRR encoder 101 and the error correction encoder 102 are each configured by one integrated circuit. On the reproduction side, the inner code decoder 108, the outer code decoder 110, and the BRR decoder 112 are each constituted by one integrated circuit.
[0017]
[Problems to be solved by the invention]
As described above, the digital data encoded by the product code is first subjected to inner code correction, and is decoded by performing outer code correction based on the result, and is also decoded by the inner code and outer code. In each error correction, the data is replaced. For this reason, as described above, the RAM 109 for performing reading in the column direction of the product code and the RAM 111 for performing reading in the row direction are required.
[0018]
Each of the inner code decoder 108 and the outer code decoder 110 has only a relatively small function. In the ICs constituting the decoders 108 and 110, the system clock having the same rate as the video data read rate is used as the internal clock. Therefore, the control of the RAMs 109 and 111 is easy.
[0019]
However, since these RAMs 109 and 111 must be connected to the inner code decoder 108 and the outer code decoder 110, respectively, the number of pins increases in the integrated circuits of the inner code decoder 108 and the outer code decoder 110, respectively. As a result, there is a problem that power consumption increases. Further, since two independent external RAMs are required like the RAMs 109 and 111, there is a problem in that it is disadvantageous in terms of cost.
[0020]
Therefore, the object of the present invention is to have problems such as wasteful power consumption, increase in the number of pins, and cost increase due to the fact that two RAMs are used to read the product code in the column direction and the row direction. An object of the present invention is to provide an error correction apparatus and method therefor, and a digital signal reproduction apparatus and method therefor.
[0021]
[Means for Solving the Problems]
  In order to solve the above-described problems, an error correction apparatus for decoding error correction encoded data using a product code includes an inner code decoder for performing inner code correction and inner code correction. And an outer code decoder for correcting the outer code and a memory for storing the error-corrected data by the inner-code decoder and the error-corrected data by the outer code. It is divided into slots defined by the clock, one sequence is constituted by a plurality of slots of the same type, and one sequence is repeated a predetermined number of times in the period of one frame or one field to perform error correction processing.If there is no need for outer code correction, the slot for performing data reading and writing processing for outer code correction of video data to the memory is diverted as the slot for performing data writing processing after inner code correction for the memory. I didAn error correction apparatus characterized by the above.
[0022]
  Further, in order to solve the above-described problem, the present invention provides an inner code for performing inner code correction in a digital signal reproducing apparatus using an error correction device for decoding data error-encoded using a product code. A decoder, an outer code decoder that performs outer code correction after inner code correction is performed, and a memory that stores data subjected to error correction by the inner code decoder and data subjected to error correction by the outer code The same type of processing is divided into slots defined by the reference clock, and a sequence is formed by a plurality of slots of the same type of processing, and one sequence is repeated a predetermined number of times in the period of one frame or one field. Error correction processingIf there is no need for outer code correction, the slot for performing data reading and writing processing for outer code correction of video data to the memory is diverted as the slot for performing data writing processing after inner code correction for the memory. I didA digital signal reproduction apparatus comprising an error correction apparatus.
[0023]
  Further, in order to solve the above-described problem, the present invention provides an inner code decoding step for performing inner code correction, an inner code in an error correction method for decoding data error-corrected coded using a product code, An outer code decoding step for correcting the outer code after the correction is performed, and an inner code decodingStepData for which error correction was performed byStoring in a memory;Outer codeDecoding stepsData for which error correction was performed byThememoryStep to store andThe same type of processing is divided into slots defined by the reference clock, and one sequence is constituted by a plurality of slots of the same type of processing, and one sequence is repeated a predetermined number of times in the period of one frame or one field. Error correction processingIf there is no need for outer code correction, the slot for performing data reading and writing processing for outer code correction of video data to the memory is diverted as the slot for performing data writing processing after inner code correction for the memory. I didAn error correction method characterized by the above.
[0024]
  In order to solve the above-described problem, the present invention provides an inner code for performing inner code correction in a digital signal reproduction method using an error correction method for decoding data error-corrected and encoded using a product code. A decoding step, an outer code decoding step in which outer code correction is performed after inner code correction is performed, and inner code decoding.StepData for which error correction was performed byStoring in a memory;Outer codeDecoding stepsData for which error correction was performed byThememoryStep to store and
The same type of processing is divided into slots defined by the reference clock, and one sequence is constituted by a plurality of slots of the same type of processing, and one sequence is repeated a predetermined number of times in the period of one frame or one field. Error correction processingIf there is no need for outer code correction, the slot for performing data reading and writing processing for outer code correction of video data to the memory is diverted as the slot for performing data writing processing after inner code correction for the memory. Using the error correction methodThis is a digital signal reproduction method characterized by the above.
[0025]
As described above, in the present invention, a predetermined unit of the same type of processing is a slot, a plurality of types of slots are collected to form a sequence, and the sequence is repeated within one frame or one field. In addition to facilitating time-sharing processing, design and verification can be performed for each type of processing.
[0026]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 schematically shows an example of the configuration of a digital video recording / reproducing apparatus to which the present invention is applied. In this configuration, an inner code decoder that performs inner code correction that decodes data encoded by a product code and an outer code decoder that performs outer code correction are configured in an integrated circuit, and data at the time of decoding The RAM for replacement is shared. In this invention, at this time, various processes are grouped in a predetermined unit to form a slot, and various slots are collected to form a sequence, and the sequence is repeated within one frame. Access to the RAM is performed by time division processing based on the slot.
[0027]
In FIG. 1, recording data including, for example, video data and 4-channel audio data is supplied to the BRR encoder 2 via the interface 1. In the BRR encoder 2, data compression is performed on the supplied recording data. This compression is performed by, for example, blocking the data supplied to the BRR encoder 2, performing DCT conversion, quantization, and variable length coding. The recording data compressed in this manner is supplied to the error correction encoder 3.
[0028]
The error correction encoder 3 is connected to a RAM (not shown), and the supplied recording data is written to the RAM. Then, as described in the above-described prior art, outer code parity and inner code parity are generated for the recording data supplied and written in the RAM memory, and error correction coding of the product code is performed. The size of data that completes the product code of the inner code and the outer code is referred to as an error correction block.
[0029]
The encoded data from the error correction encoder is read from the RAM in accordance with the row direction described above, supplied to the recording drive unit 4 including an amplifier for recording, and recorded on the magnetic tape 6 by the magnetic head 5. This recording is performed by a helical scan method in which tracks are formed obliquely with respect to the magnetic tape 6 by the magnetic head 5 provided on the rotating drum, and a pair of magnetic heads having different angles from each other. Therefore, the azimuth method is used in which the azimuth is recorded differently in adjacent tracks.
[0030]
As an example of this recording method, when four magnetic heads 5 are provided on a rotating drum and the channels corresponding to the heads are A, B, C, D, these four magnetic heads 4 perform A, B , C, D in this order. Of these, A and C, B and D are tracks in which azimuth coincides. At this time, a segment is composed of two adjacent tracks (A and B channels and C and D channels) having different azimuths as a set. Further, the audio data having four channels is arranged, for example, in the center with respect to the track so as to be sandwiched between the video data.
[0031]
The data recorded on the magnetic tape 6 is read out by the magnetic head 7 in accordance with the order in which the recording data is recorded as described above to be reproduced data. The read reproduction data is converted into serial data via the equalizer 8 and supplied to the inner code / outer code decoder 9. The inner code / outer code decoder 9 includes an inner code decoder and an outer code decoder configured as one integrated circuit, and can perform address control on the connected RAM 10.
[0032]
The reproduction data supplied to the inner code / outer code decoder 9 is subjected to inner code correction, address-controlled, and written to the RAM 10. Thus, when data for one error correction block is accumulated in the RAM 10, the data is read in the outer code direction and supplied to the inner code / outer code decoder 9 in order to perform outer code correction. The supplied data is subjected to outer code correction and written again in the RAM 10. When error correction for one error correction block is completed in this way, data is read from the RAM 10 in the inner code direction (original data order) under the control of the inner code / outer code decoder 9 and output. At this time, if an error exists beyond the error correction capability of the code, an error flag is attached to the data at a predetermined position and output.
[0033]
When data is input / output at the time of correcting the inner code and outer code in the RAM 10, there is a difference in processing units between the video data and the audio data in the A / V data, and the outer code correction is performed in one RAM. For this reason, the data for the output after error correction is replaced, so the timing of writing and reading the data to the RAM 10 is mixed. For this reason, control of the timing of writing and reading of data with respect to the RAM 10 is performed in a time division manner by the control of the inner code / outer code decoder 9. Details of this control will be described later.
[0034]
The reproduction data output from the inner code / outer code decoder 9 is supplied to the BRR decoder 11. In this BRR decoder 11, the data compression applied to the data at the time of recording is released. For example, the data supplied to the BRR decoder 11 is subjected to variable length decoding, inverse quantization, inverse DCT transform, and inverse block transform, and the compression is released. The reproduction data thus decompressed is output to the outside as digital video data via the interface 12.
[0035]
Note that the error correction is performed on the data to which the error flag is attached without being completely corrected by the inner code / outer code decoder 9, for example, using a technique such as interpolation.
[0036]
2 and 3 schematically show an example of the configuration of the error correction block described above. In this example, one frame of data is composed of 12 tracks formed on a magnetic tape. Further, as described above, a segment is composed of two adjacent tracks having different azimuths as a set, and one frame includes 12 tracks = 6 segments. These segments are numbered from 0 to 5.
[0037]
In the example of the video data shown in FIG. 2, one track in these 12 frames forms one error correction block shown in FIG. 2B as shown in FIG. 2A. For example, for video data composed of a data array of 217 bytes × 226 bytes, the data of each column is encoded in the direction of arrow b by, for example, (250, 226) Reed-Solomon code to generate a 24-byte outer code parity. Is done. Further, with respect to these video data and outer code parity, the data in each row is encoded by, for example, (229, 217) Reed-Solomon code in the direction of arrow a, and a 12-byte inner code parity is generated. In addition, sync data and ID each having a size of 2 bytes are arranged at the head of each data row.
[0038]
FIG. 3 shows an example of the configuration of an error correction block in audio data. As shown in FIG. 3A, the audio data forms one error correction block with six tracks out of twelve tracks for one frame. For example, audio data having a data array of 217 bytes × 12 bytes is encoded in the direction of arrow b by, for example, (24, 12) Reed-Solomon code, and a 12-byte outer code parity is generated. Further, these video data and outer code parity are encoded in the direction of arrow a by, for example, (229, 217) Reed-Solomon code, and a 12-byte inner code parity is generated. In addition, sync data and ID are arranged at the head of each data row.
[0039]
FIG. 4 schematically shows the configuration of one sync block in these error correction blocks, taking video data as an example. The first two bytes are sync data. The subsequent 2 bytes are an ID, which describes the number (segment number), sync block number, etc. in one track of this one sync block. This ID is followed by 217 bytes of video data (or outer code parity) and inner code parity. The recording data on the magnetic tape is a series of sync blocks.
[0040]
Next, a more detailed configuration of the inner code / outer code decoder 9 will be described with reference to FIG. In FIG. 5, reference numeral 60 denotes an IC circuit portion of the inner code / outer code decoder 9. The ECC decoder IC 60 basically has an inner code error correction function, an outer code error correction function, an audio signal processing function, an error count function, and an auxiliary data reading function. Actually, two ECC decoder ICs 60 are used as one set, and one ECC decoder IC 60 is supplied with one azimuth data of the reproduction data.
[0041]
Serial data reproduced at a recording rate of 94 Mbps and a clock generated therefrom are input in parallel to the ECC decoder IC 60, input to the S / P converter 61, and converted from serial to parallel data. The width data and the clock divided by 1/8.
[0042]
At this stage, the high-speed 1-bit data is simply reduced to the 8-bit width of 11 Mbps rate, so the breaks in byte units and sync block units are appropriate. The function converts them into regular data strings. The byte break is defined by the bit assignment of the output terminal of the synchronization detection circuit 62, and the sync block break is defined by the strobe pulse STB added by the synchronization detection circuit 62. Next, the system is switched to the system clock 46 MHz by the rate converter 63.
[0043]
The ECC decoder IC 60 has two inputs, a main system and a sub system, in order to support an 8-head system. The above is a circuit for the input through the main system, but the same configuration is provided for the input of the sub system. In order to process the reproduction data of the sub system, an S / P converter 65, a synchronization detection circuit 66, and a rate converter 67 are provided as in the main system. Data packets output from these circuits are mixed into one system by the OR circuit of the mixer 68. A signal that originally came at a rate of 11 Mbps is converted to a rate of 46 Mbps. Therefore, there is a gap between the packets, so that it is possible to mix the sub system data and the main system data. However, if the mixing process is performed randomly, the data of both systems collide, so that the two rate converters 63 and 67 are busy each other with reference to busy and keep the output during the other party's output. Yes. At the same time, a 1-bit flag of sub / main is embedded in the packet so that the origin of the packet can be determined.
[0044]
The rate converters 63 and 67 each have a small RAM as a buffer in order to perform this stepping and to absorb, for example, jitter of the traveling speed of the magnetic tape 6 and the rotational speed of the rotating drum included in the reproduction RF signal. Have The output of this buffer is controlled by an inner code decoder 69 connected to the subsequent stage.
[0045]
The input switching pulse SWP is delayed by the timing generator 64 by the delay time of the internal circuit, and information indicating the tape running direction is similarly delayed and embedded in the packet by the rate converters 63 and 67. It is. The rate converters 63 and 67 have a counter that is initialized at the head switching timing and is counted by the strobe pulse STB. By this counter, whether or not it is a data non-recording section (hereinafter referred to as a gap) in terms of format. And the information is also included in the packet.
[0046]
The packet output from the mixer 68 is subjected to inner code correction by the inner code decoder 69. In the data from the inner code decoder 69, for example, error correction information indicating whether correction is impossible or not and how many bytes have been corrected are also embedded in the packet and input to the ID reproduction circuit 71. If the inner code decoder 69 cannot correct the inner code, the ID cannot be trusted. However, in the memory controller 74 to be described later, the ID and the order of the outer code correction are determined with reference to the ID, so the ID needs to be reproduced. The function of the ID reproduction circuit 71 reproduces the ID of an uncorrectable packet in anticipation from the IDs of uncorrectable packets before and after. The ID reproduction circuit 71 has RAMs capable of storing three packets in each of the main system and the sub system in order to refer to packets that come later. The RAM is used to perform conversion to a 16-bit width and arbitration with the video outer code decoder 76.
[0047]
The error correction information obtained from the inner code decoder 69 is input to an error monitor (not shown). In the error monitor, error correction information and other information are encoded together, aggregated into main and sub signals, and output to the outside of the ECC decoder IC60. An error correction state can be observed by D / A converting this output.
[0048]
The data output from the ID reproduction circuit 71 is descrambled by a descrambler 72. The main line data output from the descrambler 72 is stored in an SDRAM (Synchronous Dynamic Random Access Memory) 75 external to the IC via the memory controller 74.
[0049]
At this time, the memory controller 74 performs timing control of data coming from the descrambler 72 and address control for separately writing video data and audio data for each segment to the SDRAM 75.
[0050]
When the main system video data has accumulated one error correction code block (for one track), in order to perform the outer code correction processing by the video outer code decoder 76, the SDRAM 75 is subjected to read control, and the data is transmitted in the outer code direction. Read and send data to the video outer code decoder 76. The memory controller 74 performs writing for returning to the SDRAM 75 again from the data whose outer code processing is completed.
[0051]
The memory controller 74 selects the main / sub data for the data for which the decoding process of the outer code for one track has been completed, reads the data in the inner code direction, and transmits the data to the compression decoder via an ID renumbering circuit (not shown). The ID is changed for the interface and output from the terminal 77.
[0052]
On the other hand, when one field (one error correction coding unit of audio data) is accumulated in the SDRAM 75, the audio data is supplied to the audio processing circuit 78. The audio processing circuit 78 performs predetermined processing such as audio outer code correction, deshuffling, and error interpolation, and is then converted into serial data and output from a terminal 79.
[0053]
As described above, the error correction block of audio data is completed in one field for six tracks. For this reason, an error correction block of audio data is formed over the normal / reverse azimuth tracks. The ECC decoder IC 60 corresponds to one azimuth. Therefore, in order to perform outer code correction of audio data, it is necessary to send the audio data for which inner code correction has been completed to the ECC decoder IC 60 '(not shown) corresponding to the other azimuth. The audio data for which the inner code correction has been completed is sent to another ECC decoder IC 60 via the terminal 82.
[0054]
This terminal 82 can exchange data in both directions, and the audio data sent from another ECC decoder IC 60 can be input to the terminal 82 by setting the mode in a predetermined method. it can.
[0055]
In addition to the above description, an interface 80 with a system control microcomputer (hereinafter referred to as a syscon) is provided so that various settings can be made and error information can be read by the syscon. Further, although not shown, a circuit for extracting video auxiliary data other than video data and a circuit for extracting audio auxiliary data other than audio data are provided, and the extracted auxiliary data is sent to the syscon via the interface 80. . Furthermore, an error counter 73 for counting the number of errors is also provided.
[0056]
Data exchange with the syscon uses a bus 81 having a predetermined bit width in the order of the interface 80, the timing generation circuit 64, the error counter 73, the memory controller 74, the outer code decoder 76, the audio processing circuit 78, and the interface 80. Data is streamed. In each part, necessary data is taken out from the bus 81. In each unit, data to be read by the interface 80 is sent to the bus 81.
[0057]
In the ECC decoder IC 60, one sync block is handled as one packet. FIG. 6 shows an example of the data structure in one packet. Here, the data is handled with 8 bits as one symbol. ID0 and ID1 indicate the ID in the data configuration of one sync block shown in FIG. 4 in more detail. That is, ID0 represents a sync block number, and ID1 represents a segment number, video / audio identification information, and the like. Data0 to Data216 are video data or audio data. The data after ID2 is auxiliary data.
[0058]
FIG. 7 shows an example of a format when reproduction data for one sync block is written to the SDRAM 75. Since this SDRAM 75 has a 16-bit data width, the 8-bit width data format shown in FIG. 6 is made such that 16 bits are 1 word and the number of words is halved to 112 words. The
[0059]
When the reproduction data is written into the SDRAM 75, the data timing is controlled under the control of the memory controller 74. The reproduction data is divided into segments and written into video data and audio data for each segment in the SDRAM 75. Address control at this time is also performed by the memory controller 74.
[0060]
8 and 9 show an example of address assignment in the SDRAM 75 by this address control. FIG. 8 shows row (column) address assignment. In bits 8 to 10, the video data is divided into segments 0 to 5, and the audio data is fixed to '6'. In this way, the video data and audio data are prevented from colliding in address allocation with these bits 8 to 10. In the video data, bits 6 and 7 indicate the running direction of the tape, and are “0” for normal running and “1” for reverse running. Further, bits 0 to 5 contain 6 bits B7 to B2 when the sync block number is represented by 8 bits B7 to B0.
[0061]
In audio data, bits 6 and 7 are fixed to “0”. Further, these fields 0 to 3 are entered for bits 4 and 5. Bits 2 and 3 are assigned to four audio channels. In bits 0 and 1, 2 or 3 bits (B2, B3) of the sync block number are entered.
[0062]
FIG. 9 shows the assignment of column (row) addresses. This column address assignment is common to audio data and video data. The SDRAM 75 has a two-bank configuration including a bank A and a bank B, and data is assigned to the bank A and the bank B. In the column, the sync block number bits 0 and 1 (B0, B1) are assigned so that data of four sync blocks of 0, 1, 2, and 3 are mixed. S 0, S 1, S 2, and S 3 shown in the figure represent data of sync blocks whose bits 0 and 1 (B 0, B 1) of these sync block numbers are 0, 1, 2, and 3, respectively.
[0063]
By combining the sync block allocation by bits 0 and 1 in the column address and the sync block number allocation in the row address described above, address allocation can be performed for all sync blocks.
[0064]
ID0 and ID1 shown in FIG. 6 are assigned to column addresses 0 to 3 of bank A. Further, data 0 to 109 are assigned to the column addresses 4 to 223. On the other hand, data 110 to 215 are allocated to the column addresses 0 to 219 of the bank B. Data 216 and ID2 are assigned to column addresses 220 to 223 of bank B.
[0065]
In addition, an error flag as a result of the outer code correction is written in the column addresses 224 to 251 of the bank A and the column addresses 224 to 251 of the bank B. Since one bit is assigned to this error flag for one data, an error flag for 16 data can be stored in one word. Therefore, an error flag for data 0 to 111 is stored in column addresses 224 to 251 of bank A, and an error flag for data 112 to 216 is stored in column addresses 224 to 251 of bank B.
[0066]
The row address and column address assignment of the SDRAM 75 shown in FIG. 8 and FIG. 9 described above is such that the data is written to the SDRAM 75 after the inner code correction is completed, and the outer code correction described later is performed and the data is transferred from the SDRAM 75. It does not change until it is read out.
[0067]
Next, control of the SDRAM 75 by the memory controller 74 will be described. FIG. 10 is a time chart showing an example of access to the SDRAM 75 during normal speed reproduction. In the figure, segments 0 to 5 indicate areas in the SDRAM 75 provided for the respective segments, and audios 0 to 3 indicate areas in the SDRAM 75 provided for one error correction block of each audio data. Indicates.
[0068]
In the SDRAM 75 of FIG. 10A, the video data of the segments 0 to 5 is supplied and written with respect to the video data writing cycle after the inner code correction. Then, reading and writing for the outer code correction processing in the video outer code decoder 31 are performed on the written data. Thereafter, readout for outputting video data is performed based on the readout cycle of video data in FIG. 10B. As shown in FIG. 10D, the video data is written to and read from the SDRAM 75 for each segment. Further, as shown in FIG. 10C, the audio data has one field as a writing and reading cycle. Then, as shown in FIG. 10E, data is written to and read from the SDRAM 75 for each channel.
[0069]
Thus, in normal speed playback, (1) video data writing after inner code correction, (2) reading and writing for outer code correction processing, (3) reading for video data output, and (4) Multiple types of processing of writing and reading audio data are performed in parallel. As described above, this is because the internal clock rate of the error correction decoder 9 is converted to a sufficiently high value of 46.4 MHz by the rate converter 63 (or 67). This is realized by being able to be performed by division.
[0070]
Of these processes, the timing of video data writing after inner code correction and reading for video data output depend on the outside. Other processes are controlled by the memory controller 74.
[0071]
FIG. 11 shows an example of time division processing for writing and reading data in the SDRAM 75. FIG. 11A shows a write cycle of video data and audio data after inner code correction. FIG. 11B shows processing of video data and audio data. In the case of 30 frames / second, one frame corresponds to 1,546,872 clocks with a 46.4 MHz clock. With respect to this clock, the time division processing of the above-described plural types of processing is performed in units of 1008 clocks. 1008 clocks are one sequence of processing.
[0072]
In the present invention, the 1008 clock is divided into clocks necessary for each of the above-described plural types of processing. For example, each of a plurality of types of processing is finely divided into a series of necessary processing units in this processing. This disassembly is performed so that the processing among a plurality of types is substantially equivalent to each other, and is performed with the required maximum number of clocks. This number of clocks is called a slot. The time division process is performed in units of this slot.
[0073]
The number of clocks that can be divided is different for each of the multiple types of processing. Therefore, the slot size varies depending on the type of processing. For example, as shown in FIG. 11C, the video data output after the inner code and outer code correction processing has 154 clocks as one slot. The audio data readout for error correction by the audio outer code decoder 32 is 16 slots per slot. Writing and reading video data for error correction by the video outer code decoder 31 takes 256 slots as one slot. In addition, writing of A / V data to the SDRAM 75 after the inner code correction takes 582 clocks as one slot. Note that how to determine the number of clocks in the slot for each type of processing will be described later.
[0074]
All types of slots are collected to form one sequence. By repeating this sequence, various processes can be performed in a time-sharing manner. In the example of FIG. 11, 154 clocks of video data output after inner code and outer code correction processing are the first, 16 clocks of data reading for audio outer code correction, and 256 clocks of reading and writing for video data outer code correction , And slots are arranged in the order of 582 clocks of data writing after inner code correction, thereby forming one sequence. The slot order is fixed. These total 1008 clocks are taken as one sequence, and this is repeated.
[0075]
Here, the reason why the slot of the video data output process after the inner code and outer code correction processing is set at the head is that the timing is determined by the reference frame pulse given from the outside. The repeated sequence is reset by this reference frame pulse and starts from the beginning of the frame. That is, the sequence is started in synchronization with the reference frame pulse.
[0076]
FIG. 11D shows an example of the number of slots per frame for each process. The video data output after the inner code and outer code correction processing requires 1400 slots / frame. Data reading for audio outer code correction requires 1300 slots / frame. Read / write for video data outer code correction requires 1350 slots / frame. Then, 1534 slots / frame is required for data writing after inner code correction.
[0077]
As described above, one frame is composed of 1,546,872 clocks. That is, when one sequence is 1008 clocks, one frame can include a 1534 sequence. Therefore, 1534 slots / frames are provided for each of a plurality of types of processing, and all processing can be completed.
[0078]
Since various processes are performed by repeating the sequence, the number of slots in which various processes can be used in one frame is equal. Accordingly, in various processes, the number of slots in one frame is slightly different, so that a surplus slot is generated. No processing is performed in the remaining slots.
[0079]
Next, an example of how to determine the number of clocks in one slot will be described using a more specific example. In order to facilitate understanding, FIG. 12 shows in detail an example of the data arrangement in the error correction block of the video data shown in FIG. Data is composed of one symbol of 8 bits as a unit. In FIG. 12, Sx-Dy represents one symbol of data. The same x indicates that the data is in the inner code direction of the same series, and the same y indicates that the data is in the outer code direction of the same series. That is, Sx-D0, Sx-D1, SxD2,..., Sx-D216 are data in the inner code direction of the same series. Similarly, S0-Dy, S1-Dy, S2-Dy,..., S249-Dy are data in the outer code direction of the same series.
[0080]
In the following, “data in the inner code direction of the same sequence” is referred to as “data in the inner code sequence”, and “data in the outer code direction of the same sequence” is referred to as “data in the outer code sequence”.
[0081]
The address assignment in the SDRAM 75 is made in a matrix with column (row) addresses and row (column) addresses. FIG. 13 shows an example of address assignment in the SDRAM 75. That is, FIG. 13 schematically shows an example of the data arrangement of the error correction block shown in FIG. 12 described above with respect to the address space of the SDRAM 75 composed of these column address and row address.
[0082]
As schematically shown in FIG. 13A, the SDRAM 75 has two areas of a bank A and a bank B that are used by switching as memory areas. In each of these banks A and B, a row address consisting of 6 bits represented by bits '0' to '5' is provided. The SDRAM 75 has a data width of 16 bits. A column address consisting of 256 words is arranged for each row address with the 16 bits as one word.
[0083]
The SDRAM 75 can perform so-called burst write / burst read, in which a plurality of column addresses are continuously accessed by one designation, and writing or reading is continuously performed. The number of words that are continuously output or input by writing or reading is called a burst length. The burst length can be set in various manners such as “1”, “2”, “4”, “8”, full page, and the like. In this example, the burst length is set to '4'.
[0084]
In this example, the data of the same inner code sequence is collected in the order of the outer code sequence for each number corresponding to the burst length, and arranged for the same row address. At the same time, the data of the inner code series is divided into a first half and a second half, and these are alternately arranged for banks A and B for each row address. Therefore, when writing / reading data in the inner code direction, the column is randomly accessed. Further, when writing / reading data in the outer code direction, banks A and B are interleaved and accessed in units of burst length.
[0085]
For one row address, the data in the inner code direction is allocated in a group of four sequences for each number corresponding to the burst length. That is, in the row address starting from the address “0”, four series of data of S0-Dy, S1-Dy, S2-Dy, and S3-Dy are assigned to the row address “0”. Four series of data S4-Dy, S5-Dy, S6-Dy, and S7-Dy are assigned to the row address '1'. Similarly, four series of data S8-Dy, S9-Dy, S10-Dy, and S11-Dy are assigned to the row address '2'. In the same manner, data is assigned to each of the four lines up to row address '61'.
[0086]
The inner code data is composed of 250 sync blocks as shown in FIG. 2B, and there are 250 data sequences in the inner code direction from sequence S0 to sequence S249. For this reason, when four sequences of data in the inner code direction are assigned to one row address in this way, the last two sequences (S248-Dy and S249-Dy) remain. Accordingly, S248-Dy and S249-Dy are assigned to the row address '62', and the remaining two series are filled with dummy data.
[0087]
On the other hand, for the column address, the data in the inner code direction is divided into the first half and the second half (that is, the first half Sx-D0 to Sx-D109 and the second half Sx-D110 to Sx-216). These first half and second half are replaced with bank A and bank B and arranged. That is, for the row address “0”, the first half of the data series S0 to S3 in the inner code direction is arranged in the bank A, and the second half is arranged in the bank B. In the next row address “1”, the arrangement of the banks A and B is switched, the second half of the data series S4 to S7 is arranged in the bank A, and the first half is arranged in the bank B.
[0088]
FIG. 13B shows in detail an example of data arrangement for each row address. Here, row addresses “0” to “2” are shown. Since one data item consists of 8 bits in an area indicated by one column address having one word, that is, 16 bits, two symbols are arranged as one set. For convenience, the upper 8 bits of the area indicated by one column address in FIG. 13B are referred to as the upper column, and the lower 8 bits are referred to as the lower column. In the sequence Dy in the outer code direction, data in which y is an odd number is arranged in the upper column, and data in which y is an even number is arranged in the lower column.
[0089]
In the first four column addresses (column addresses “0” to “3”) of the bank in which the first half of the data sequence in the inner code direction is arranged, an ID for identifying data arranged at the same row address is stored. Be placed. Subsequent to this ID, data is stored from the column address “4”.
[0090]
As described above, symbols are arranged in a burst length unit. At this time, the sequences in the outer code direction (Dy) are the same, and the sequences in the inner code direction (Sx) are continuous. In this example, since the burst length is 4, 4 data are collected in each of the upper column and the lower column.
[0091]
In the four column addresses following the ID (column addresses “4” to “7”), the lower column is data in which x is 0 to 3 and y is 0, that is, data S0-D0, S1-D0, S2- D0 and S3-D0 are arranged in order. In the upper column of the column address, data in which x is 0 to 3 and y is 1 as in the lower column, that is, S0-D1, S1-D1, S2-D1, and S3-D1 are sequentially arranged. Similarly, data sequences in the same outer code direction are collected for every four column addresses, and data is arranged in the memory space. Note that dummy data is arranged after the column address '224' in each of the banks A and B.
[0092]
Incidentally, the SDRAM 75 is controlled by commands. For example, a predetermined command input to the SDRAM 75 is made by a combination of signals supplied to a predetermined command input terminal of the SDRAM 75 and an address input terminal having a 12-bit input terminal in parallel. This command is generated and output by the memory controller 74 and supplied to the SDRAM 75.
[0093]
When controlling the SDRAM 75, there are some restrictions based on the asynchronous characteristics of the SDRAM 75 which is the synchronous memory when a command is input. This restriction must be taken into consideration when efficiently controlling writing to and reading from the SDRAM 75. In the following, the control of the SDRAM 75 and restrictions will be outlined.
[0094]
In using the SDRAM 75, a mode register is first set. By setting this mode register, the operation mode of the SDRAM 75 is set. The mode register is set by a mode register setting command. The CAS latency, wrap type, and burst length are set by the mode register. After this mode register is set, the next command cannot be input until 20 ns or more have elapsed.
[0095]
The CAS latency is the most important of these parameters, and sets the latency (number of clocks) from command input to data read. That is, after a command is input, data read is started after waiting for this CAS latency. The CAS latency is set by selecting any value from, for example, “1”, “2”, or “3”. In this example, the CAS latency is set to '2'.
[0096]
The wrap type designates the order in which the burst data address is incremented when performing burst write / burst read. Either sequential or interleave can be selected. The burst length is selected and set from among “1”, “2”, “4”, “8”, or full page. In this example, the burst length is set to '4'.
[0097]
In the SDRAM 75, a predetermined row address of the target bank is activated by an active command, and is in a state where writing / reading is possible. Then, a data write / data read command for the row address of the activated bank is input, and data is input to write / read data to / from the target row address of the target bank. It is necessary to precharge after writing / reading data. By executing the write / read command with auto precharge, the precharge can be automatically performed after a predetermined period after the data is written / read.
[0098]
The interval between write commands is one clock. That is, the write command can be input without limitation every clock. Similarly, the interval between read commands is one clock, and the read command can be input without limitation for each clock. However, since there is CAS latency at the time of reading, there is a delay corresponding to the CAS latency from when a read command is input to when data is actually output. In this example in which the CAS latency is designated as “2”, data is output two clocks after the read command is input.
[0099]
These write commands and read commands can be interrupted by different write commands or read commands. As a result, the column address for writing or reading can be specified in units of one clock.
[0100]
In the SDRAM 75, as a restriction based on the asynchronous characteristic, a predetermined interval is required between each command input and operation. Violation of this restriction causes a malfunction of the SDRAM 75. FIG. 14 shows a list of examples of the constraint conditions. The numerical value shown at the top is the cycle that is the minimum interval of operation of the SDRAM 75. Here, an example in which an SDRAM having a cycle of 13 ns is operated with a clock of 20 ns will be described.
[0101]
The interval from one refresh command to the next refresh command or active command is the interval t_RCAnd a minimum of 130 ns corresponding to 7 clocks is required. The interval from the active command to the precharge command is the interval t_RASAnd a minimum of 91 ns is required. This corresponds to 5 clocks. Conversely, the interval between the precharge command and the active command is the interval t_RPAnd 39 ns is required. This corresponds to two clocks. The interval between the active command and the data read / data write command is the interval t_RCD39 ns corresponding to two clocks is required. The interval between each active command when activating one bank after activating one bank is the interval t_RRDAnd requires 39 ns. This corresponds to two clocks.
[0102]
The interval between the data input and the precharge command is the interval t_DPLIt is called. When data is written by a write command with auto precharge and auto precharge is specified, the interval between the last data input and the next active command is the interval t_DALIt is called. These intervals t_DPLAnd interval t_DALDepends on CAS latency. Interval t_DPLIn the case where the CAS latency is 3, 1 clock + 13 ns is required. This corresponds to two clocks. When the CAS latency is 1 or 2, 19.5 ns corresponding to one clock is required. Also, the interval t_DALIn the case where the CAS latency is 3, 2 clocks +39 ns are required. This corresponds to 4 clocks. When the CAS latency is 1 or 2, 1 clock + 39 ns is required. This corresponds to 3 clocks.
[0103]
Next, data write / read control with respect to the SDRAM 75 in consideration of such restrictions will be described with reference to FIGS. 15 and 16 and FIG. 13 described above.
[0104]
First, the inner code series will be described. In the writing / reading of the inner code sequence, there are a sequence starting from bank A and a sequence starting from bank B. This is because the first half and the second half in the inner code direction are alternately arranged for each row address with respect to bank A and bank B. FIG. 15A shows writing of the inner code sequence starting from bank A, and FIG. 15B shows reading starting from bank A. Similarly, FIG. 15C shows writing of the inner code sequence starting from bank B, and FIG. 15D shows reading starting from bank B. Further, in common with each drawing of FIG. 15 and FIG. 16 described later, the upper row indicates a control command, and the lower row indicates data.
[0105]
In FIG. 15A, an active command RAx is supplied to activate a predetermined row address x of bank A. By this command RAx, the row address of the x-th row is made active. As shown in FIG. 13 described above, the first data (S0-D0) is written at an address represented by a row address “0” and a column address “1”. Therefore, here, x is set to “0”, and the row address “0” is activated. Interval t from this active command RAx_RCDAfter the elapse of (that is, two clocks), a write command is executed, and a column address for writing data is designated.
[0106]
As described above, in the SDRAM 75, a write command can be input without limitation at every clock. Using this, when a column address is specified, write commands are successively interrupted every clock. As a result, the column addresses are successively designated in units of words such as CA0, CA1, CA2,..., CA55. Following the address CA55, writing to the column address CAdum, which is an empty area, is designated, and dummy data is written for 4 words. This writing of dummy data is designated because precharge is executed when writing to bank B is performed following bank A.
[0107]
When this CAdum, which is the last address of the bank A, is specified, the column address CAdum is specified by a write command with auto precharge. In this example in which the CAS latency is set to '2', precharge is automatically started one clock after the command CAdum is input.
[0108]
Each column address is designated such that the same inner code series are consecutive and the outer code series are written according to the data order. That is, referring to FIG. 13B described above, the data is arranged in a burst length unit with respect to the row address, the outer code direction sequence (Dy) is the same, and the inner code direction sequence (Sx) is continuous. Has been. Therefore, the column address is incremented in units of burst length and sequentially designated with respect to the column address designated first. For example, the column address “4” is designated when the column address CA0 is designated, and the column address “8” is designated at the address CA1.
[0109]
By specifying the column address in this manner, data is continuously input to the row address RAx as Sx-D0, Sx-D1, Sx-D2,..., Sx-D108, Sx-D109. Can write.
[0110]
When the column address CAdum is designated, an active command RBx for activating the bank B is input with the same row address at intervals of two clocks. Thereafter, the address is designated by the same control as the writing to the bank A, and the data is written. Next to the last data corresponding to the row address, an empty area is designated by the column address CBdum, and dummy data is continuously written for 4 words.
[0111]
When writing to the bank B is completed, the starting column address is again moved from the bank A to the next, and the same control is performed. For example, in the above description, since the column address “4” is the first address, the adjacent column address “5” is the first address here. This control is repeated for the burst length, that is, four times. As a result, for example, all the data writing to the row address “0” shown in FIG. 13 is completed.
[0112]
When the writing of the inner code sequence starting from bank A is completed, the row address is incremented by one, and the inner code sequence starting from bank B is written as shown in FIG. 15C. The writing of the inner code sequence starting from the bank B is the same as the writing starting from the bank A in FIG. 15A except that the address designation is switched between the bank A and the bank B. Omitted.
[0113]
In this way, the control shown in FIGS. 15A and 15C is alternately performed while sequentially incrementing the row address. By performing such control, data is written in the arrangement as shown in FIGS. 13A and 13B described above in accordance with the order of the inner code series. When the writing to the row address '62' is completed, the writing of all data is completed.
[0114]
The reading of the inner code series is also performed by substantially the same control as the writing. That is, as shown in FIG. 15B, a predetermined row address of the bank A is activated by the active command RAx, and the interval t_RCDAfter the elapse, a read command is input and a column address is designated. Data is read in units of burst length, reading of bank A is completed, and precharging is executed. And the interval t_RPBank B is activated later, and reading from bank B is performed. After repeating this for the burst length, the row address is incremented, and reading of the inner code series from the bank B shown in FIG. 15D is started. In this way, the control shown in FIGS. 15B and 15D is alternately performed while sequentially incrementing the row address.
[0115]
In the case of reading, due to the presence of CAS latency, data is read with a delay of CAS latency with respect to the input of the active command. In the example shown in FIG. 15B, an active command RAx for activating a predetermined row address x of the bank A is input, and the interval t_RCDThat is, a read command is input after 2 clocks, and a column address CA0 is designated. The data is read from the column address CA0 by CAS latency, that is, in this example in which the CAS latency is set to “2”, the data is read after two clocks from the designation of the column address CA0 by the read command. .
[0116]
Also, at the time of reading, a dummy read address is designated corresponding to the precharge at the time of switching the bank. At the time of reading, unlike data writing, data destruction or the like does not occur due to access to dummy data, so dummy data for three column addresses shorter than the burst length is read.
[0117]
By performing the control at the time of reading in this way, the data written as shown in FIG. 13 can be sequentially read in the inner code direction. As described above, with respect to the inner code series, only 8 clocks required for writing dummy data when writing data and 6 clocks required for reading dummy data when reading data are not wasted. is there.
[0118]
Next, the outer code sequence will be described with reference to FIG. Regarding the writing / reading of the outer code sequence, there are a sequence starting from bank A and a sequence starting from bank B. The sequence starting from bank A is for the first half of the inner code sequence, and the sequence starting from bank B is for the second half. FIG. 16A shows writing of the inner code sequence starting from bank A, and FIG. 16B shows reading starting from bank A. Similarly, FIG. 16C shows the writing of the inner code sequence starting from the bank B, and FIG. 16D shows the reading starting from the bank B.
[0119]
In the above inner code direction, data is written / read in the horizontal direction, that is, in the column direction with respect to the address space shown in FIG. On the other hand, in this outer code series, data is written / read in the vertical direction with respect to the address space, that is, in the row direction. Data is written / read so that the inner code sequence is continuous for each identical outer code sequence by incrementing the row address and specifying the address while alternately switching between bank A and bank B and interleaving. It can be performed.
[0120]
First, writing will be described. As shown in FIG. 13, the data (S0-D0) to be written first is arranged at the row address “0” and the column address “1” of the bank A. Therefore, as shown in FIG. 16A, the writing is started from the bank A, and the active command RA0 is input to activate the row address “0” of the bank A. Next, a column address is specified. Interval t from this active command RA0_RCDAfter the elapse of (that is, 2 clocks), a write command with auto precharge is input, and a column address CAy for writing data is designated. By this write command, data is written in burst length units. Further, in this SDRAM 75, since one word is 16 bits, symbols each consisting of 8 bits are written two by two.
[0121]
For example, when y = 1, a set of data written to the same column address from column addresses “1” to “4”, that is, data S0-D0 and S0-D1, S1-D0 and S1-D1, S2-D0. And S2-D1, and S3-D0 and S3-D1 are continuously written. When this writing is completed, precharging is automatically started.
[0122]
The address to which the next data is to be written is the row address one level higher in the bank B as shown in FIG. Therefore, the bank is switched from bank A to bank B. While writing to the bank A is being performed, an active command RB1 for activating the row address “1” of the bank B is input. The active command RB1 is input after two clocks after the above-described write command with auto precharge specifying the column address CAy is input.
[0123]
Interval t after active command RB1 is input_RCDAfter (2 clocks), a write command with auto precharge is input, and a column address CBy for writing data is designated. Here, a column address “0” is designated. As in the case of bank A described above, 4 data × 2 (S4-D0 and S4-D1, S5-D0 and S5-D1, S6-D0 and S6- D1, S7-D0 and S7-D1) are written, and after being written, precharging is automatically performed.
[0124]
Further, while writing is being performed on the bank B, the active command RA2 of the bank A is input, and the next row address “2” of the bank A is activated. This active command RA2 is transmitted at an interval t from the data input previously made to bank A (from the clock in which S3-D0 was input in the above example)._DALThat is, it is input after waiting for three clocks. Then, a write command with auto precharge is input two clocks after the active command RA2, and the column address CAy of the bank A is designated. In this example, the column address “0” is designated.
[0125]
Hereinafter, the row address is incremented and the address is designated while alternately switching between the bank A and the bank B. The column address is fixedly designated until writing to the row address '62'. Since the burst length is 4 and the number of data in the outer code direction is 250, a remainder of 2 data is generated at the end of writing. Here, two pieces of dummy data are written.
[0126]
When writing to the row address “62” is completed, the row address is returned to the address “0”, the column address CAy is incremented, and writing to the next column address is started. This is repeated, and when writing is performed to the address specified by the row address '62' and the column address '223', all writing of the first half of the inner code series is completed. Then, the second half writing of the inner code sequence is started. Writing in the latter half of this inner code sequence starts from bank B.
[0127]
The writing started from the bank B is performed in the same manner as the writing started from the bank A described above. As shown in FIG. 16C, an active command RB0 for activating bank B is input. An interval t from this active command RB0_RCDAfter that, a write command with auto precharge is input and the column address CBy is designated. Since the writing started from the bank B is started from the column address “0”, y = 0 is set and the column address “0” is designated. While incrementing the row address and alternately switching between the bank B and the bank A, the column address is fixed for the banks A and B, and the address is designated. Data is written in burst length units continuously to the outer code sequence.
[0128]
Reading of the outer code series is performed by control substantially similar to writing. That is, for the read that starts from the bank A, as shown in FIG. 16B, the row address “0” of the bank A is activated by the active command RA0, and the interval t_RCDAfter the elapse of time, a read command with auto precharge is input, the column address CAy is designated, and data is read from the designated column address CAy in burst length units. Further, an active command RB1 is input after two clocks of the read command, the bank B is activated, and the row address is incremented. The interval t from this active command RB1_RCDAfter the elapse of time, a read command with auto precharge is input, the column address CBy is designated, and data is read from the designated column address CBy in units of burst length.
[0129]
As described above, the column address corresponding to each of the banks A and B is fixedly designated while incrementing the row address and alternately switching between the bank A and the bank B during reading. Thus, the address is designated, and the data of the same inner code sequence is read in burst length units continuously in the outer code direction. When the reading up to the row address “62” is completed, the column address is incremented and the reading is similarly started from the row address “0”. Thus, when all the readings started from the bank A are completed, the reading from the bank B shown in FIG. 16D is started. Reading from the bank B is performed by substantially the same control as the reading started from the bank A.
[0130]
At the time of reading, the CAS latency is limited, and the reading is started after the clock specified by the CAS latency elapses after the read command is input. Therefore, in this example, data reading is started two clocks after the column address CAy is designated by the read command.
[0131]
Further, when the CAS latency is 2, the auto precharge by the write command with auto precharge is started one clock before the burst data output last. For example, auto precharge by the first write command (CAy) with auto precharge in FIG. 16A is started at the data output timing of S2. In the same bank, the interval t from the start of pre-jersey to the input of an active command_RPRequired (2 clocks). After the elapse of two clocks, the next active command RA1 is input.
[0132]
Thus, according to this embodiment, for the outer code series, only two clocks required for writing dummy data at the time of data writing and only two clocks required for reading of dummy data at the time of reading are used. The clock is efficient without waste.
[0133]
As described above, in this example, writing and reading of the data of the inner code sequence is performed most efficiently when both are performed in units of one sync block, and the processing is shown in FIG. As can be seen, 122 clocks are required. Similarly, both the writing and reading of the outer code sequence data are performed most efficiently when the outer code sequence data shown in FIG. 12 is used as a unit. As can be seen from the diagram, 254 clocks are required for writing and 256 clocks are required for reading. The reason why the number of clocks required for writing and reading is different is that reading is started after a clock specified by CAS latency elapses after a read command is input due to the CAS latency limitation.
[0134]
If the processing is further decomposed for both the inner code sequence and the outer code sequence, the processing method differs, and the efficiency of data access in the SDRAM 75 is reduced. Therefore, the decomposition of each process is performed up to here, and the number of clocks for one slot is determined based on the decomposition result.
[0135]
Video data output after inner code and outer code correction processing, read / write for video data outer code correction, data write after inner code correction, and data read for audio outer code correction For each, the number of clocks in one slot is obtained. The number of clocks in one slot is determined so that the number of slots required for one frame is substantially equal for various processes. Thereby, various processes can be easily performed.
[0136]
In the video data output processing after the inner code and outer code correction processing, data is read from the SDRAM 75 in the inner code sequence direction. As shown in FIG. 15, the reading of the inner code series requires 122 clocks. At this time, an error flag is read together with the video data. Reading this error flag requires 32 clocks. Therefore, in this process, as shown in FIG. 11 described above, 122 clocks + 32 clocks = 154 clocks are allocated, and this is one slot in this process.
[0137]
One frame is composed of six segments, and one ECC decoder IC 60 processes one error correction block per segment. One error correction block consists of 226 sync blocks. Therefore, the number of slots per frame is 226 sync blocks / segment × 6 segments / frame = 1356 sync blocks / frame. As described above, since one sync block is one slot in writing / reading the inner code series, it is 1356 slots / frame. Actually, since other fine processing is added, 1400 slots / frame is required as shown in FIG.
[0138]
In the read / write processing for correcting the video data outer code, the SDRAM 75 is accessed in the outer code sequence direction. As shown in FIG. 16, in the access of the outer code series, 254 clocks are required for writing and 256 clocks are required for reading, and the required number of clocks is different. However, since the slot length needs to be fixed, one slot is set to 256 clocks as shown in FIG. 11 in accordance with the longer clock.
[0139]
As can be seen from FIG. 13 above, in the address assignment of the SDRAM 75, two data are assigned to one word. Therefore, when video data is written / read in the direction of the outer code sequence in accordance with the chart of FIG. 16, writing / reading of two outer code sequences can be performed by processing for one slot. Further, as can be seen from FIG. 12, in one azimuth, there are 217 outer code sequences per segment. Accordingly, the number of slots per frame is 217 outer code series / segments / 2 data / word × 2 (write / read) × 6 segments / frame = 1302 outer code series / frame. Since one outer code sequence is one slot, it is set to 1302 slots / frame. Actually, since detailed processing such as error flag processing is added, as shown in FIG. 11, 1350 slots / frame is required.
[0140]
Similarly, in data reading for audio outer code correction, in this example, one slot is set to 16 clocks as shown in FIG. Further, 1300 slots / 1 frame is required.
[0141]
In the data writing process after the inner code correction, data is written to the SDRAM 75 in the inner code sequence direction. This processing requires 122 clocks as shown in FIG.
[0142]
By the way, the data writing process after the inner code correction is a process in which inner code correction is performed on the data reproduced from the magnetic tape 6 and subjected to the predetermined process, and the inner code corrected data is written in the SDRAM 75. is there. Therefore, it is influenced by the jitter of the running speed of the tape and the rotating speed of the rotating drum. As described above, in order to absorb this jitter, a buffering process using a buffer (RAM) provided in the rate converters 63 and 67 is performed. Therefore, data writing to the SDRAM 75 is performed asynchronously. That is, it cannot be specified when data is written to the SDRAM 75.
[0143]
On the other hand, in buffering processing for absorbing jitter, for example, when data for 122 clocks is written in the SDRAM 75, data for one sync block is swept out of the buffer. This buffer needs to be controlled so that it never overflows with possible jitter. Therefore, for example, in this embodiment, processing is performed at a ratio of 1/2 of the whole. Based on the above consideration, the number of slots required for data writing after inner code correction is 1546887 clocks / frame ÷ 122 clocks / slot × 1/2 (ratio) = 6340 slots / frame when 122 clocks are one slot. It is said. By assigning 6340 slots per frame, the data after the inner code correction can be written to the SDRAM 75 without omission.
[0144]
As described above, in the present invention, one sequence configured by collecting all types of slots is repeated. For this reason, if 122 clocks are set to 1 slot in the writing process after the inner code correction as described above, 6340 slots / frames are required, and as a result, 6340 sequences / frames are required. However, since the other processing only requires about 1400 slots / frame at most, a useless sequence occurs.
[0145]
Therefore, in this embodiment, a plurality of data for one sync block in the data writing process after the inner code correction is collected so that the number of slots per frame is substantially equal to that of other processes, and one slot is obtained. . In this example, four sync blocks are grouped into one slot. That is, as shown in FIG. 11, the data write processing after the inner code correction is 582 clocks / slot, and the processing is concentrated on this one slot. In one frame, 1534 slots / frame is required.
[0146]
Note that the processing for grouping data for four sync blocks is performed by, for example, a RAM provided as a buffer for absorbing jitter in the above-described rate converters 63 and 67 having a capacity for three sync blocks. It is accompanied by. The output from this buffer is controlled by the inner code decoder 69 so that the data for four sync blocks are output together.
[0147]
Thus, by determining the slots for various processes, one sequence is set to 1008 clocks as shown in FIG. When a system clock of 46.4 MHz is used, 1534 sequences / frame is obtained, and all processing can be completed.
[0148]
Next, a modification of this embodiment will be described. This modification is an example in the case of high-speed playback. High-speed reproduction is performed by moving the magnetic tape 6 at high speed, and the magnetic head 7 traces while traversing the track diagonally. Therefore, data can be reproduced in sync block units, but one error correction block is not configured because data for one track cannot be reproduced. Therefore, there is no need to perform outer code correction.
[0149]
Further, by performing high speed reproduction, the relative speed between the data recorded on the magnetic tape 6 and the magnetic head 7 changes, and the rate of data reproduced from the magnetic tape 6 increases. For this reason, during high-speed playback, data write processing after inner code correction to the SDRAM 75 may increase. FIG. 17 is a time chart showing an example of access to the SDRAM 75 during high-speed playback. FIG. 17A and FIG. 17B show periods of data writing processing after inner code correction and reading processing for video data output, respectively. As in this example, during high-speed playback, data writing processing of 6 segments or more may occur in one frame. In the example of FIG. 17C, writing of 7 segments has occurred.
[0150]
In this modification, a slot for reading and writing for correcting the outer code of video data, which is not necessary at the time of high-speed reproduction, is diverted to the data writing process after the inner code correction. FIG. 18 is a time chart showing an example of SDRAM access during high-speed playback according to this modification. FIG. 18A shows a writing cycle of video data and audio data after inner code correction. FIG. 18B shows processing of video data and audio data. As shown in FIG. 18C, the data write processing slot (256 clocks) after inner code correction at normal speed reproduction and the read / write processing slot (582 clocks) for video data outer code correction are combined. Thus, a new slot for 838 clocks is set. This new slot is used as a slot for data write processing after inner code correction at high speed reproduction. Since the number of clocks is increased, the increased processing by high-speed reproduction can be sufficiently performed.
[0151]
In this case, since the video data output processing after the inner code and outer code correction processing and the data reading for audio outer code correction are not related to high-speed playback, as shown in FIG. It is processed in exactly the same way as during playback. As described above, by using the present invention, even if the reproduction mode is changed, it is possible to correspond to the processing only by changing only the slot affected by the change.
[0152]
【The invention's effect】
As described above, according to the present invention, a single SDRAM connected to the ECC decoder IC is used in time division processing to perform data write processing after inner code correction, read / write processing for video data outer code correction, A plurality of types of processing such as data reading processing for audio outer code correction and video data output processing after inner code and outer code correction are performed. Furthermore, each type of processing is clearly delimited as a slot. Therefore, there is an effect that design and verification can be performed for each process.
[0153]
Also, when multiple types of processing are performed in a time division manner in one SDRAM, if the processing is performed asynchronously, the processing times are related to each other, so that all processing is always completed. Must assume all cases. For this purpose, the simulation becomes enormous, the guarantee is difficult, and the reliability as a product is lowered. Therefore, design becomes difficult and the circuit scale increases.
[0154]
In the present invention, since various processes are fixed in slot units, it is possible to perform time division processing in a synchronous manner. Therefore, since it is only necessary to ensure that the processing is reliably completed in each given slot for each type of processing, the simulation for ensuring the reliability is simple and the risk of bugs is reduced. Therefore, there is an effect that the reliability of the product is improved and the circuit scale can be reduced.
[0155]
Further, when the processing is performed asynchronously, it is not known where various processing is performed, and verification after the ECC decoder IC is completed becomes very difficult. By using the present invention, complete synchronization in units of frames and complete synchronization within a sequence are realized, so that the timing at which various processes are performed is made constant, and verification can be performed very easily. .
[0156]
Furthermore, for example, during high-speed playback, the relative speed between the rotating drum (magnetic head) and the magnetic tape changes, and data writing after inner code correction to the SDRAM may increase. According to the modification of the present invention, it is not necessary at the time of high-speed reproduction, for example, the slot for the read / write process for video data outer code correction is diverted to the data write process slot after the inner code correction. There is an effect that can cope. At this time, there is no influence on the slots of other unrelated processes, and there is no need to change them. That is, there is a public A that can easily cope with the difference in processing depending on the mode of the video tape recorder only by diverting the slot.
[Brief description of the drawings]
FIG. 1 is a block diagram schematically showing an example of the configuration of a digital video recording / reproducing apparatus to which the present invention is applied.
FIG. 2 is a schematic diagram schematically illustrating an example of a configuration of an error correction block.
FIG. 3 is a schematic diagram schematically illustrating an example of a configuration of an error correction block.
FIG. 4 is a schematic diagram illustrating a configuration of one sync block in an error correction block.
FIG. 5 is a block diagram illustrating an example of a configuration of an ECC decoder IC.
FIG. 6 is a schematic diagram illustrating an example of a data configuration in one packet.
FIG. 7 is a schematic diagram showing an example of a format when reproduction data for one sync block is written to an SDRAM.
FIG. 8 is a schematic diagram showing row address assignment in an SDRAM.
FIG. 9 is a schematic diagram illustrating column address assignment in an SDRAM.
FIG. 10 is a time chart showing an example of SDRAM access during normal speed playback;
FIG. 11 is a time chart showing an example of time division processing for data writing and reading in the SDRAM;
FIG. 12 is a schematic diagram showing in detail an example of a data arrangement in an error correction block of video data.
FIG. 13 is a schematic diagram illustrating an example of address assignment in an SDRAM.
FIG. 14 is a schematic diagram showing a list of examples of constraints of SDRAM.
FIG. 15 is a timing chart for explaining writing / reading of an inner code sequence.
FIG. 16 is a timing chart for explaining writing / reading of an outer code sequence.
FIG. 17 is a time chart showing an example of SDRAM access during high-speed playback.
FIG. 18 is a time chart for explaining diversion of a slot.
FIG. 19 is a block diagram showing an example of a configuration of a conventional digital recording / reproducing apparatus using product code encoding.
[Explanation of symbols]
6 ... Magnetic tape, 7 ... Magnetic head for reproduction, 9 ... Inner code / outer code decoder, 10 ... RAM, 60 ... ECC decoder IC, 63, 67 ... Rate conversion 69 ... Inner code decoder, 74 ... Memory controller, 75 ... SDRAM, 76 ... Video data outer code decoder

Claims (10)

In an error correction apparatus that decodes data that has been error correction encoded using a product code,
An inner code decoder for performing inner code correction;
An outer code decoder for performing outer code correction after the inner code correction is performed;
A memory for storing data subjected to error correction by the inner code decoder and data subjected to error correction by the outer code;
The same type of processing is divided into slots defined by the reference clock, and a sequence is constituted by a plurality of the slots of the same type of processing, and the one sequence is repeated a predetermined number of times in the period of one frame or one field. Error correction processing ,
When there is no need for the outer code correction, the slot for performing the data reading and writing process for the outer code correction of the video data to the memory is the slot for performing the data writing process for the memory after the inner code correction. An error correction apparatus characterized by being diverted as: The error correction device according to claim 1,
The same type of processing includes data write processing after the inner code correction to the memory, data read and write processing for the outer code correction of video data to the memory, and data from the memory for data output. An error correction apparatus characterized by being a data reading process. The error correction device according to claim 2,
The same type of processing further includes a data reading process for correcting the outer code of the audio data from the memory. The error correction device according to claim 1,
An error correction apparatus, wherein an initial sequence of one frame period is started in synchronization with a reference frame pulse. The error correction device according to claim 1,
An error correction apparatus characterized in that the order of the slots in one sequence is fixed. The error correction device according to claim 2,
The slot for the data writing process after the inner code correction to the memory and the slot for the data reading and writing process for the outer code correction of the video data to the memory are arranged adjacent to each other in the sequence. An error correction device characterized by that. The error correction device according to claim 2,
An error correction apparatus, further comprising a buffer in front of the inner code decoder, wherein control is performed so that data is output from the buffer in the slot of the data writing process after the inner code correction to the memory. . In a digital signal reproduction device using an error correction device that decodes data that has been error correction encoded using a product code,
An inner code decoder for performing inner code correction;
An outer code decoder for performing outer code correction after the inner code correction is performed;
A memory for storing data subjected to error correction by the inner code decoder and data subjected to error correction by the outer code;
The same type of processing is divided into slots defined by the reference clock, and a sequence is constituted by a plurality of the slots of the same type of processing, and the one sequence is repeated a predetermined number of times in the period of one frame or one field. If the error correction process is performed and the outer code correction is not necessary , the slot for performing the data reading and writing process for the outer code correction of the video data to the memory is designated as the inner code for the memory. A digital signal reproducing device comprising an error correcting device adapted to be used as the slot for performing data writing processing after correction . In an error correction method for decoding data that has been error correction encoded using a product code,
An inner code decoding step for inner code correction;
An outer code decoding step of performing outer code correction after the inner code correction is performed;
Storing the error correction by the step of the inner code decode has been performed the data in the memory,
The error correction by the step of the outer code decoding is performed data have <br/> and storing in the memory,
The same type of processing is divided into slots defined by the reference clock, and a sequence is constituted by a plurality of the slots of the same type of processing, and the one sequence is repeated a predetermined number of times in the period of one frame or one field. Error correction processing ,
When there is no need for the outer code correction, the slot for performing the data reading and writing process for the outer code correction of the video data to the memory is the slot for performing the data writing process after the inner code correction to the memory. An error correction method characterized by being diverted as : In a digital signal reproduction method using an error correction method for decoding error correction encoded data using a product code,
An inner code decoding step for inner code correction;
An outer code decoding step of performing outer code correction after the inner code correction is performed;
Storing the error correction by the step of the inner code decode has been performed the data in the memory,
The error correction by the step of the outer code decoding is performed data have <br/> and storing in the memory,
The same type of processing is divided into slots defined by the reference clock, and a sequence is constituted by a plurality of the slots of the same type of processing, and the one sequence is repeated a predetermined number of times in the period of one frame or one field. If the error correction process is performed and the outer code correction is not necessary, the slot for performing the data reading and writing process for the outer code correction of the video data to the memory is designated as the inner code for the memory. A digital signal reproduction method using an error correction method diverted as the slot for performing data writing processing after correction .

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