JPH1146146A - Device and method for correcting error and device and method for reproducing digital signal - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain an error correcting device which does not have wasteful power consumption, an increase of the number of pins, an increase in costs, etc., by using one SDRAM that is connected to an ECC decoder IC in time division processing and performing plural kinds of processing. SOLUTION: An internal code/external code decoder 9 which decodes data that are encoded through a product code is configured in an integrated circuit. Read reproduced data are made into serial data through an equalizer 8, supplied to the decoder 9, performed internal code correction, undergone address control and written to RAM 10. Next, data are read in the direction of an external code, supplied to the decoder 9, performed external code correction and rewritten to the RAM 10. Data are read from the RAM 10 in the direction of the internal code (original order of the data) and outputted. The control of a timing of writing and reading data to/from the RAM 10 is performed with time division by the control of the decoder 9.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error correcting apparatus and method for decoding digital data error-corrected using a product code using a single external RAM, and a method thereof. And a digital signal reproducing apparatus and method.

[0002]

2. Description of the Related Art At present, A / V (audio / video) such as DVCR (digital video cassette recorder) is used.
2. Description of the Related Art In an apparatus for digitally recording / reproducing a signal on a recording medium such as a magnetic tape, encoding using a product code is often used for error correction.

In the coding by the product code, data arranged in a matrix in units of one symbol (for example, one byte) is coded in a column direction by, for example, a Reed-Solomon code. Code parity is generated. Then, the data and the outer code parity are encoded in the row direction to generate an inner code parity. As described above, the outer code parity is generated in the column direction and the inner code parity is generated in the row direction, so that the error correction coding by the product code is performed. At this time, the time-series order of the data coincides with, for example, the row direction.

FIG. 19 shows an example of the configuration of a digital recording / reproducing apparatus according to the prior art using the encoding by the product code. For example, digital video data is recorded as BRR (Bit R
ate Reduction) encoder 101. This B
The RR encoder 101 performs data compression on the supplied recording data. The compressed recording data is
The signal is supplied to the error correction encoder 102 that performs the error correction encoding based on the product code described above.

The error correction encoder 102 has an RA
M (not shown), and the supplied recording data is written to the RAM. As described above, the outer code parity and the inner code parity are generated for the recording data supplied and written to the RAM memory, and the product code is subjected to error correction encoding.
The encoded recording data is read from the RAM according to the above-described row direction, supplied to the recording driving unit 103 including an amplifier for recording, and recorded on the magnetic tape 105 by the magnetic head 104.

The recording at this time is performed by, for example, the magnetic head 1
The magnetic head 104 is provided on a rotating drum.
Is performed by a helical scan method in which tracks are formed obliquely with respect to the magnetic tape 105.

[0007] Data recorded on the magnetic tape 105 is read by the magnetic head 106 and is used as reproduction data. The reproduced data is supplied to the inner code decoder 108 via the equalizer 107, and error correction by the inner code (hereinafter, referred to as “inner code correction”. Similarly, error correction by the outer code is referred to as “outer code correction”. ) Is performed. That is, error correction is performed for each row based on the inner code parity allocated to each row of data. Then, as a result of the error correction, an error flag is added to the symbol in each row. For example, if the number of errors exceeds the error correction capability of the code and the error remains uncorrected, an error flag is added to all the symbols in the row to indicate that an error exists. Is done.

The reproduced data having the inner code error corrected is written to the RAM 109. The inner code decoder 108 can perform address control on the RAM 109. The reproduced data written in the RAM 109 is address-controlled by the inner code decoder 108 and is arranged in the address space of the RAM 109.

When the inner code is corrected in the inner code decoder 108, the error-corrected reproduced data is read from the RAM 109. At this time, the reproduced data is read out in the column direction of the product code in the RAM 109 by the address control by the decoder 108. Therefore, in this RAM 109,
The order of the data is read in the direction of the outer code.

The reproduced data read in the outer code direction is supplied to the outer code decoder 110, and the outer code decoder 110 corrects the outer code. That is, error correction is performed for each column based on the outer code parity allocated to each column of data. At the time of this outer code correction, an error flag attached to each symbol at the time of decoding in the inner code decoder 108 is used together with the outer code.

The reproduced data having been subjected to the error correction in the outer code decoder 110 is written to the RAM 111. The outer code decoder 110 can perform address control on the RAM 111.
The reproduced data to be written into the
The address is controlled by the address 10 and is arranged in the address space of the RAM 109.

[0012] As an error correction result, an error flag is added to each symbol. This is, for example,
If the number of errors exceeds the error correction capability of the code and no error correction has been performed, this is added to indicate that an error exists.

When outer code correction is performed in outer code decoder 110, the error-corrected reproduced data is stored in RA.
Read from M111. At this time, the decoder 110
The reproduction data is stored in the RAM 1
Data is read out in the row direction in the address space of No. 11. Therefore, in this RAM 111, RAM
The read direction read at the time of reading from 109 is read again, and is returned to the first read direction, that is, the original data order.

The reproduced data on which the inner code and the outer code have been corrected in this way is supplied to the BRR decoder 112. In the BRR decoder 112, the data compression applied to the data at the time of recording is released. The decompressed reproduction data is output to the outside as digital video data via the interface 113.

For data to which an error flag has been added without being completely corrected by the outer code decoder 110, error correction is performed thereafter by using a technique such as interpolation.

In the digital recording / reproducing apparatus as described above, the BRR encoder 101 on the recording side is actually used.
And the error correction encoder 102 are each configured by one integrated circuit. On the reproduction side, the inner code decoder 108, the outer code decoder 110, and the BRR
Each of the decoders 112 is formed of one integrated circuit.

[0017]

As described above, digital data encoded by a product code is decoded by first performing an inner code correction and then performing an outer code correction based on the result. In addition, at the time of each error correction by the inner code and the outer code, data is replaced. Therefore, as described above, the RAM 109 for reading the product code in the column direction and the RAM 111 for reading the product code in the row direction are required.

The inner code decoder 108 and the outer code decoder 110 each have only relatively small functions. In the ICs constituting the decoders 108 and 110, a system clock having the same rate as the video data read rate is used as an internal clock. Therefore, the control of the RAMs 109 and 111 was easy.

However, these RAMs 109, 11
1 must be connected to the inner code decoder 108 and the outer code decoder 110, respectively, so that the number of pins in each of the integrated circuits of the inner code decoder 108 and the outer code decoder 110 increases, and the power consumption accordingly increases. There was a problem of becoming large.
Further, independent external RAMs are RAMs 109 and 111.
However, there is a problem that the cost is disadvantageous because two are required as in the above.

Therefore, an object of the present invention is to provide two RAs for reading a product code in a column direction and a row direction.
It is an object of the present invention to provide an error correction apparatus and method, and a digital signal reproduction apparatus and method, in which problems such as wasteful power consumption, an increase in the number of pins, and an increase in cost due to the use of M are eliminated. is there.

[0021]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention provides an error correcting apparatus for decoding data which has been error-correction-encoded using a product code. A decoder, an outer code decoder that performs outer code correction after inner code correction is performed, and a memory that stores data corrected by the inner code decoder and data corrected by the outer code. The same type of processing is decomposed into slots defined by the reference clock, and one sequence is constituted by a plurality of slots of the same type of processing, and one sequence is repeated a predetermined number of times in a period of one frame or one field. An error correction device characterized in that the error correction device performs error correction processing.

According to another aspect of the present invention, there is provided a digital signal reproducing apparatus using an error correction apparatus for decoding data subjected to error correction coding using a product code. An inner code decoder that performs an inner code correction, an outer code decoder that performs an outer code correction after the inner code correction is performed, and data that has been subjected to error correction by the inner code decoder and data that has been subjected to error correction by the outer code. And a memory, wherein the same type of processing is decomposed into slots defined by a reference clock, one sequence is constituted by a plurality of slots of the same type of processing, and one sequence is performed a predetermined number of times in a period of one frame or one field. A digital signal reproducing device comprising an error correcting device for repeating an error correction process A.

According to another aspect of the present invention, there is provided an error correction method for decoding data that has been error-correction-encoded using a product code. An outer code decoding step of performing outer code correction after inner code correction, and a memory for storing data corrected by the inner code decoder and data corrected by the outer code. The same type of processing is decomposed into slots defined by the reference clock, and one sequence is constituted by a plurality of slots of the same type of processing, and one sequence is repeated a predetermined number of times in a period of one frame or one field. This is an error correction method characterized by performing an error correction process by using an error correction method.

According to another aspect of the present invention, there is provided a digital signal reproducing method using an error correction method for decoding error correction encoded data using a product code. An inner code decoding step to be performed, an outer code decoding step to perform an outer code correction after the inner code correction is performed, and data subjected to error correction by the inner code decoder and data subjected to error correction by the outer code. And the same type of processing is decomposed into slots defined by the reference clock, one sequence is constituted by a plurality of slots of the same type of processing, and one sequence is one frame or one field. An error correction method that performs an error correction process by repeating a predetermined number of times in a period. It is a digital signal reproduction method.

As described above, in the present invention, a predetermined unit of the same type of processing is a slot, a plurality of types of slots are collected to form a sequence, and the sequence is repeated within one frame or one field. Therefore, time-division processing is facilitated, and design and verification can be performed for each type of processing.

[0026]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 schematically shows an example of the configuration of a digital video recording / reproducing apparatus to which the present invention is applied. In this configuration, an inner code decoder for performing inner code correction for decoding data encoded by a product code and an outer code decoder for performing outer code correction are configured in an integrated circuit. The RAM for replacement is shared. According to the present invention, at this time, a slot is formed by combining various processes in predetermined units, a sequence is formed by collecting various slots, and the sequence is repeated within one frame. Access to the RAM is made by time division processing based on the slot.

In FIG. 1, recording data including, for example, video data and four-channel audio data is supplied to a BRR encoder 2 via an interface 1. In the BRR encoder 2, the supplied recording data is subjected to data compression. This compression
For example, the data supplied to the BRR encoder 2 is divided into blocks, DCT-transformed, quantized, and variable-length coded. The recording data compressed in this way is supplied to the error correction encoder 3.

The error correction encoder 3 has a RAM
(Not shown), and the supplied recording data is written to the RAM. And supplied R
For this recording data written in the AM memory, an outer code parity and an inner code parity are generated and error correction coding of a product code is performed, as described in the above-described related art. The size of the data in which the product code of the inner code and the outer code is completed is called an error correction block.

The encoded data from the error correction encoder is read from the RAM in the above-described row direction, supplied to a recording drive unit 4 including an amplifier for recording, and recorded on a magnetic tape 6 by a magnetic head 5. You. This recording is performed by a helical scan method in which tracks are formed obliquely with respect to the magnetic tape 6 by a magnetic head 5 provided on a rotating drum, and further, a set of magnetic heads having different angles from each other. The azimuth method is used in which different azimuths are recorded in adjacent tracks.

As an example of this recording system, when four magnetic heads 5 are provided on a rotating drum and channels corresponding to the respective heads are A, B, C, and D, these four magnetic heads 4 Tracks are formed in the order of A, B, C, and D. Of these, tracks A and C, and tracks B and D have the same azimuth. At this time, a segment is composed of two adjacent tracks (A and B channels and C and D channels) having different azimuths. Further, audio data having four channels is arranged, for example, at the center of a track so as to be interposed between video data.

The data recorded on the magnetic tape 6 is read out by the magnetic head 7 in the order in which the recording data was recorded, and is used as reproduction data. The read reproduction data is converted into serial data via an equalizer 8 and supplied to an inner / outer code decoder 9. The inner code / outer code decoder 9 is one in which the inner code decoder and the outer code decoder are configured as one integrated circuit, and can perform address control on the connected RAM 10.

The reproduced data supplied to the inner code / outer code decoder 9 is subjected to inner code correction, address-controlled, and
AM10 is written. Thus, when data for one error correction block is accumulated in the RAM 10, data is read in the outer code direction and supplied to the inner code / outer code decoder 9 in order to perform outer code correction. The supplied data is subjected to outer code correction and written into the RAM 10 again. When the error correction for one error correction block is completed in this manner, data is read out from the RAM 10 in the inner code direction (the order of the original data) under the control of the inner code / outer code decoder 9 and output. At this time, if an error exists beyond the error correction capability of the code, an error flag is attached to a predetermined position with respect to the data and output.

At the time of data input / output at the time of correcting the inner code and outer code in the RAM 10, there is a difference in processing units between video data and audio data in A / V data.
In this case, data replacement for outer code correction and output for error-corrected output occurs, so that the timings of writing and reading data to and from the RAM 10 intersect. Therefore, the control of the timing of writing and reading data to and from the RAM 10 is performed in a time division manner under the control of the inner code / outer code decoder 9. Details of this control will be described later.

The reproduced data output from the inner code / outer code decoder 9 is supplied to a BRR decoder 11.
In the BRR decoder 11, the data compression applied to the data at the time of recording is released. For example, the data supplied to the BRR decoder 11 is subjected to variable-length decoding, inverse quantization, inverse DCT transform, and inverse block transform to decompress the data. The reproduced data thus decompressed is output to the outside as digital video data via the interface 12.

For data to which an error flag has been added without being able to perform error correction in the inner code / outer code decoder 9, an error correction is performed thereafter using, for example, an interpolation method.

FIGS. 2 and 3 schematically show an example of the configuration of the above-described error correction block. In this example, one frame of data is constituted by 12 tracks formed on a magnetic tape. In addition, as described above, a segment is configured with two adjacent tracks having different azimuths as one set, and one frame includes 12 segments = 6 segments. These segments include
Up to five segment numbers are assigned.

In the example of the video data shown in FIG. 2, one track in these 12 frames forms one error correction block shown in FIG. 2B as shown in FIG. 2A. For example, for video data having a data array of 217 bytes × 226 bytes, data in each column is encoded by, for example, a (250,226) Reed-Solomon code in the direction of arrow b to generate a 24-byte outer code parity. Is done. Further, with respect to the video data and the outer code parity, the data of each row is, for example, (2
29, 217) encoded by the Reed-Solomon code to generate a 12-byte inner code parity. Also,
At the head of each data line, sync data and ID each having a size of 2 bytes are arranged.

FIG. 3 shows an example of the configuration of an error correction block in audio data. As shown in FIG. 3A, the audio data forms one error correction block with six tracks out of twelve tracks for one frame. For example, audio data composed of a data array of 217 bytes × 12 bytes is encoded in the direction of arrow b by, for example, a (24,12) Reed-Solomon code to generate a 12-byte outer code parity. Further, the video data and the outer code parity are coded in the direction of arrow a by, for example, a (229, 217) Reed-Solomon code to generate a 12-byte inner code parity. Sync data and ID are arranged at the head of each data line.

FIG. 4 schematically shows the structure of one sync block in these error correction blocks, taking video data as an example. The first two bytes are sync data. The next two bytes are an ID that describes the number (segment number) of one sync block in one track, the sync block number, and the like. This ID is followed by 217 bytes of video data (or outer code parity) and inner code parity. The recording data on the magnetic tape is a sequence of the sync blocks.

Next, a more detailed configuration of the inner code / outer code decoder 9 will be described with reference to FIG. In FIG. 5, 60
Indicates an IC circuit portion of the inner code / outer code decoder 9. The ECC decoder IC 60 basically has an inner code error correction function, an outer code error correction function, an audio signal processing function, an error counting function, and an auxiliary data reading function. Also, actually, the ECC decoder IC6
As for 0, two are used as one set, and one azimuth data of the reproduction data is input to one ECC decoder IC 60.

For this ECC decoder IC 60, 9
Serial data reproduced at a recording rate of 4 Mbps and a clock generated therefrom are input in parallel,
The data is input to the S / P converter 61 and becomes 8-bit data converted from serial to parallel data, and a 1/8 frequency-divided clock.

At this stage, since the high-speed 1-bit data is simply reduced in speed to the 8-bit width of the 11 Mbps rate, the break in the byte unit and the sync block unit is appropriate. Are converted to a regular data sequence by the synchronization detection function. The break between bytes is defined by the bit assignment of the output terminal of the synchronization detection circuit 62, and the break between sync blocks is defined by the strobe pulse STB added by the synchronization detection circuit 62. Next, the rate is changed to 46 MHz by the rate converter 63.

It should be noted that the ECC decoder IC 60 has two system inputs, a main system and a sub system, in order to support an 8-head system. The above is the circuit for the input through the main system, but the same configuration is provided for the input of the sub system. An S / P converter 65, a synchronization detection circuit 66, and a rate converter 67 are provided in the same manner as in the main system to process the reproduced data of the sub system. The data packets output from these circuits are mixed into one system by the OR circuit of the mixer 68. A signal originally coming at a rate of 11 Mbps is converted to a rate of 46 Mbps. Therefore, since a gap is left between each packet, data of the sub system and data of the main system can be mixed. However, if the mixing process is performed randomly, the data of both systems will collide, so that the two rate converters 63 and 67 start each other with reference to the busy state and keep the output during the output of the other party. I have. At this time, a 1-bit flag of sub / main is embedded in the packet so that the source of the packet can be determined.

The rate converters 63 and 67 perform this start and stop,
In order to absorb, for example, jitter of the running speed of the magnetic tape 6 and the rotating speed of the rotating drum included in the reproduced RF signal, a small RAM is provided inside each as a buffer. The output of this buffer is controlled by an inner code decoder 69 connected at the subsequent stage.

The input switching pulse SWP is
The information is delayed by the timing generator 64 by the delay time of the internal circuit, and information indicating the tape running direction is similarly delayed and embedded in the packets by the rate converters 63 and 67. Each of the rate converters 63 and 67 has a counter which is initialized at the timing of head switching and counted by the strobe pulse STB, and determines whether or not a data non-recording section (hereinafter referred to as a gap) in format according to the counter. Is determined, and the information is also included in the packet.

The packet output from the mixer 68 is subjected to inner code correction by an inner code decoder 69. The data from the inner code decoder 69 includes, for example,
Error correction information such as how many bytes have been corrected is embedded in the packet and input to the ID reproduction circuit 71.
If the inner code decoder 69 cannot correct the inner code, the ID
Can not trust. However, in the memory controller 74 described later, since the sequence and order of the outer code correction are determined with reference to the ID, it is necessary to reproduce the ID. Expecting from the non-correctable packet ID before and after, etc.,
The function of the ID reproduction circuit 71 is to reproduce the ID of the uncorrectable packet. The ID reproduction circuit 71 has a RAM capable of storing three packets for each of the main system and the sub system in order to refer to a packet that comes later. By utilizing the RAM, conversion to a 16-bit width and start-up with the video outer code decoder 76 are performed.

The error correction information obtained from the inner code decoder 69 is input to an error monitor (not shown). The error monitor encodes the error correction information and other information together, aggregates them into main / sub signals, and outputs them outside the ECC decoder IC 60. By performing D / A conversion on this output, the state of error correction can be observed.

The data output from the ID reproduction circuit 71 is subjected to a descrambling process by a descrambler 72. The main line data output from the descrambler 72 is transmitted via a memory controller 74 to an external SDRAM (Synchronous Dynamic Random Accumulator).
ess Memory) It is stored in 75.

At this time, the memory controller 74 performs the timing control of the data coming from the descrambler 72 and the address control for separately writing video data and audio data for each segment to the SDRAM 75.

When the main system video data is accumulated in one error correction code block (for one track), read control is performed on the SDRAM 75 in order to perform outer code correction processing by the video outer code decoder 76, and the outer code direction is controlled. , And sends the data to the outer video code decoder 76. The memory controller 74
The SDRAM 75 starts again from the data after the outer code processing.
Write to return to.

The memory controller 74 applies the main / decoded data to the data for which the decoding of the outer code for one track has been completed.
Sub data is selected, read in the direction of the inner code, and the ID is changed for an interface with the compression decoder via an ID renumbering circuit (not shown).
7 is output.

On the other hand, audio data for one field (one error correction coding unit of audio data)
Accumulates in the SDRAM 75, the audio processing circuit 78
Supplied to The audio processing circuit 78 performs predetermined processing such as external audio code correction, deshuffling, and error interpolation, and then converts the data into serial data.
9 is output.

As described above, the error correction block of the audio data is completed in one field for six tracks. Therefore, an error correction block of audio data is formed over the forward / reverse azimuth tracks. This ECC decoder IC 60 corresponds to one azimuth. Therefore, in order to correct the outer code of the audio data, it is necessary to send the audio data of which the inner code has been corrected to the ECC decoder IC 60 '(not shown) corresponding to the other azimuth. The audio data for which the inner code correction has been completed is sent to another ECC decoder IC 60 via the terminal 82.

This terminal 82 is capable of bidirectional data exchange. By setting the mode in a predetermined manner, another ECC decoder I is connected to terminal 82.
Audio data sent from C60 can be input.

In addition to the above, an interface 80 for a system control microcomputer (hereinafter, referred to as a syscon) is provided so that various settings can be made and error information can be read by the syscon. Although not shown, a circuit for extracting video auxiliary data other than video data and a circuit for extracting audio auxiliary data other than audio data are provided, and the extracted auxiliary data is sent to the system controller via the interface 80. . Further, an error counter 73 for counting the number of errors is provided.

The exchange of data with the system controller is as follows.
Data flows in the order of the interface 80, the timing generation circuit 64, the error counter 73, the memory controller 74, the outer code decoder 76, the audio processing circuit 78, and the interface 80 using a bus 81 having a predetermined bit width. In each unit, necessary data is taken out from the bus 81. In each unit, data to be read by the interface 80 flows to the bus 81.

In the ECC decoder IC 60, one sync block of data is treated as one packet.
FIG. 6 shows an example of the data structure in one packet.
Here, the data is handled with 8 bits as one symbol. ID0 and ID1 show the ID in the data structure of one sync block shown in FIG. 4 in more detail. That is, ID0 represents a sync block number, and ID1 represents a segment number, video / audio identification information, and the like. Data0 to Data21
Reference numeral 6 denotes video data or audio data. The data after ID2 is auxiliary data.

FIG. 7 shows an example of a format when one sync block of reproduction data is written to the SDRAM 75. Since the SDRAM 75 has a data width of 16 bits, the data format of the 8-bit width shown in FIG. 6 described above has 16 bits as one word and the number of words is reduced to half as 112 words. You.

When the reproduced data is written to the SDRAM 75, the timing of the data is controlled by the control of the memory controller 74. The reproduction data is divided into video data and audio data for each segment and written into the SDRAM 75, and the address control at this time is also performed by the memory controller 7.
4 is performed.

FIG. 8 and FIG. 9 show an example of address assignment in the SDRAM 75 by this address control. FIG. 8 shows row (column) address assignment. In bits 8-10, the video data is segment 0
The audio data is divided into ~ 5 segments.
It is fixed to '6'. Thus, bits 8 to 1
0 prevents video and audio data from colliding in address assignment. In the video data, bits 6 and 7 indicate the tape running direction, and are set to "0" for normal running and "1" for reverse running. Further, bits 0 to 5 are bits B7 to B7 when the sync block number is represented by eight bits B7 to B0.
Two 6 bits are entered.

In the audio data, bit 6,
7 is fixed to '0'. Bits 4 and 5
Are stored in the fields 0 to 3. Bits 2 and 3 are assigned to each of four audio channels. Bits 0 and 1 contain the 2 and 3 bits (B2, B3) of the sync block number.

FIG. 9 shows the assignment of column (row) addresses. This assignment of column addresses is common to audio data and video data. This SDRA
M75 has a two-bank configuration including a bank A and a bank B, and data is allocated to these banks A and B. In the column, bits 0 and 1 (B0, B1) of the sync block number are 0,
Data is allocated so that data of four sync blocks of 1, 2, and 3 are mixed. S0, S1, S described in the figure
2, S3 are bits 0, 1 of these sync block numbers.
(B0, B1) represents the data of the sync block in which 0, 1, 2, and 3, respectively.

Bits 0 and 1 in this column address
By combining the assignment of the sync block with the above-mentioned assignment of the sync block number in the row address, the address can be assigned to all the sync blocks.

The column addresses 0 to 3 of the bank A are assigned ID0 and ID1 shown in FIG. The column addresses 4 to 223 have data 0 to 0, respectively.
109 is assigned. On the other hand, data 110 to 215 are assigned to column addresses 0 to 219 of bank B. Then, the column addresses 220 to 2 of the bank B
23, data 216 and ID2 are assigned.

The column addresses 224 to 224 of bank A
251 and the column addresses 224 to 251 of the bank B
Is written with an error flag resulting from outer code correction. Since one bit is assigned to one error flag, one word can store 16 data error flags. Therefore, data 0 to 1 are stored in the column addresses 224 to 251 of the bank A.
11 is stored in the column address 224 to 251 of the bank B.
Is stored.

SDRAM shown in FIGS. 8 and 9
The assignment of the row address and the column address of 75 is performed by writing the data to the SDRAM 75 after the inner code correction, and performing the outer code correction described later.
It does not change until data is read from the DRAM 75.

Next, the SD by the memory controller 74
The control of the RAM 75 will be described. FIG. 10 is a time chart showing an example of access of the SDRAM 75 during normal speed reproduction. In the figure, segments 0 to 5 indicate areas in the SDRAM 75 provided for each segment, and audios 0 to 3 indicate areas in the SDRAM 75 provided for one error correction block of each audio data. Is shown.

In the SDRAM 75 of FIG. 10A, video data of segments 0 to 5 is supplied and written in the video data writing cycle after the inner code correction. Then, reading and writing for the outer code correction process are performed on the written data by the outer video code decoder 31. Thereafter, reading for outputting the video data is performed based on the reading cycle of the video data in FIG. 10B. As shown in FIG. 10D, writing and reading of the video data to and from the SDRAM 75 are performed for each segment. The audio data is, as shown in FIG. 10C,
One field is set as a write and read cycle.
Then, as shown in FIG. 10E, writing and reading of data to and from the SDRAM 75 are performed for each channel.

As described above, in reproduction at normal speed, (1) writing of video data after inner code correction, (2) reading and writing for outer code correction processing, and (3) output of video data A plurality of types of processing of reading and (4) writing and reading of audio data are performed in parallel. This is because, as described above, the clock rate inside the error correction decoder 9 is set to 46.4 MHz by the rate converter 63 (or 67).
This is realized by making it possible to perform these multiple types of processing in a time-division manner.

Of these processes, the timing of writing the video data after the inner code correction and reading the video data for output depends on the outside. Other processes are controlled by the memory controller 74.

FIG. 11 shows an example of a time division process of writing and reading data in the SDRAM 75. FIG. 11A shows a write cycle of video data and audio data after inner code correction. FIG. 11B
4 shows processing of video data and audio data. 3
If 0 frames / 1 second, one frame is 46.4
It is equivalent to 1,546,872 clock in MHz clock. The time-division processing of the above-described plurality of types of processing is performed on this clock in units of 1008 clocks. 100
Eight clocks constitute one sequence of processing.

In the present invention, this 1008 clock is divided into clocks required for each of the above-described plural types of processing. For example, each of a plurality of types of processing is finely divided into a series of necessary processing units in this processing. This disassembly is performed so that the processes among the plurality of types are substantially equal to each other and with the required maximum number of clocks. This number of clocks is called a slot. The time division processing is performed using this slot as a unit.

The number of clocks that can be divided is different for each of a plurality of types of processing. Therefore, the size of the slot varies depending on the type of processing. For example, as shown in FIG. 11C, the video data output after the inner code and outer code correction processing has 154 clocks as one slot. The reading of audio data for error correction by the outer audio code decoder 32 takes 16 clocks as one.
It is a slot. Writing and reading of video data for error correction by the outer video code decoder 31 are performed with 256 clocks as one slot. Writing of A / V data to the SDRAM 75 after the inner code correction is performed using 582 clocks as one slot. How to determine the number of clocks in the slot for each type of processing will be described later.

All sequences of slots are collected to form one sequence. By repeating this sequence, various processes can be performed in a time-sharing manner. In the example of FIG. 11, 154 clocks of the video data output after the inner code and outer code correction processing are started, and 16 clocks of data reading for audio outer code correction and 256 clocks of read / write for video data outer code correction are performed. , And 582 clocks of data writing after the inner code correction, the slots are arranged in this order to form one sequence. The order of the slots is fixed. This is repeated with these total 1008 clocks as one sequence.

Here, the slot of the video data output processing after the inner code and outer code correction processing is set at the top because
This is because the timing of this processing is determined by a reference frame pulse supplied from the outside. The repeated sequence is reset by this reference frame pulse and starts from the beginning of the frame. That is, the sequence is started in synchronization with the reference frame pulse.

FIG. 11D shows that each process has 1
An example of the number of slots per frame is shown. Video data output after the inner code and outer code correction process requires 1400 slots / frame. 1300 slots / frame are required for reading data for correcting an extra-audio code. Reading and writing for correcting codes outside video data requires 1350 slots / frame. The data writing after the correction of the inner code is 1
534 slots / frame are required.

As described above, one frame includes 1,54 frames.
6,872 clocks. That is, when one sequence is 1008 clocks, one frame is 153 clocks.
Four sequences can be included. Therefore, 1534 slots / frame are provided for each of the plurality of types of processing, and all the processing can be completed.

Since the sequence is repeated and various processes are performed, the number of slots in which various processes can be used in one frame is equal. Therefore, in various processes, the number of slots in one frame is slightly different, so that extra slots are generated. In this extra slot,
No action is taken.

Next, an example of how to determine the number of clocks in one slot will be described using a more specific example. For ease of understanding, FIG. 12 shows an example of the data arrangement in the error correction block of the video data shown in FIG. 2 described above in detail. The data is configured in units of one symbol consisting of 8 bits. In FIG. 12, Sx-Dy represents data of one symbol. The same x indicates that the data is the same sequence in the inner code direction, and the same y indicates that the same sequence is the data in the outer code direction. That is, Sx-D0,
Sx-D1, SxD2,..., Sx-D216 are data of the same sequence in the inner code direction. Similarly, S0-D
y, S1-Dy, S2-Dy,..., S249-Dy
Are data in the same code in the outer code direction.

In the following, “data of the same sequence in the inner code direction” is referred to as “data of the inner code sequence”, and “data of the same sequence in the outer code direction” is referred to as “data of the outer code sequence”. Name.

The address assignment in the SDRAM 75 is as follows.
A matrix is formed by column (row) addresses and row (column) addresses. FIG. 13 shows an example of an address assignment in the SDRAM 75. That is, FIG.
FIG. 1 shows an address space of the SDRAM 75 including these column addresses and row addresses.
2 schematically shows an example of the data arrangement of the error correction block shown in FIG.

As schematically shown in FIG. 13A, SD
The RAM 75 has two areas, that is, a bank A and a bank B, which are switched and used as memory areas. Each of these banks A and B is provided with a 6-bit row address represented by bits '0' to '5'. The SDRAM 75 has a data width of 16 bits, and the 16 bits are defined as one word.
A column address consisting of 256 words is arranged for each row address.

The SDRAM 75 can perform a so-called burst write / burst read, in which a plurality of column addresses are continuously accessed by one designation and writing or reading is continuously performed. The number of words continuously output or input in writing or reading is called a burst length. This burst length is, for example, '
Various settings such as 1 ',' 2 ',' 4 ',' 8 ', and full page are possible. In this example, the burst length is set to '4'.

In this example, data of the same inner code sequence is grouped in the order of the outer code sequence for each number corresponding to the burst length, and is arranged for the same row address. At the same time, the data of the inner code sequence is divided into a first half and a second half, each of which is alternately arranged for bank A and bank B for each row address. Therefore, at the time of writing / reading data in the inner code direction, the column is randomly accessed. When writing / reading data in the outer code direction,
Banks A and B are interleaved and accessed in burst length units.

For one row address, data in the inner code direction for four sequences are collectively allocated for each row address. That is, in the row address starting from the address “0”, the row address “
Data of four series of S0-Dy, S1-Dy, S2-Dy, and S3-Dy is assigned to 0 '. Row address '1' includes S4-Dy, S5-Dy, S6
-Dy and S7-Dy are allocated. Similarly, the row address '2' contains S8-D
Four series data of y, S9-Dy, S10-Dy, and S11-Dy are allocated. In the same manner, data is allocated to each of the four sequences up to the row address '61'.

As shown in FIG. 2B, the inner code data is composed of 250 sync blocks, and the data sequence in the inner code direction is 250 S0 to S249.
is there. Therefore, for one row address,
When the data in the inner code direction is assigned by four sequences, the last two sequences (S248-Dy and S249-Dy) are left. Therefore, the row address '62' contains these S24's.
8-Dy and S249-Dy are allocated, and the remaining two streams are filled with dummy data.

On the other hand, regarding the column address, the data in the inner code direction is the first half and the second half (that is, the first half Sx-D
0 to Sx-D109 and the latter half Sx-D110 to Sx-
216), and the former half and the latter half are exchanged and arranged by bank A and bank B for each row address. That is, for the row address '0', the first half of the data series S0 to S3 in the inner code direction is arranged in the bank A, and the second half is arranged in the bank B. In the next row address “1”, the arrangement is switched between the banks A and B, the latter half of the data series S4 to S7 is arranged in the bank A, and the former half is arranged in the bank B.

FIG. 13B shows an example of the data arrangement for each row address in detail. Here, row addresses '0' to '2' are shown. In a region indicated by one column address having one word, that is, 16 bits, two symbols are arranged as one set because one data of data is composed of eight bits. For convenience, the upper 8 bits of the area indicated by one column address in FIG. 13B are referred to as an upper column, and the lower 8 bits are referred to as a lower column. In the sequence Dy in the outer code direction,
Data in which y is odd is arranged in the upper column, and data in which y is even is arranged in the lower column.

The first four column addresses (column address') of the bank in which the first half of the data sequence in the inner code direction is arranged
In IDs 0 'to' 3 '), IDs for identifying data arranged at the same row address are arranged. This ID
, Data is stored from the column address '4'.

As described above, symbols are arranged collectively in units of burst length. At this time, the sequences are grouped so that the sequence (Dy) in the outer code direction is the same and the sequence (Sx) in the inner code direction is continuous. In this example, since the burst length is 4, four data are collected in each of the upper column and the lower column.

In the four column addresses (column addresses '4' to '7') following the ID, the data in the lower column where x is 0 to 3 and y is 0, that is, data S0-D0, S
1-D0, S2-D0, and S3-D0 are sequentially arranged. In the upper column of the same column address, data in which x is 0 to 3 and y is 1 as in the lower column, that is, S0-
D1, S1-D1, S2-D1, and S3-D1 are arranged in order. Similarly, data sequences in the same outer code direction are grouped for every four column addresses, and data is arranged in the memory space. Note that dummy data is arranged after the column address '224' of each of the banks A and B.

The control of the SDRAM 75 is performed by a command. For example, a predetermined command is input to the SDRAM 75 by a combination of signals supplied to a predetermined command input terminal of the SDRAM 75 and an address input terminal having a 12-bit input terminal in parallel. This command is generated and output by the memory controller 74, and is stored in the SDRAM 75.
Supplied to

In controlling the SDRAM 75, when a command is input, the SDRAM 75, which is a synchronous memory, is used.
There are several restrictions based on the asynchronous properties that have. Writing to the SDRAM 75 or SDRAM 7
It is necessary to take this restriction into account when controlling the readout from block 5 efficiently. Below, this SD
The control and restrictions of the RAM 75 will be briefly described.

In using the SDRAM 75, first, a mode register is set. By setting this mode register, the operation mode of SDRAM 75 is set. The mode register is set by a mode register setting command. By the mode register, CA
S latency, lap type, and burst length are set. After setting the mode register, the next command cannot be input until 20 ns or more has elapsed.

The CAS latency is the most important of these parameters, and sets the latency (number of clocks) from command input to data read. That is, after the command is input, data reading is started after waiting for the CAS latency. The CAS latency is set by selecting any value from, for example, '1', '2', or '3'. In this example, the CAS latency is set to '2'.

The wrap type specifies the order in which burst data addresses are incremented when performing burst write / burst read. Either sequential or interleaved can be selected. The burst length is set by selecting any one of '1', '2', '4', '8', or a full page. In this example, the burst length is set to '4'.

In the SDRAM 75, a predetermined row address of the target bank is activated by an active command, and a write / read is enabled. Then, a data write / data read command for the row address of the activated bank is input, data is input, and data writing / reading for the target row address of the target bank is performed. After writing / reading data, it is necessary to perform precharge. By executing the write / read command with auto-precharge, pre-charge can be automatically performed after a predetermined period of time after data is written / read.

The interval between write commands is one clock. That is, the write command can be input without any limitation for each clock. Similarly, the interval between read commands is one clock, and a read command can be input without limitation at every clock. However, since there is a CAS latency at the time of reading, there is a delay corresponding to the CAS latency from when a read command is input to when data is actually output. In this example in which the CAS latency is designated as "2", data is output two clocks after the input of the read command.

The write command and the read command can be interrupted by different write commands or different read commands. This allows
A column address for writing or reading can be specified in units of one clock.

In the SDRAM 75, as a restriction based on the asynchronous characteristic, a predetermined interval is required between each command input and operation. Violation of this restriction causes the SDRAM 75 to malfunction.
FIG. 14 shows a list of examples of the constraint conditions. The numerical value shown at the top is the cycle that is the minimum interval of the operation of the SDRAM 75. Here, the cycle is 13 ns
An example in which the SDRAM is operated with a clock of 20 ns will be described.

The interval from the refresh command to the next refresh command or active command is
Interval t _RC, which is a minimum of 1 corresponding to 7 clocks
30 ns is required. The interval from the active command to the precharge command is called an interval t _RAS and requires a minimum of 91 ns. This corresponds to five clocks. Conversely, the interval between the precharge command and the active command is called an interval t _RP and requires 39 ns. This corresponds to two clocks. An interval between the active command and the data read / data write command is referred to as an interval t _RCD and requires 39 ns corresponding to two clocks. The interval between each active command when activating one bank after activating one bank is referred to as the interval t _RRD and
ns required. This corresponds to two clocks.

The interval between the data input and the precharge command is called interval t _DPL . When data is written by a write command with auto-precharge and auto-precharge is specified, the interval between the last data input and the next active command is called an interval t _DAL . The interval t _DPL and the interval t _DAL depend on the CAS latency. At interval t _DPL , CA
When the S latency is 3, one clock + 13 ns is required. This corresponds to two clocks. When the CAS latency is 1 or 2, 19.5 ns corresponding to one clock is required. If the CAS latency is 3 at the interval t _DAL , 2 clocks + 3
9 ns is required. This corresponds to four clocks. When the CAS latency is 1 or 2, 1 clock +
39 ns is required. This corresponds to three clocks.

Next, control of writing / reading data to / from the SDRAM 75 in consideration of such restrictions will be described with reference to FIGS. 15 and 16 and FIG.

First, the inner code sequence will be described. In the writing / reading of the inner code sequence, there are a sequence starting from bank A and a sequence starting from bank B. This is because the first half and the second half of the inner code direction are alternately arranged for banks A and B for each row address. FIG. 15A shows the writing of the inner code sequence starting from bank A, and FIG. Similarly, FIG. 15C shows the writing of the inner code sequence starting from bank B, and FIG.
D indicates a read initiated from bank B. 15 and FIG. 16 to be described later, the upper part shows a control command and the lower part shows data.

In FIG. 15A, an active command RAx is supplied to activate a predetermined row address x of bank A. With this command RAx, the row address in the x-th row is activated. As shown in FIG. 13 described above, the first data (S0-D
0) is written to an address represented by a row address '0' and a column address '1'. Therefore, here, x is set to "0", and the row address "0" is activated. Interval t from this active command RAx
After the elapse of _RCD (that is, two clocks), a write command is executed, and a column address for writing data is specified.

As described above, in the SDRAM 75, a write command can be input for each clock without any limitation. By utilizing this, when specifying a column address, a write command is interrupted one by one every clock. As a result, the column address becomes CA0, CA1, C
A2,..., CA55 are specified continuously in word units. Following the address CA55,
Writing to the column address CAdu, which is an empty area, is designated, and four words of dummy data are written.
This writing of the dummy data is designated because precharging is performed when writing to bank B is performed following bank A.

This CA, which is the last address of bank A,
When specifying dum, the column address CAdu is specified by a write command with auto-precharge. In this example in which the CAS latency is "2", the precharge is automatically started one clock after the command CAdu is input.

Each column address is specified so that the same inner code sequence is successively written and the outer code sequence is written in the data order. That is, FIG.
, The data is arranged and arranged in such a manner that the data in the burst direction is the same as the row address, the sequence (Dy) in the outer code direction is the same, and the sequence (Sx) in the inner code direction is continuous. Therefore, the column address is incremented in units of burst length for the first specified column address and is sequentially specified. For example, when the column address CA0 is specified, the column address “4” is specified, and the address CA1 is specified.
Specifies the column address '8'.

By specifying the column address in this manner, Sx-D0, Sx-D1, Sx-D2,.
.., Sx-D108, Sx-D109, etc.
Data can be continuously written to the row address RAx.

When the column address CAdu is specified, an active command RBx for activating the bank B is input at the same row address at intervals of two clocks. Thereafter, an address is specified by the same control as that for writing to the bank A, and data is written. After the final data corresponding to the row address, a free area is specified by the column address CBdu, and four words of dummy data are continuously written.

When the writing to bank B is completed, the starting column address is shifted to the next one from bank A again.
Similar control is performed. For example, in the above description, the column address '4' is set as the first address, and here, the adjacent column address '5' is set as the first address. This control is repeated for the burst length, that is, four times. Thus, for example, the data writing to the row address “0” shown in FIG. 13 is completed.

When the writing of the inner code sequence started from bank A ends, the row address is incremented by one, and the writing of the inner code sequence started from bank B is performed as shown in FIG. 15C. The writing of the inner code sequence started from bank B is the same as the writing started from bank A in FIG. 15A, except that the address designation is switched between bank A and bank B. Omitted.

In this way, the control shown in FIGS. 15A and 15C is alternately performed while sequentially incrementing the row address. By performing such control, data is written in the arrangement shown in FIGS. 13A and 13B described above according to the order of the inner code sequence. When the writing to the row address '62' is completed, the writing of all data is completed.

The reading of the inner code sequence is performed under substantially the same control as the writing. That is, as shown in FIG. 15B, a predetermined row address of bank A is activated by an active command RAx, and the interval t
After the elapse of the _RCD , a read command is input, and a column address is specified. Data reading is performed in units of burst length, and reading of bank A ends, and precharge is executed. Then, after the interval t _RP , the bank B is activated, and reading from the bank B is performed. After repeating this for the burst length, the row address is incremented, and the reading of the inner code sequence from the bank B shown in FIG. 15D is started. Thus, the control shown in FIGS. 15B and 15D is alternately performed while sequentially incrementing the row address.

In the case of reading, due to the presence of the CAS latency, the data is read with a delay of the CAS latency with respect to the input of the active command.
In the example shown in FIG. 15B, an active command R for activating a predetermined row address x of bank A is set.
Ax is input, a read command is input after an interval t _RCD, that is, two clocks later, and the column address CA0 is specified. In the reading of data from the column address CA0, the data is read two clocks after the designation of the column address CA0 by the read command in this example in which the CAS latency is set to "2" in this example. .

Also, at the time of reading, a dummy read address is specified corresponding to the precharge when switching banks. At the time of reading, unlike data writing, access to the dummy data does not cause data destruction or the like. Therefore, dummy data for three column addresses shorter than the burst length is read.

By performing the control at the time of reading in this way, the data written as shown in FIG. 13 can be sequentially read in the inner code direction. As described above, with regard to the inner code sequence, only eight clocks required for writing dummy data when writing data, and only six clocks required for reading dummy data when reading data, the clock is not wasted and efficient. is there.

Next, the outer code sequence will be described with reference to FIG. Regarding the writing / reading of the outer code sequence, there are a sequence started from bank A and a sequence started from bank B. The sequence starting from bank A is for the first half of the inner code sequence, and the sequence starting from bank B is for the second half. FIG.
16A shows the writing of the inner code sequence started from the bank A, and FIG. Similarly, FIG. 16C shows the writing of the inner code sequence starting from bank B, and FIG. 16D shows the reading starting from bank B.

In the above inner code direction, data was written / read in the horizontal direction with respect to the address space shown in FIG. 13, that is, in the column direction. On the other hand, in this outer code sequence, data is written / read in the address space in the vertical direction, that is, in the row direction. By incrementing the row address and alternately switching between bank A and bank B to specify the address while interleaving, data writing / reading is performed so that the inner code sequence is continuous for each same outer code sequence. It can be performed.

First, writing will be described. As shown in FIG. 13, the data to be written first (S0
−D0) is arranged at the row address “0” and the column address “1” of the bank A. Thus, as shown in FIG. 16A, writing starts from bank A, and
An active command RA0 is input in order to activate the row address '0'. Next, a column address is specified. After a lapse of an interval t _RCD (ie, two clocks) from the active command RA0, a write command with an auto-precharge is input, and a column address CAy for writing data is designated. With this write command, data is written in burst length units. Also, this SDRAM 75
Since one word is made up of 16 bits, a symbol consisting of 8 bits is written every two symbols.

For example, when y = 1, the column address'
From 1 'to' 4 ', a set of data written to the same column address, that is, data S0-D0 and S0-D
1, S1-D0 and S1-D1, S2-D0 and S2-D
1, and S3-D0 and S3-D1 are continuously written. When this writing is completed, precharge is automatically started.

The address to which the next data is to be written is the next higher row address in bank B, as shown in FIG. Then, the bank is switched from bank A to bank B. While writing to bank A is being performed, row address '1' of bank B is
Is activated. The active command RB1 is input two clocks after the input of the write command with auto-precharge specifying the column address CAy described above.

After a lapse of an interval t _RCD (two clocks) from the input of the active command RB1, a write command with auto-precharge is input, and a column address CBy for writing data is specified. Here, the column address “0” is specified. And
As in the case of the above-described bank A, 4 data × 2 (S4-D0 and S4-D
1, S5-D0 and S5-D1, S6-D0 and S6-D
1, S7-D0 and S7-D1) are written, and after the writing, the precharge is automatically executed.

Also, while data is being written to bank B, active command RA2 of bank A is
Is input, and the next row address '2' of bank A is activated. This active command RA2 has an interval t from the data input previously made to bank A (in the above example, from the clock at which S3-D0 was input).
_DAL is input after waiting for three clocks. Then, two clocks after the active command RA2, a write command with auto-precharge is input, and the column address CAy of the bank A is specified. In this example, the column address “0” is specified.

As described above, the row address is incremented, and the address is specified while the bank A and the bank B are alternately switched. The column address is fixedly designated until writing to the row address '62'. Since the burst length is 4 and the number of data in the outer code direction is 250, there is a surplus of 2 data at the end of writing. Here, two pieces of dummy data are written.

When the writing to the row address '62' is completed, the row address is returned to the address '0', the column address CAy is incremented, and the writing to the next column address is started. This is repeated,
Row address '62' and column address '223'
When writing is performed to the address specified by, all the writing in the first half of the inner code sequence is completed. Then, writing of the latter half of the inner code sequence is started next.
Writing in the latter half of this inner code sequence is started from bank B.

The writing started from the bank B is also
The writing is performed in the same manner as the writing started from the bank A described above. As shown in FIG. 16C, an active command RB0 for activating bank B is input. Then, an interval t from this active command RB0
_After waiting only for _RCD, a write command with auto precharge is input, and the column address CBy is specified. Writing starting from bank B is performed at column address'
Since it starts from 0, y = 0 and the column address '0' is specified. Then, while the row address is incremented and the bank B and the bank A are alternately switched, the column address is fixed to these banks A and B, and the address is designated.
Data of the same inner code sequence is written in units of burst length, following the outer code sequence.

The reading of the outer code sequence is performed under substantially the same control as the writing. That is, as for the reading started from the bank A, as shown in FIG. 16B, the row address '0' of the bank A is activated by the active command RA0, and the read command with auto-precharge is input after the elapse of the interval t _RCD. And
A column address CAy is specified, and data is read from the specified column address CAy in burst length units. An active command RB1 is input two clocks after the read command, the bank B is activated, and the row address is incremented. A read command with auto-precharge is input after an elapse of an interval t _RCD from the active command RB1, a column address CBy is designated, and the designated column address C
Data is read from By in burst length units.

As described above, at the time of reading, the row address is incremented and the bank A and the bank B are read.
While alternately switching between these, the corresponding column address is fixedly designated for each of the banks A and B, and the address is designated, so that the data of the same inner code sequence continues in the outer code direction. , And are read out in burst length units. When the reading up to the row address '62' is completed, the column address is incremented, and the reading is similarly started from the row address '0'. When all the readings started from the bank A are completed, reading from the bank B shown in FIG. 16D is started. Reading from the bank B is performed under substantially the same control as the reading started from the bank A.

At the time of reading, due to the limitation of CAS latency, a CA is not applied until a read command is input.
Reading starts after the clock specified by the S latency has elapsed. Therefore, in this example, data reading is started two clocks after the column address CAy is specified by the read command.

When the CAS latency is 2, the auto-precharge by the write command with the auto-precharge is started one clock before the last output burst data. For example, the auto precharge by the first write command with auto precharge (CAy) in FIG. 16A is started at the data output timing of S2. In the same bank, from the start of the pre-jersey to the input of the active command,
An interval t _RP (for two clocks) is required. After the elapse of these two clocks, the next active command RA1 is input.

As described above, according to this embodiment,
With respect to the outer code sequence, only two clocks required for writing the dummy data when writing data and two clocks required for reading the dummy data when reading the data are efficient because the clock is not wasted.

As described above, in this example, the writing and reading of the data of the inner code sequence are made most efficient when both are performed in units of one sync block. As shown in FIG.
It can be seen that two clocks are required. Similarly, the writing and reading of the outer code sequence data are made most efficient when both data of the outer code sequence data shown in FIG. 12 are used as a unit. As shown in FIG. 7, it can be understood that 254 clocks are required for writing and 256 clocks are required for reading. The number of clocks required for writing and reading differs from each other because reading is started after a clock specified by the CAS latency has elapsed from the input of the read command due to the limitation of CAS latency.

If the processing of both the inner code sequence and the outer code sequence is further decomposed, the processing method will be different, and the data access efficiency in the SDRAM 75 will be reduced. Therefore, the decomposition of each process is performed so far, and the number of clocks per slot is determined based on the result of the decomposition.

For the above four types of processing, ie, video data output after inner code and outer code correction processing, read / write for video data outer code correction, data write after inner code correction, and audio outer code correction. , The number of clocks for one slot is obtained. The number of clocks in one slot is determined such that the number of slots required for one frame is substantially equal for various processes. Thus, various processes can be easily performed.

In the video data output processing after the inner code and outer code correction processing, data is read from SDRAM 75 in the inner code sequence direction. As shown in FIG. 15, reading of the inner code sequence requires 122 clocks. At this time, the error flag is read together with the video data. To read this error flag, 3
Two clocks are required. Therefore, in this process, as shown in FIG.
32 clocks = 154 clocks are allocated, and this is one slot in this processing.

One frame is composed of six segments.
One ECC decoder IC 60 processes one error correction block per segment. One error correction block is composed of 226 sync blocks. Therefore,
The number of slots per frame is 226 sync blocks / segment × 6 segments / frame = 1356 sync blocks / frame. As described above, in the writing / reading of the inner code sequence, one sync block is one.
Since it is a slot, it is 1356 slots / frame. Actually, because other details are added,
As shown in FIG. 11, 1400 slots / frame are required.

In the read / write processing for correcting the outer code of the video data, the SDRAM 75 is accessed in the outer code sequence direction. As shown in FIG. 16, in the access of the outer code sequence, 254 clocks are used for writing,
At the time of reading, 256 clocks are required, and the required number of clocks differs between the two. However, since the slot length needs to be fixed,
As shown in FIG. 11, one slot has 256 clocks.

As can be seen from FIG.
In 75 address assignments, two data are assigned to one word. Therefore, if video data is written / read in the outer code sequence direction according to the chart of FIG. 16, two slots of the outer code sequence can be written / read by processing for one slot. FIG.
As can be seen from the above, in one azimuth, there are 217 outer code sequences per segment. Therefore, the number of slots per frame is 217 outer code sequences / segment / 2 data / word × 2 (write / read) × 6
Segment / frame = 1302 outer code sequence / frame. Since one outer code sequence is one slot, 130
2 slots / frame. Actually, since detailed processing such as processing of an error flag is added, 1350 slots / frame are required as shown in FIG.

Similarly, in the data reading for correcting the extra-audio code, in this example, as shown in FIG. 11, one slot is set to 16 clocks. Also, 130
0 slots / 1 frame is required.

In the data write processing after the inner code correction,
Data is written to SDRAM 75 in the inner code sequence direction. This process requires 122 clocks as shown in FIG.

In the data write processing after the inner code correction, the data reproduced from the magnetic tape 6 and subjected to the predetermined processing is subjected to the inner code correction, and the inner code corrected data is transferred to the SDRAM 75. This is the writing process. Therefore, it is affected by the jitter of the tape running speed and the rotating speed of the rotating drum. As described above, in order to absorb the jitter, the buffering process by the buffers (RAM) provided in the rate converters 63 and 67 is performed. Therefore, data writing to SDRAM 75 is performed asynchronously. That is, it cannot be specified when data is written to the SDRAM 75.

On the other hand, in the buffering process for absorbing jitter, for example, when data for 122 clocks is written to the SDRAM 75, data for one sync block is swept out of the buffer. This buffer needs to be controlled so that it never overflows with possible jitter. For this purpose, for example, in this embodiment, processing is performed at a rate of 1/2 of the whole. Based on the above idea, the number of slots required for writing data after correcting the inner code is 1546872 clocks / frame ÷ 122 clocks / slot × １ ／ (ratio) = 6340 slots / frame when 122 clocks are defined as one slot. It is said. By allocating 6,340 slots per frame, the data after the inner code correction can be written to the SDRAM 75 without omission.

As described above, in the present invention, one sequence formed by collecting all types of slots is repeated. Therefore, if 122 clocks are set to one slot in the writing process after the inner code correction, 6340 slots / frame are required, and consequently, 6340 sequences / frame are required. However, other processes only require at most about 1400 slots / frame, so that a useless sequence occurs.

Therefore, in this embodiment, a plurality of data for one sync block in the data write processing after the inner code correction is collected so that the number of slots per frame is substantially equal to that of other processing. Slots. In this example, four sync blocks are grouped into one slot. That is, as shown in FIG. 11, the data write processing after the inner code correction is 582
Clock / slot is used, and processing is concentrated on this one slot. In one frame, 1534 slots /
A frame is needed.

Note that the processing for collecting data for four sync blocks is performed, for example, in the rate converters 63 and 6 described above.
7, R provided as a buffer for jitter absorption
AM has a capacity of three sync blocks, and is performed in conjunction with jitter absorption processing. By the inner code decoder 69, 4
The output from this buffer is controlled so that the data for the sync block is output collectively.

By deciding slots for various processes in this manner, one sequence is set to 1008 clocks as shown in FIG. When a system clock of 46.4 MHz is used, 1534 sequences / frame are set, and all processing can be completed.

Next, a modification of this embodiment will be described. This modification is an example in the case of high-speed reproduction. High-speed reproduction is performed by running the magnetic tape 6 at high speed, and the magnetic head 7 traces the track while obliquely crossing the track. Therefore, data can be reproduced in sync block units, but one track of data cannot be reproduced, so that one error correction block is not formed. Therefore, there is no need to perform outer code correction.

Further, by performing high-speed reproduction, the relative speed between the data recorded on the magnetic tape 6 and the magnetic head 7 changes, and the rate of data reproduced from the magnetic tape 6 increases. Therefore, during high-speed reproduction, the SDRAM 75
In some cases, the data write processing after the inner code correction for the FIG. 17 is a time chart showing an example of access of the SDRAM 75 during high-speed reproduction. FIG. 17A
FIG. 17B and FIG. 17B show the cycles of the data write processing after the inner code correction and the read processing for outputting the video data, respectively. As in this example, at the time of high-speed reproduction, data write processing of 6 segments or more may occur in one frame. In the example of FIG. 17C, writing of 7 segments has occurred.

In this modification, there is no need for high-speed playback,
The slot of the read / write processing for correcting the outer code of the video data is diverted to the data write processing after the correction of the inner code. FIG. 18 shows the SDR at the time of high-speed playback according to this modification.
6 is a time chart illustrating an example of an AM access. FIG. 18A shows a write cycle of video data and audio data after inner code correction. FIG. 18B shows processing of video data and audio data. FIG. 18C
As shown in the figure, a slot for data write processing (256 clocks) after inner code correction during normal-speed reproduction and a slot for read / write processing for outer code correction for video data (582 clocks) are synthesized. This is a new slot for 838 clocks. This new slot is used as a slot for data write processing after inner code correction during high-speed reproduction. Since the number of clocks is increased, the increased processing can be sufficiently performed by high-speed reproduction.

In this case, the processing of video data output after the inner code and outer code correction processing and the data reading for audio outer code correction are not related to high-speed reproduction, and as shown in FIG. The processing is performed in exactly the same way as during normal speed reproduction. As described above, by using the present invention, even if the reproduction mode is changed, it is possible to cope with the processing only by changing only the slot affected by the change.

[0152]

As described above, according to the present invention, one SDRAM connected to an ECC decoder IC
Is used in time division processing to write data after correcting the inner code, read / write processing for correcting the outer code of video data,
A plurality of types of processing are performed, such as data read processing for audio outer code correction, and video data output processing after inner code and outer code correction. Further, each type of processing is clearly demarcated as a slot.
Therefore, there is an effect that design and verification can be performed for each type of processing.

When a plurality of types of processes are performed in a time-division manner by one SDRAM, if the processes are performed asynchronously, the respective processing times are related to each other. Every case must be envisaged to guarantee. The number of simulations for that purpose is enormous, guarantee is difficult, and the reliability as a product is reduced. Therefore, the design becomes difficult and the circuit scale also increases.

In the present invention, since various processes are fixedly performed on a slot basis, time-division processes can be performed synchronously. Therefore, it is only necessary to guarantee that the processing is completed within a given slot for each processing, so that a simulation for guaranteeing reliability can be simplified and the risk of bugs is reduced. Therefore, there is an effect that the reliability of the product is improved and the circuit scale can be reduced.

Further, when the processing is performed asynchronously, it is difficult to know where the various processing is performed, and it becomes very difficult to verify the ECC decoder IC after completion. By using the present invention, full synchronization in a frame unit and full synchronization in a sequence are realized,
The timing at which the various processes are performed is fixed, and the verification can be performed very easily.

Furthermore, for example, at the time of high-speed reproduction, the relative speed between the rotating drum (magnetic head) and the magnetic tape changes, and data writing to the SDRAM after correcting the inner code may increase. According to the modified example of the present invention, it is not necessary at the time of high-speed reproduction, for example, the slot of the read / write processing for the correction of the outer code of the video data is simply changed to the slot of the data write processing after the correction of the inner code, thereby increasing the processing. There is an effect that can be dealt with. Also, at that time, there is no effect on other irrelevant processing slots, and there is no need to change them. That is, there is a public service A that can easily cope with a difference in processing depending on the mode of the video tape recorder simply by diverting the slot.

[Brief description of the drawings]

FIG. 1 shows a digital video recording / video to which the present invention is applied.
It is a block diagram which shows an example of a structure of a reproducing device schematically.

FIG. 2 is a schematic diagram schematically illustrating an example of a configuration of an error correction block.

FIG. 3 is a schematic diagram schematically illustrating an example of a configuration of an error correction block.

FIG. 4 is a schematic diagram illustrating a configuration of one sync block in an error correction block.

FIG. 5 is a block diagram illustrating an example of a configuration of an ECC decoder IC.

FIG. 6 is a schematic diagram illustrating an example of a data configuration in one packet.

FIG. 7 is a schematic diagram illustrating an example of a format when reproduction data for one sync block is written to an SDRAM;

FIG. 8 is a schematic diagram showing row address assignment in an SDRAM.

FIG. 9 is a schematic diagram showing column address assignment in an SDRAM.

FIG. 10 is a time chart showing an example of SDRAM access during normal speed reproduction.

FIG. 11 is a time chart showing an example of a time division process of writing and reading data in the SDRAM.

FIG. 12 is a schematic diagram illustrating an example of a data array in an error correction block of video data in detail.

FIG. 13 is a schematic diagram illustrating an example of an address assignment in an SDRAM.

FIG. 14 is a schematic diagram showing an example of a list of constraints on the SDRAM;

FIG. 15 is a timing chart for explaining writing / reading of an inner code sequence.

FIG. 16 is a timing chart for explaining writing / reading of an outer code sequence.

FIG. 17 is a time chart showing an example of SDRAM access at the time of high-speed reproduction.

FIG. 18 is a time chart for explaining that a slot is diverted.

FIG. 19 is a block diagram showing an example of a configuration of a digital recording / reproducing apparatus according to a conventional technique using encoding by a product code.

[Explanation of symbols]

6 magnetic tape, 7 magnetic head for reproduction, 9
... Inner / outer code decoder, 10 ... RAM, 6
0 ... ECC decoder IC, 63, 67 ... Rate converter, 69 ... Inner code decoder, 74 ... Memory controller, 75 ... SDRAM, 76 ... Video data outer code decoder

Continued on the front page (51) Int.Cl. ⁶ Identification code FI G11B 20/18 544 G11B 20/18 544Z H04N 5/94 H04N 5/94 Z

Claims (11)

[Claims] 1. An error correction apparatus for decoding error-corrected data using a product code, comprising: an inner code decoder for performing inner code correction; and an outer code correction after the inner code correction is performed. An outer code decoder, and a memory for storing data corrected by the inner code decoder and data corrected by the outer code, wherein the same type of processing is defined by a reference clock The sequence is decomposed into slots, and one sequence is constituted by a plurality of the slots of the same type of processing, and the one sequence is
An error correction device, wherein the error correction is performed by repeating a predetermined number of times during a frame or one field. 2. The error correction device according to claim 1, wherein the same type of processing includes data writing processing after the inner code correction to the memory, and data for the outer code correction of video data to the memory. An error correction device for reading and writing data from the memory and reading data from the memory for data output. 3. The error correction device according to claim 2, wherein the same type of processing further includes a process of reading data for correcting the outer code of the audio data from the memory. Error correction device. 4. The error correction device according to claim 1, wherein the first sequence of one frame period is started in synchronization with a reference frame pulse. 5. The error correction device according to claim 1, wherein the order of the slots in one sequence is fixed. 6. The error correction apparatus according to claim 2, wherein reading and writing of the data for the outer code correction of the video data to the slot and the slot of the data write processing after the inner code correction to the memory are performed. An error correction apparatus characterized in that the slot for processing is arranged adjacent to the slot in the sequence. 7. The error correction device according to claim 6, wherein when the outer code correction is not required, the slot for reading and writing data for the outer code correction of the video data to the memory is set to the slot. An error correction apparatus, wherein the error correction device is diverted as the slot in data writing processing after the inner code correction to the memory. 8. The error correction device according to claim 2, further comprising a buffer in a preceding stage of the inner code decoder, wherein the data is written from the buffer to the memory in the slot of the data write processing after the inner code correction. An error correction device which controls so as to output the error correction signal. 9. A digital signal reproducing apparatus using an error correction device for decoding data subjected to error correction coding using a product code, wherein an inner code decoder for performing inner code correction and said inner code correction are performed. An outer code decoder for performing an outer code correction after the correction, and a memory for storing data subjected to the error correction by the inner code decoder and data subjected to the error correction by the outer code. Is decomposed into slots defined by a reference clock, and one slot is composed of a plurality of the slots of the same type of processing, and the one sequence is
A digital signal reproducing apparatus comprising: an error correction device that performs an error correction process by repeating a predetermined number of times during a frame or one field. 10. An error correction method for decoding error-correction-encoded data using a product code, comprising: an inner code decoding step for performing an inner code correction; and an outer code correction after the inner code correction is performed. And a memory for storing data on which error correction has been performed by the inner code decoder and data on which error correction has been performed by the outer code. Is decomposed into slots defined by the following, and one sequence is constituted by the plurality of slots of the same type of processing, and the one sequence is
An error correction method characterized by performing an error correction process by repeating a predetermined number of times in a frame or one field period. 11. A digital signal reproducing method using an error correction method for decoding data subjected to error correction coding using a product code, wherein: a step of decoding an inner code for correcting an inner code; An outer code decoding step of performing an outer code correction after being performed, and a memory for storing the data corrected by the inner code decoder and the data corrected by the outer code. The same type of processing is decomposed into slots defined by a reference clock, and a plurality of the slots of the same type of processing constitute one sequence, and the one sequence is
A digital signal reproducing method characterized by using an error correction method of repeating an error correction process a predetermined number of times during a frame or one field.