JP4257656B2 - Audio data processing device - Google Patents

Description

The present invention relates to audio data that is encoded by shuffling audio data arranged in the time axis direction according to a predetermined rule, rearranging the audio data for each group, and adding an error correction code to the audio data rearranged for each group. The present invention relates to a processing apparatus.
The present invention also relates to an audio data processing apparatus for performing error correction decoding on data obtained by shuffling audio data arranged in the time axis direction according to a predetermined rule and performing error correction decoding to decode the audio data in the original arrangement.

  In order to improve the correction capability for burst errors during transfer of digital data, a method is widely used in which burst errors are dispersed by shuffling symbols and converted into average errors. FIG. 11 is an explanatory diagram showing a tape format of a DV system digital VTR. In the case of the NTSC system (525-60 system), 10 tracks (numbers 0 to 9 in FIG. 11) are formed per frame. As shown in FIG. 12, one track is composed of sectors of audio, video, and last subcode from the first ITI. The audio sector is indicated by hatching in FIG. 11, and the audio data of channel CH1 is arranged in the audio sector of the first half of one frame, and the audio data of channel CH2 is arranged in the audio sector of the second half of the frame.

  As shown in FIG. 13, the audio sector of each track is roughly 90 bytes (byte position number = 0-89) / sync block (Sync block) × 17 sync blocks (sync block number (sync block number) = 0 to 16), and one word of audio data is 2 bytes, and byte position number on this audio sector = 10 to 81 (72 bytes) × sync block number = 2 to 10 (9 sync blocks) (72 × 9 = 648 bytes = 324 words). This audio data (and audio auxiliary data) has an outer code (outer parity) added in the vertical direction and an inner code (inner parity) added in the horizontal direction. It is error correction coded.

Furthermore, audio data (n + 1 word: n = 0 to 1619) for one channel of one frame is shuffled for each word (2 bytes) and then distributed and arranged in five tracks of audio sectors. The audio data for one frame is shuffled in units of frames for each of CH1 and CH2, and the shuffle pattern of the 525-60 scheme is expressed by the following formula.
Track number CH1: (INT (n / 3) + 2x (n mod 3)) mod 5
Track number CH2: (INT (n / 3) + 2x (n mod 3)) mod 5 + 5
Sync block number: 2 + 3 x (n mod 3) + INT ((n mod 45) / 15)
Byte position number of upper byte: 2 x lNT (n / 45) + 10
Byte position number of lower byte: 2 x lNT (n / 45) + 11
This formula defines where the nth word is placed in the frame. Here, one word is 2 bytes, and the positions of the upper byte and the lower byte in the word are also defined.

  The audio data of 1CH for one frame differs depending on the sampling frequency fs, but is 1620 when fs = 48 kHz. Then, as shown in FIG. 14, the words D0 to D1619 are shuffled for each word (every 2 bytes) and then distributed and arranged in 5 tracks. FIG. 15 shows the structure of the sync block of sync block number = 2 shown in FIG. 13, and the shuffled audio data (first word) is SYNC, ID, AUX blocks and error correction code (inner parity). In addition, a sync block structure is configured.

  The conventional audio processing during recording (and during transmission) will be described with reference to FIG. The audio signal input via the A / D converter 1a, the buffer (input buffer) 2 and the DSP 3 in the path (4) (indicated by circled numbers in FIG. The data is stored in the memory (MEM) 4 and shuffled, and then the outer code correction circuit (OECC) 5 adds an outer code (outer parity) to the data on the memory 4. When recording on the tape T, an inner code (inner parity) is added while reading data on the memory 4 by the inner code correction circuit (IECC) 6 through a path (6) -a, and a recording signal processing circuit SYNC and parity are added via 7a to form a sync block structure as shown in FIG. When transmitting to an external device via the digital I / F (1394 I / F) 8, the path (6) -b is a part of the sync block shown in FIG. Only the transmission packet) is transmitted. This part is 80 bytes, and the audio data is 72 bytes. In the above-described shuffle formula, the byte position number starts at the beginning of the sync block, so the main data is arranged at byte position numbers = 10 to 81.

  Next, audio processing at the time of reproduction (and reception) will be described with reference to FIG. (1) (indicated by circled numbers in FIG. 6; the same applies hereinafter) -a shows the flow of processing when reproducing from the tape T, and (1) -b shows digital I / F (1394 I / F from an external device). ) 8 shows the flow of processing in the case of reception via 8, and in either case, the internal code correction processing (IECC) 6 is performed via the system bus 9 and stored in the memory 4. Only 80 bytes of the transmission packet are stored in the memory 4. Since the audio data constitutes a product code, the outer code correction circuit (OECC) 5 performs error correction processing on the audio data in the memory 4. An outer code correction circuit (OECC) 5 is one of the blocks that accesses the memory 4 on the bus 9 and occupies the bus 9 for a certain period of time. Since the signal processing block, the subcode signal processing block, and the like access the memory 4 via the bus 9, it is necessary to arbitrate each access.

  The DSP 3 performs audio reproduction, and the DSP 3 sequentially reads words from the memory 4 via the path (2), and sends them to the D / A converter 1b via the buffer (output buffer) 2 via the path (3). Reproduce. Since the audio data on the memory 4 is shuffled, the DSP 3 needs to sequentially read from the memory 4 word by word while releasing the shuffle.

  Here, the shuffle process is a process of rearranging the codewords according to a predetermined rule, and there are various variations in the unit of rearrangement, but it is often performed in units of words constituting the data. Here, the word means one meaningful data or a combination of a plurality of these, and is often 1 byte to several bytes.

  On the other hand, in recent multimedia signal processing, a very wide bit width such as 128 bits or 256 bits is often used as a system data bus in order to realize more sophisticated processing. The memory connected to these buses stores 16 bytes of data for one address in the case of a 128-bit bus.

  Here, assuming that the shuffle process is performed in units of 1 byte, the next data of a certain data is generally stored at another address depending on the distance of the shuffle. Therefore, in order to access 1-byte data in order, it is necessary to specify and access a new address for each data. In addition, even though 16 bytes of data can be handled in one access, there is only 1 byte of valid data, and the remaining 15 bytes of access are wasted, consuming power and bandwidth. Become.

  Such an access is a random access operation to the memory, but if the system is a unified memory architecture, many blocks will try to access a single memory, so this many accesses. When necessary, it is very disadvantageous in obtaining the right to use the bus. In addition, it is very inefficient that only one byte is valid for each access even though a large number of clocks are consumed from when the memory access command is issued until data can actually be accessed. In addition, if these operations are performed by a CPU or DSP in charge of signal processing, the processing is waited for each access, and therefore the program cannot be executed efficiently.

  FIG. 16 shows an example of a system in which one memory (MEM) is shared by a plurality of blocks. One memory is under the control of the memory controller (MEMCTL), and a plurality of blocks issue an access request (REQ) to the memory controller. The memory controller has a function as an arbiter, appropriately determines the priority of each block, and notifies access permission (ACK) to a specific block. The block that has received the ACK acquires the right to use the bus and can perform a memory read or write operation.

  Next, a case where a certain block requires data access (read or write) of 4 words D0 to D3 will be described with reference to FIGS. FIG. 17 shows an example in which 4 words D0 to D3 are continuously accessed by burst transfer. In the time a from the issuance of REQ to the acquisition of the right to use the bus, the right to use the bus can be immediately obtained from the issuance of the REQ. In case it is minimized. If not immediately available, time a extends to the maximum waiting time. Once acquired, the four words D0 to D3 can be accessed continuously, which is efficient. In the case where 4 words D0 to D3 are continuously stored in the memory, or in the case of a memory that can be randomly accessed even if it is scattered, it can be accessed in this way.

  FIG. 18 shows an example in which 4 words D0 to D3 are individually transferred one word at a time. In the case of a memory in which 4 words D0 to D3 are arranged separately and there is a penalty for random access such as a DRAM. Times a, b, and c for obtaining the words D0 to D3 are extended. The time a is a case where the right to use the bus can be obtained immediately after issuing the REQ as shown in FIG. 17, and the REQ for the next word access can be issued after the ACK is received, but the REQ as shown in the time b. After the issuance, if another block acquires the usage right first, the ACK is not returned until the block acquires the usage right again by releasing the bus, so the processing is delayed. Since this delay depends on the number of blocks to be interrupted and the bus occupation time of those blocks, it is not constant like the times b and c. However, normally, since the maximum bus occupancy time T of one block is specified, the access of 4 words is completed in about 4T or less.

  FIG. 18 shows a case where the REQ / ACK handshake is realized by hardware, and the timing between REQ / ACK can be realized by the minimum interval allowed by the hardware. On the other hand, FIG. 19 shows an example in the case where it is realized by software, and shows an example in which a block to be accessed operates on a software base such as a CPU or DSP. In the case of software processing, after acquiring the right to use the bus, loop processing is performed by software that actually accesses and reads or writes data and moves to data processing. There is a slight delay from time to time until the next REQ is issued. In addition, other processing such as an interrupt may enter during this processing, and the time until the next REQ is issued may be delayed as e. When the maximum value of the time d or e is S, the maximum processing time caused by the software processing part is (4-1) S = 3S or less.

  In the example of FIG. 19, the case where there is no delay between REQ and ACK is shown. However, in practice, the right to use the bus may not be acquired immediately by arbitration with other blocks, and the times b and c in FIG. Thus, a delay between REQ and ACK occurs. Therefore, the maximum processing time in software processing is the sum of these, and is about (3S + 4T) or less.

  The problem will be described by taking as an example a case where the transmission packet includes shuffled 4-word main data. The transmission packet may include other information such as a synchronization signal, ID, and parity in addition to the main data, but may or may not be present in the present invention. Since these are not directly related to the present invention, the description is omitted because they are not here. FIG. 20 shows a conventional example of a case where four transmission packets are used as one transfer unit and a transmission packet is received. The transmission packet is received by a buffer in the receiving circuit or the reproducing circuit, and then written into a memory storage area for each packet data. The buffer is often composed of a FIFO or the like. If the data bus width of the storage area is equal to or larger than the data amount of packet data, all data of one packet can be written by one write.

  Otherwise, it is efficient to write continuously over consecutive column addresses of the same RAW address by burst transfer. FIG. 17 illustrates this. The packet data written in the storage area may be arranged continuously in a packed manner to save the storage area, or a certain amount of space is opened and each packet does not cross the column boundary and is aligned in an appropriate size unit. You may arrange so that it may take.

  At the time of writing, as shown in FIG. 20, four times of four word writing occur. This corresponds to the path (1) -a or (1) -b in FIG. Since data is reproduced or received without interruption, it is processed by hardware. Therefore, the maximum waiting time at this time is 4T. When the packet data is shuffled for each word, in order to process each data in order, as shown in FIG. 20, it is necessary to read one word at a time according to the shuffled order, for a total of 16 times. 1-word read occurs. The situation at the time of reading from this storage area is the same as the case where the access efficiency described above is the lowest. When the reading process can be performed without delay by hardware processing, the maximum processing time required for reading is determined by the maximum waiting time of the bus and is 16T. If the reading is a software process and there is a possibility that the process may be delayed, 15S + 16T.

  An object of the present invention is to provide an audio data processing apparatus capable of reducing a read delay from a memory when the bit width of a data bus is wide.

In order to achieve the above object, the present invention
In an audio data processing apparatus for shuffling and rearranging audio data arranged in a time axis direction according to a predetermined rule, and adding and correcting an error correction code to the shuffled and rearranged audio data,
Storage means;
The shuffled and rearranged audio data is stored in the rearranged data unit with respect to the storage means, and the address interval SW is set to the second power of 2 to the n-th power of the shuffle period Q (Q ≦ n · 2 ^m = SW: n, m are positive integers), and writing means for writing the column boundaries of the storage means so as to match the shuffled and rearranged group of audio data ;
Error correction encoding means for adding the error correction code to audio data on the storage means;
Reading means for sequentially reading the audio data rearranged with the error correction code added on the storage means.

In order to achieve the above object, the present invention
The audio data arranged in the time axis direction is shuffled according to a predetermined rule and rearranged, and the data that has been encoded by adding an error correction code to the shuffled and rearranged audio data is subjected to error correction decoding and the original In an audio data processing device for decoding audio data in an array in the time axis direction of
Storage means;
Error correction decoding means for performing error correction decoding on the error correction encoded data and making the shuffled and rearranged audio data;
The error-corrected decoded audio data is arranged in the original time axis direction, and the address interval SW is set to 2 m to the second power of n bytes of the shuffle period Q or more for the storage means in the arranged data unit. The writing means writes the column boundary of the storage means so as to match the shuffled and rearranged group of audio data by setting Q ≦ n · 2 ^m = SW: n, m are positive integers) When,
Reading means for sequentially reading the audio data on the storage means.

  According to the present invention, the memory is shuffled and stored at the time of encoding, and the shuffle is released and stored at the time of decoding, so that continuous reading is possible at the time of reading, thus reducing the read delay from the memory. Can be made.

<First Embodiment>
The first embodiment of the present invention will be described below with reference to the drawings.
FIG. 1 is a diagram for explaining processing at the time of decoding, and shows a state in which each word DPk (DP0˜) is shuffled in the packet data. In this example, each word DPk (DP0˜) is shuffled at the same word position in the packet, and the subscript Pk of D indicates the word number. Therefore, the distance between words in the packet matches the shuffle period Q.

  In the present invention, when reproducing (receiving) these packet data, writing to the storage area is performed while the shuffle is solved and the original order is restored. At this time, as shown in FIG. 2, when paying attention to a packet, the write address is added by SW (= an integer equal to or less than Q) and written for each word in the packet. In FIG. The word DP0 of 0 is recorded at the head of the write destination area of the storage area when P0 = 0 (head data), and the next word DP0 + Q is written in an area separated by the address interval SW. The next word DP0 + 2Q is further written in an area separated by the address interval SW. Next, the packet No. If PX = 1 (next data) in X, packet No. The first word DPX of X is written at the next address of the word DP0. The next word DPX + Q is written in the area of the address separated from the word DPX by the address interval SW, that is, the next address of the word DP0 + Q.

  As described above, in the present invention, each word in each packet is written in the group divided by the address interval SW while being dispersed in order. At this time, the word data at the same word position in the packet is written so that the offset position from the head of the group in the group is the same.

  When the address interval SW is equal to the shuffle cycle Q, the data written in the storage area is arranged without a gap at the end of writing, and the memory utilization efficiency is the best. The written data is arranged in the original order of the words from the beginning and the shuffle release is performed. Therefore, when reading, as shown in FIG. Can be processed.

  FIG. 4 is an explanatory diagram showing a writing method in which the above method is applied to FIG. In FIG. 4, at the time of writing, each word in the packet is written at the same offset position in the group divided for each word. In this case, since one word is written by one writing, a total of 16 one-word writing occurs. If four words are read four times at the time of reading, the data arranged in the order in which the shuffle is released can be read. When the bus width is sufficiently large, for example, 4 words or more, 4 words can be read at a time by one reading. Otherwise, for example, when the bus width is the same as the word length, burst reading of four consecutive addresses is performed as shown in FIG.

  The maximum time required for writing is 16 times the maximum waiting time of the bus, which is 16T. Reading can be performed continuously for four words. If the bus width is wide, four words can be read simultaneously by one reading. Otherwise, continuous reading is possible by burst access as shown in FIG. In the case of software processing, even if it is burst access, the time is negligibly small compared to the maximum waiting time in software processing, so the total maximum waiting time is about 3S + 4T. In the end, reading from the FIFO is 4T on the writing side and 15S + 16T on the reading side in FIG. 20, and 15S + 20T in total, whereas in FIG. . In FIG. 4, the total is smaller and the processing is more efficient.

  The merit of the processing shown in FIG. 4 is that the processing time on the writing side can be substantially ignored by securing a sufficient storage area. That is, since the processing on the writing side can be scheduled to be processed in the background, an increase in processing time due to a penalty at the time of writing can be ignored. Therefore, the processing time is substantially concentrated on the processing time on the reading side, and the processing time of the processing shown in FIG. 4 can be significantly improved to 3S + 4T as compared with 15S + 20T in FIG.

Further, as shown in FIG. 4, the address interval SW is set to 2 to the mth power of 2 bytes (Q ≦ n · 2 ^m = SW: n, where m is a positive integer) greater than or equal to the shuffle period Q. When the SW and the shuffle cycle Q are not equal, an unused area is generated in the group, so that the memory use efficiency is somewhat lowered, but the following effects are obtained. In DRAMs, memory cells are generally specified by row and column addresses, so continuous access can be made within the same row. However, cross-row (column boundary) access requires a reset of the row address. There is a problem that occurs. This is a problem that processing such as boundary determination and address control becomes complicated and access time is excessive. In the present invention, by setting the address interval SW to a power of 2 that is equal to or greater than the shuffle period Q, the memory column boundary can be matched with the group. Therefore, it is possible to access without being aware of the column boundary when reading data.

  In the above processing, when data is read from the FIFO and written to the storage area, an address control circuit (not shown) directly manipulates the write destination address of the storage area, thereby realizing the method unique to the present invention. The above is the explanation at the time of reproduction and reception, but the processing contents are the same except that the signal flow is reversed at the time of recording and transmission, and the explanation is omitted. In the above description, the case where the shuffle direction is limited to the same word position has been described. However, any shuffle rule may be used as long as each word is continuously arranged within the same group. Can respond.

  Next, audio processing during recording according to the present invention will be described with reference to FIG. The audio signal input via the A / D converter 1 a and the buffer (input buffer) 2 is shuffled by the DSP 3 and stored in the memory (MEM) 4, and then stored in the memory 4 by the outer code correction circuit (OECC) 5. The outer code (outer parity) is added. When recording on the tape T, the inner code (inner parity) is added while reading the data on the memory 4 by the inner code correction circuit (IECC) 6 through the path (6) -a, and the recording signal processing circuit 7a. Thus, the data is recorded on the tape T in the sync block structure as shown in FIG. When transmitting to an external device via the digital I / F (1394 I / F) 8 in FIG. 5, only the part (the transmission packet in FIG. 14) constituting the ID and audio data in the sync block shown in FIG. Are transmitted. This part is 80 bytes, and the audio data is 72 bytes.

  Next, audio processing during reproduction according to the present invention will be described with reference to FIG. Data reproduced from the tape T is subjected to inner code correction processing by an inner code correction circuit (IECC) 6 and stored in a storage area of the memory (MEM) 4. The stored data is then written to the memory 4 by the outer code correction circuit (OECC) 5 performing an outer code error correction process on the audio data in the memory 4 to release the shuffle. The shuffled audio data on the memory 4 is read by the DSP 3 and sent to the D / A converter 1b via the buffer (output buffer) 2 to reproduce the audio signal.

<Second Embodiment>
FIG. 7 shows a second embodiment of the present invention. In FIG. 6, when reading from the FIFO and writing to the storage area of the memory 4, the address control circuit (not shown) directly implements the write destination address of the storage area to realize the method of the present invention. In this manner, a DMA controller (DMA) 10 may be provided to release shuffle. That is, in FIG. 6, the processing shown in FIG. 4 in which the memory writing is performed in the path (1) (indicated by circled numbers in FIG. 7; the same applies hereinafter) -a or (1) -b is illustrated in FIG. In (6), the DMA controller 10 performs memory writing. Therefore, in the writing of the route (1) -a or (1) -b in FIG. 7, the packet reproduced or received is written in the memory as it is as before. That is, it is the same as the writing shown in FIG.

  In the second embodiment, the DMA controller 10 reads the packets as they are in the order of writing, and performs writing by releasing the shuffle at the time of writing as in the writing of FIG. Thereby, in the path (2), continuous reading is possible as in the reading shown in FIG. The process is also shown in FIG. 8 for explaining the third embodiment.

Since the processing by the DMA controller 10 may be executed with the priority lowered in the background, the processing time is substantially aggregated to the time on the reading side, and the substantial maximum processing time is 3S + 4T as in FIG. The merit of this method is that when the method of the present invention is applied to an existing circuit, it can be realized only by adding the DMA controller 10 without changing the existing circuit. In addition, since the circuits are independent, it is easy to execute the rearrangement process at a lower priority in the background. As a result, the shuffle release can be executed without consuming much resources of the entire system.
The above is the explanation at the time of reproduction and reception, but the processing contents are the same except that the signal flow is reversed at the time of recording and transmission, and the explanation is omitted.

<Third Embodiment>
In general, in order to reduce the amount of data during transmission, there is a method of compressing the amount of data in units of words. For example, there is a method of nonlinearly compressing 16-bit data in one word into 12-bit data. FIG. 8 shows a third embodiment in which a compression circuit 11 and an expansion circuit 12 are provided in the DMA controller 10. FIG. 9 shows the compression rule, and shows how 16-bit shuffled data is converted to 12-bit compressed data. In order to obtain byte alignment of the compressed data, 2 words are converted into units. That is, two consecutive uncompressed words of 32 bits and 24 bits of compressed data are converted into each other. FIG. 10 is a diagram showing how 12-bit compressed data is expanded to 16-bit uncompressed data.

  In FIG. 9, the first 16-bit uncompressed word is converted by the 16 → 12 compression circuit 11 to become a 12-bit compressed word. Of the 12 bits, the upper 8 bits are assigned to the first byte, and the lower 4 bits are assigned to the upper 4 bits of the third byte. Similarly, the next 16-bit uncompressed word is converted by the 16 → 12 compression circuit 11 into a 12-bit compressed word. Of the 12 bits, the upper 8 bits are assigned to the second byte, and the lower 4 bits are assigned to the lower 4 bits of the third byte.

  At the time of decompression, the 12-bit two compressed data are converted into 16-bit uncompressed words by the 12 → 16 decompression circuit 12, respectively, and are shuffled as shown in FIG. Conventionally, the above operation has been performed as internal processing of the DSP 3 when the DSP 3 reads the word after the shuffle release from the memory 4 through the path (2) in FIG. Further, at the time of compression, before the DSP 3 writes to the memory 4 through the path (5) in FIG.

  In the present invention, these processes are performed in the DMA controller 10, and data conversion processing (compression or expansion) is performed simultaneously with data transfer. Referring to FIG. 7, in the DMA controller 10 of the path (6), the 2-word data read from the memory 4 is expanded and converted into two consecutive 16-bit words. Write again.

  At the time of compression, the direction of the signals in FIG. Referring to FIG. 7, compression processing is performed on continuous 2-word data read from the memory 4 in the DMA controller 10 through the path (6), and the compressed data is converted into 24-bit 2-word data. Write again. According to the above method, data conversion and transfer can be simultaneously performed in one clock in the DMA controller 10, so that there is an advantage that efficiency is improved and conversion processing is not required in the DSP 3.

(1) When writing to the memory 4, shuffled words are released from the shuffle and arranged continuously on the memory 4, so it is not necessary to release the shuffle at the time of reading, and shuffle is performed by continuous reading. The released data can be read, and the reading efficiency can be greatly improved.
(2) In addition to (1), there is no penalty at the column boundary at the time of reading, so that complicated control near the column boundary becomes unnecessary and access efficiency does not decrease.
(3) Data conversion for decompressing compressed data can be performed efficiently during transmission, so that subsequent processing is unnecessary. In addition, it is more efficient than processing at a later stage.
(4) Since data arranged continuously in units of groups can be rearranged into a shuffled state, when reading to transmit a transmission packet, the main data can be read out by continuous reading. Efficiency can be greatly improved.
(5) In addition to (4), there is no penalty at the column boundary at the time of reading, so that complicated control near the column boundary becomes unnecessary and access efficiency does not decrease.
(6) Data conversion for compressing data can be efficiently performed in the middle of transmission, so that processing in the previous stage is unnecessary. Also, it is more efficient than processing in the previous stage.
(7) Since a DMA controller is separately provided as a means for shuffling and a means for releasing the shuffle, it can be realized without changing an existing circuit. Further, by making the processing circuits independent, the rearrangement process can be executed with a lower priority in the background, so that the shuffle and the shuffle release can be realized without consuming too much resources of the entire system.

It is explanatory drawing which shows the shuffle data in the process at the time of the decoding in this invention. It is explanatory drawing which shows the state which cancels | releases the shuffle of the shuffle data of FIG. 1, and writes in a memory. FIG. 3 is an explanatory diagram showing a reading order of shuffle release data in FIG. 2. It is explanatory drawing which shows the address space | interval which writes shuffle data in this invention. It is a block diagram which shows 1st Embodiment of the audio processing system at the time of recording in this invention. It is a block diagram which shows 1st Embodiment of the audio processing system at the time of reproduction | regeneration in this invention. It is a block diagram which shows 2nd Embodiment of the audio processing system at the time of reproduction | regeneration in this invention. It is a block diagram which shows the principal part of 3rd Embodiment of the audio processing system at the time of reproduction | regeneration of this invention. It is explanatory drawing which shows the process of the compression circuit of FIG. It is explanatory drawing which shows the process of the expansion | extension circuit of FIG. It is explanatory drawing which shows the tape format of DV system digital VTR. It is explanatory drawing which shows the structure of one track in FIG. It is explanatory drawing which shows the structure of the audio sector in FIG. It is explanatory drawing which shows the structure of the audio data in FIG. It is explanatory drawing which shows the structure of the sync block of the audio sector of FIG. It is a block diagram which shows a general memory access circuit. It is explanatory drawing which shows an example of the memory reading in FIG. It is explanatory drawing which shows the other example of the memory reading in FIG. It is explanatory drawing which shows the other example of the memory reading in FIG. It is explanatory drawing which shows the process which writes the conventional shuffle data.

Explanation of symbols

1a A / D converter 1b D / A converter 2 Buffer (input buffer, output buffer)
3 DSP
4 Memory (MEM)
5 Outer code correction circuit (OECC)
6 Inner code correction circuit (IECC)
7a Recording signal processing circuit 8 Digital I / F (1394 I / F)
9 Bus 10 DMA controller (DMA)
11 Compression circuit (16 → 12 compression circuit)
12 expansion circuit (12 → 16 expansion circuit)
SW address interval T tape

Claims (2)

In an audio data processing apparatus for shuffling and rearranging audio data arranged in a time axis direction according to a predetermined rule, and adding and correcting an error correction code to the shuffled and rearranged audio data,
Storage means;
The shuffled and rearranged audio data is stored in the rearranged data unit with respect to the storage means, and the address interval SW is set to the second power of 2 to the n-th power of the shuffle period Q (Q ≦ n · 2 ^m = SW: n, m are positive integers), and writing means for writing the column boundaries of the storage means so as to match the shuffled and rearranged group of audio data ;
Error correction encoding means for adding the error correction code to audio data on the storage means;
Read means for sequentially reading out the audio data rearranged by adding the error correction code on the storage means,
An audio data processing apparatus. The audio data arranged in the time axis direction is shuffled according to a predetermined rule and rearranged, and the data encoded by adding an error correction code to the shuffled and rearranged audio data is error corrected and decoded. In an audio data processing device for decoding audio data in an array in the time axis direction of
Storage means;
Error correction decoding means for performing error correction decoding on the error correction encoded data and making the shuffled and rearranged audio data;
The error correction decoded audio data is arranged in the original time axis direction, and the address interval SW is set to the second power of n bytes equal to or greater than the shuffle period Q to the storage means in the arranged data unit. The writing means writes the column boundaries of the storage means so as to match the shuffled and rearranged group of audio data by setting Q ≦ n · 2 ^m = SW: n, m are positive integers) When,
Reading means for sequentially reading the audio data on the storage means;
An audio data processing apparatus.

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