JP5037814B2 - Memory control device and memory control method - Google Patents

Description

  The present invention relates to a memory control device and a memory control method, and more particularly to a data transfer technique related to a commonly used memory.

  Conventionally, in a system in which various processing units, memories, input / output units, and the like are connected by buses, a method has been proposed in which each processing unit shares and uses one memory in order to reduce the overall cost of the system. ing. In a system that handles moving image signals, audio signals, etc., there are a plurality of processing units that perform predetermined processing at a fixed time, and they operate simultaneously, so that each processing unit also performs data transfer with the memory. Must finish within a certain time.

  In general, the memory control unit of such a system is equipped with an arbiter circuit that arbitrates memory access requests from each processing unit according to priority in order to prevent one processing unit from occupying the memory for a long time. . As a result, when a certain processing unit is permitted to transfer data to and from the memory, the other processing unit waits for data transfer to and from the memory.

  However, in data transfer to and from the memory, depending on the data length and priority settings to be transferred, the process cannot be completed within a certain time, or the data transfer cannot be completed within the required certain time. there's a possibility that. As one method for dealing with this, for example, Patent Document 1 discloses the following memory control method. Assume that there is a memory access request from a processing unit having a higher priority than the processing unit that has previously transferred data to and from the memory. In this case, a method has been proposed in which the current data transfer is interrupted, the data transfer is performed by a processing unit having a high priority, and the interrupted data transfer is resumed after the data transfer is completed.

JP 2003-114825 A

  As described above, when a high-priority processing unit performs data transfer with a memory, in a mechanism for waiting for data transfer by a processing unit having a lower priority than the processing unit, the processing unit having a lower priority The waiting time becomes longer. Therefore, it is relatively difficult to determine the priority and the transfer data length per transfer process in consideration of the performance of the entire system. Also, in order to perform data transfer by interrupting a memory access request from a processing unit having a high priority with respect to data transfer performed in advance with the memory, complicated processing is performed in the memory control unit. I need.

  The present invention has been made in view of such circumstances, and is intended to enable data transfer with a shared and used memory easily and without breaking real-time characteristics or the like. Objective.

The memory control device according to the present invention is a means for controlling a plurality of processing means and data transfer between the plurality of processing means and the memory, wherein a transfer request is sent from a first processing means in the plurality of processing means. The first data is transferred in units of the first data length, and the second data requested by the second processing means in the plurality of processing means is transferred to the second data shorter than the first data length. Control means for transferring the data length in units of data, and the control means transfers the first data having the first data length and then transferring the second data having one second data length. The first data of the next first data length is transferred at a time interval necessary for the first data length, and the first data of the first data length is transferred after the first data of the first data length is transferred. The second data until the first data is transferred. Characterized by transferring the second data over data length.
A memory control method according to the present invention is a method for controlling data transfer between a memory and a plurality of processing means, wherein the first data requested to be transferred from the first processing means in the plurality of processing means is stored. The first data length is transferred in units, and the second data requested to be transferred from the second processing unit in the plurality of processing units is transferred in units of a second data length shorter than the first data length. Then, after transferring the first data of the first data length, the next first data length at a time interval necessary for transferring the second data of one second data length. The first data is transferred, and the second data length is transferred after the first data having the first data length is transferred and before the first data having the first data length is transferred. The second data is transferred.

  Transfer from the second processing means can be performed easily and without breaking the real-time property of the data transfer by the transfer request from the first processing means even during the data transfer by the transfer request from the first processing means. It becomes possible to transfer data upon request. Therefore, the waiting time for data transfer in each processing means can be reduced, and the memory capacity for holding input / output data for each processing means can be reduced accordingly.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a block diagram showing a configuration example of a video recording / reproducing apparatus to which an information processing system according to an embodiment of the present invention is applied.

  An A / D (analog / digital) converter 101 converts an analog video signal input as a video signal input into a digital video signal. The D / A (digital / analog) conversion unit 102 converts the digital video signal supplied from the video signal processing unit 103 into an analog video signal and outputs the analog video signal as a video signal output.

  The video signal processing unit 103 converts the digital video signal supplied from the A / D conversion unit 101 into a data format corresponding to the recording format and supplies it as recording video data to the recording / playback processing unit 104 during the recording operation. Further, the video signal processing unit 103 converts the playback video data supplied from the recording / playback processing unit 104 into a digital video signal and supplies the digital video signal to the D / A conversion unit 102 during the playback operation.

  The recording / playback processing unit 104 records the recorded video data supplied from the video signal processing unit 103 on the recording medium 107 during the recording operation. At this time, the recording / playback processing unit 104 performs an encoding process according to the recording format on the recording video data supplied from the video signal processing unit 103, adds an error correction code, and records the data on the recording medium 107. I do. Further, the recording / playback processing unit 104 performs decoding processing and error correction processing on the data read from the recording medium 107 during the playback operation, and uses the decoded data as playback video data. To supply.

  The processing performed by the video signal processing unit 103 and the recording / playback processing unit 104 is executed while reading and writing data in units of a predetermined data length with respect to the memory 106 via the memory controller 105. The memory 106 is, for example, an SDRAM (Synchronous Dynamic Random Access Memory), and an area accessed by the video signal processing unit 103 and an area accessed by the recording / playback processing unit 104 are arranged in different banks.

  The memory controller 105 includes a FIFO (First In First Out) (A) 108, a sequencer (A) 109, a FIFO (B) 110, a sequencer (B) 111, and a selector unit 112.

  A FIFO (A) 108 temporarily holds write data from the video signal processing unit 103 or read data from the memory 106, and a sequencer (A) 109 controls a memory access request from the video signal processing unit 103. . Similarly, the FIFO (B) 110 temporarily holds write data from the recording / playback processing unit 104 or read data from the memory 106, and the sequencer (B) 111 receives a memory access request from the recording / playback processing unit 104. To control. The selector unit 112 switches SDRAM commands, addresses, and data from the sequencer (A) 109 and the sequencer (B) 111.

  Here, the sequencer (A) 109 controls the data transfer with the data length requested from the video signal processing unit 103 to be divided into designated data length units and to perform data transfer with the memory 106. Similarly, the sequencer (B) 111 controls the data transfer with the data length requested from the recording / playback processing unit 104 to be divided into designated data length units and to perform data transfer with the memory 106.

  The sequencer (A) 109 operates to perform data transfer with a time interval necessary for data transfer between the sequencer (B) 111 and the memory 106 when performing data transfer with the memory 106. To do. That is, in the data transfer between the sequencer (A) 109 and the memory 106, the divided data having the designated data length is transferred, and at least the time during which the data transfer can be executed between the sequencer (B) 111 and the memory 106 is performed. After elapses, the next divided data is transferred.

  The sequencer (A) 109 supplies the transfer start timing signal of the sequencer (B) 111 to the sequencer (B) 111. The sequencer (B) 111 operates to transfer data to and from the memory 106 in accordance with the transfer start timing signal supplied from the sequencer (A) 109. That is, this transfer start timing signal is a signal indicating that the start of data transfer between the sequencer (B) 111 and the memory 106 is permitted.

  As a result, the memory controller 105 divides and reads / writes data to / from the memory 106 in response to memory access requests from the video signal processing unit 103 and the recording / playback processing unit 104. That is, data transfer between the video signal processing unit 103 and the recording / playback processing unit 104 and the memory 106 is performed by the memory controller 105 in a time division manner.

  Here, the video signal processing unit 103 includes only a memory capable of storing at least the amount of data necessary for processing of one video signal or less within the video signal processing unit 103, and within one line time of the video signal to be input / output. It is necessary to read / write data for one line to / from the memory 106. The video signal processing unit 103 ensures real-time performance by performing burst transfer of data corresponding to one line of the video signal to the memory 106 in units of a predetermined data length.

  On the other hand, the recording / playback processing unit 104 is a processing unit that only needs to process data for one frame within one frame time of the video signal during both recording and playback processing operations. That is, the recording / playback processing unit 104 has lower real-time characteristics than the video signal processing unit 103, and also has a low transmission rate in order to handle encoded data. Note that the video signal processing unit 103 and the recording / playback processing unit 104 can make a memory access request for data transfer in a predetermined data length unit independently at each processing timing.

  Note that each function unit (for example, the video signal processing unit 103, the recording / playback processing unit 104, the memory controller 105, and the memory 106) illustrated in FIG. 1 may be configured by an independent device or integrated. It may be a single device. Further, not all functional units but arbitrary functional units may be integrated and configured as one device.

  The data transfer control operation in the memory controller 105 will be described below. The video signal processing unit 103 makes a read request with a 90 word length as shown in FIG. 2A, and the recording / playback processing unit 104 makes a write request with a 20 word length as shown in FIG. The case where it performs is demonstrated as an example. Note that the data length when the video signal processing unit 103 and the recording / playback processing unit 104 make a read request or write request to the memory 106 is not limited to this and is arbitrary.

  Here, the video signal processing unit 103 and the recording / playback processing unit 104 communicate with the memory controller 105 using the same protocol. That is, as shown in FIGS. 2A and 2B, the video signal processing unit 103 and the recording / reproduction processing unit 104 are sections in which a request signal indicating a data transfer request to and from the memory 106 is asserted to a high level. Simultaneously transmit an address signal indicating the contents of the transfer request. Write data is output or read data is input at a timing when a certain period has elapsed from the assertion timing of the request signal.

  As shown in FIG. 2, the address signal is defined by an R / W area, a burst length area, and an offset address area. The R / W area indicates whether the transfer request is a read request or a write request, and the burst length area indicates the amount of transfer data. The offset address area indicates the head address on the memory 106 that performs reading or writing. The memory controller 105 performs data transfer with the memory 106 based on each information in the address signal.

  First, in the data transfer related to the request from the video signal processing unit 103, the sequencer (A) 109 is set to divide the burst length requested from the video signal processing unit 103 into units of 8 words. If the burst length is not divisible in units of 8 words, the remaining fractional word is scheduled to be added to the first burst length for transfer (this reduces the number of divided transfers by one). Therefore, the overhead generated by the SDRAM command can be reduced).

  That is, in the example shown in FIG. 2A, 90 words related to the request from the video signal processing unit 103 are divided into units of 8 words, so that the remaining 2 words are added to the head, and 10 words (= 8 + 2) It is scheduled to perform data transfer at × 1 + 8 words × 10 times. The sequencer (A) 109 is connected to the memory 106 with a time interval necessary for divided transfer (described later) by the sequencer (B) 111 described later for each divided transfer (every data transfer of 10 words or 8 words). Data transfer with. The sequencer (A) 109 generates a transfer start timing signal for the sequencer (B) 111 to start the divided transfer every time one divided transfer (10-word or 8-word data transfer) is completed. (B) is supplied to 111 (see FIG. 3A).

  On the other hand, in the data transfer related to the request from the recording / playback processing unit 104, the sequencer (B) 111 is set to divide the burst length requested from the recording / playback processing unit 104 into units of four words. If the burst length is not divisible in units of 4 words, the remaining fractional word is scheduled to be added to the leading burst length for transfer.

  In the example shown in FIG. 2B, since 20 words related to the request from the recording / playback processing unit 104 are divided into units of 4 words, scheduling is performed so that data transfer is performed in 4 words × 5 times. When writing to the memory 106, the data (20 words) output from the recording / playback processing unit 104 is sequentially stored in the FIFO (B) 110. The sequencer (B) 111 reads data from the FIFO (B) 110 four words at a time in accordance with the transfer start timing signal supplied from the sequencer (A) 109, and performs write transfer to the memory 106 (FIG. 3B). )reference). Therefore, the empty interval required for the divided transfer in the sequencer (B) 110 provided by the sequencer (A) 108 is an interval for 4 word transfer.

  The SDRAM command, address, and data input / output between the sequencer (A) 109 and the sequencer (B) 111 and the memory 106 are appropriately switched by the selector unit 112. As a result, the data transfer requested from the video signal processing unit 103 and the recording / playback processing unit 104 is divided into time divisions, and the data transfer is performed with the memory 106 (SDRAM) (see FIG. 3C). . Here, when the sequencer (A) 109 does not receive a data transfer request from the video signal processing unit 103, the sequencer (A) 109 transfers the transfer start timing signal at the shortest interval necessary for the burst transfer of the sequencer (B) 111. Is output (see FIG. 4). In this way, when there is no data transfer request from the video signal processing unit 103 and there is no competition in the data transfer requested from the recording / playback processing unit 104, the transfer of the recording / playback processing unit 104 can be performed efficiently. It has become.

  The area accessed by the video signal processing unit 103 and the area accessed by the recording / playback processing unit 104 are arranged in different banks on the memory 106 as described above. With this configuration, when the video signal processing unit 103 and the recording / reproduction processing unit 104 perform data transfer alternately as shown in FIG. Data transfer is possible.

  The above-described data transfer control operation is the same regardless of whether the transfer request from the video signal processing unit 103 and the recording / playback processing unit 104 is a request with another burst length or a request for reading or writing. It is. By this data transfer control operation, the divided transfer by the video signal processing unit 103 and the recording / playback processing unit 104 can be simultaneously performed without waiting for the data transfer by the video signal processing unit 103.

  As described above, according to the present embodiment, data transfer requested from the video signal processing unit 103 and the recording / playback processing unit 104 is divided into fixed data lengths specified in advance, and data transfer to and from the memory 106 is performed. . At this time, data transfer with the divided fixed data length according to the video signal processing unit 103 is performed such that a time during which the data transfer with the divided fixed data length according to the recording / playback processing unit 104 can be executed is made free after the divided data transfer. Do. Then, data transfer related to the recording / playback processing unit 104 is performed in the idle time. By performing time division transfer with such easy control, it is possible to perform data transfer related to the recording / playback processing unit 104 almost simultaneously without waiting for data transfer related to the video signal processing unit 103. Therefore, efficient memory transfer can be performed between the video signal processing unit 103 and the recording / playback processing unit 104 and the memory 106 used in common, and data transfer can be easily performed without breaking real-time characteristics or the like. It becomes possible to do.

  The above-described embodiments are merely examples of implementation in carrying out the present invention, and the technical scope of the present invention should not be construed as being limited thereto. That is, the present invention can be implemented in various forms without departing from the technical idea or the main features thereof.

It is a block diagram which shows the structural example of the video recording / reproducing apparatus in one Embodiment of this invention. It is a figure for demonstrating the transfer protocol and address definition of the memory controller in this embodiment. It is a figure which shows an example of the data transfer control in this embodiment. It is a figure which shows the other example of the data transfer control in this embodiment.

Explanation of symbols

103 video signal processing unit 104 recording / playback processing unit 105 memory controller 106 memory 107 recording medium 108, 110 FIFO
109, 111 Sequencer 112 Selector section

Claims (10)

A plurality of processing means;
Means for controlling data transfer between the plurality of processing means and the memory, wherein the first data requested to be transferred from the first processing means in the plurality of processing means is expressed in units of a first data length. Control means for transferring and transferring the second data requested to be transferred from the second processing means in the plurality of processing means in units of a second data length shorter than the first data length;
The control means transfers the next first data at a time interval necessary for transferring the second data having one second data length after transferring the first data having the first data length. The first data having the data length of the first data length is transferred, and the second data is transferred between the transfer of the first data having the first data length and the transfer of the first data having the first data length. A memory control device for transferring second data having a data length of.   The control means transfers the second data of the second data length every time the transfer of the first data of the first data length is completed once. The memory control device described.   2. The memory control device according to claim 1, wherein the data length of one transfer request of the first processing unit is longer than the data length of one transfer request of the second processing unit.   The control means is necessary for transferring the second data having the second data length when there is no transfer request from the first processing means and there is a transfer request from the second processing means. The memory control device according to claim 1, wherein the second data having the second data length is transferred at various time intervals. The control means includes a first transfer control unit that controls transfer of the first data, and a second transfer control unit that controls transfer of the second data,
The first transfer control unit outputs transfer permission to the second transfer control unit in response to completion of transfer of the first data of the first data length,
2. The memory according to claim 1, wherein the second transfer control unit transfers the second data having the second data length in accordance with the transfer permission from the first transfer control unit. Control device.   The first transfer control unit transfers the second data having the second data length when there is no transfer request from the first processing means and there is a transfer request from the second processing means. 6. The memory control device according to claim 5, wherein the transfer permission is output to the second transfer control unit at a time interval necessary for the transfer.   The control means transfers the first data from the first processing means to the memory when the transfer request from the first processing means is a write request, and from the first processing means. If the transfer request is a read request, the first data is transferred from the memory to the first processing means, and if the transfer request from the second processing means is a write request, When the second data is transferred from the second processing means to the memory, and the transfer request from the second processing means is a read request, the second processing means sends the second data to the second processing means. The memory control device according to claim 1, wherein two data are transferred.   The control means divides the first data requested to be transferred by one transfer request from the first processing means into the first data length, and as a result, the control data is less than the first data length. 2. The memory control device according to claim 1, wherein, in addition to the first data length, data is transferred at the beginning of data transfer by one transfer request from the first processing means.   2. The memory control device according to claim 1, wherein a transmission rate of data handled by the first processing unit is higher than a transmission rate of data handled by the second processing unit. A method for controlling data transfer between a memory and a plurality of processing means,
The first data requested to be transferred from the first processing means in the plurality of processing means is transferred in units of a first data length, and the second data requested to be transferred from the second processing means in the plurality of processing means. Is transferred in units of a second data length shorter than the first data length, the first data of the first data length is transferred, and then the second data length of one second data length is transferred. The first data having the first data length is transferred at a time interval necessary for transferring the first data, and the first data having the first data length is transferred and then the first data having the first data length is transferred. A memory control method comprising: transferring the second data having the second data length before the first data having the data length is transferred.

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