JP3569592B2 - Codec - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a codec suitable for codec processing of a signal such as an audio signal for a relatively long time.
[0002]
[Prior art]
2. Description of the Related Art At present, multimedia is being promoted in various fields, and the types of information to be provided to users and the types of information provision are being enriched. Various types of personal computers and other devices equipped with a PCM sound source and the like have been provided for a long time. Recently, however, devices having a function of reproducing or recording not only musical sounds but also human voices and music have been provided. Are provided. Here, since the duration of human voice, music, and the like is much longer than that of musical sounds, dedicated hardware for recording and reproduction is mounted on a personal computer or the like.
[0003]
FIG. 2 shows an example in which such hardware is applied to a personal computer. In this figure, 1 is a CPU of a personal computer, 2 is a memory such as a RAM, 3 is a CODEC (Code-Decoder; codec), 4 is a DMAC (Direct Memory Access Controller), and 5 is a bus connecting the above components. It is.
[0004]
In this personal computer, a storage area of a predetermined size secured in the memory 2 is used as a buffer, and PCM audio data reproduced from a hard disk device (not shown) is converted into a continuous analog signal via a CODEC 3. It is possible to execute a process of converting an external analog signal into PCM audio data by the CODEC 3 and storing the same in a hard disk device or the like.
[0005]
The CODEC 3 samples an analog audio signal of an external sound obtained through an input device (not shown) such as a microphone and performs PCM encoding on the sampled audio signal. The encoding process takes in PCM audio data into the personal computer. This is a means for performing a decoding process of converting the generated PCM audio data into an analog audio signal and supplying it to an output device such as a speaker.
[0006]
The encoding process and the decoding process need to be continuously performed according to a clock of a fixed sampling frequency completely asynchronously with the transmission of the PCM audio data between the memory 2 and the CODEC 3. For this reason, the CODEC 3 has a built-in buffer for absorbing a timing difference between the encoding process or the decoding process and the input / output operation of the PCM audio data to the CODEC 3.
[0007]
The transmission of PCM audio data between the CODEC 3 and the memory 2 is performed by DMA transfer. This DMA transfer is performed under the control of the DMAC 4.
[0008]
In such a configuration, the process of outputting sound to the outside is performed as follows. First, the CPU 1 reads a predetermined amount of PCM audio data from, for example, a hard disk device and stores it in the memory 2. Information necessary for controlling DMA transfer, such as a storage start address of the PCM audio data in the memory 2 and a data size. Is set to DMAC4. In addition, the CPU 1 sets information necessary for controlling the decoding process, such as a sampling frequency when the PCM audio data is D / A converted, in the CODEC 3.
[0009]
When the above initialization is completed, the DMA transfer is started. That is, the PCM audio data in the memory 2 is read one byte at a time in order from the first one by the DMAC 4 and supplied to the CODEC 3. As a result, the buffer of the CODEC 3 is filled with the PCM audio data. Then, in the CODEC 3, a clock having the sampling frequency set by the initial setting is generated, and in synchronization with this clock, the PCM audio data in the buffer is sequentially converted into an analog audio signal and output to the outside. When the amount of unprocessed PCM audio data in the buffer becomes small, a signal indicating that fact is sent from the CODEC 3 to the DMAC 4. As a result, new PCM audio data is read from the memory 2 by the DMAC 4 and supplied to the CODEC 3. Thereafter, similarly, whenever the PCM audio data in the buffer of the CODEC 3 becomes small, the DMA transfer of the PCM audio data from the memory 2 to the CODEC 3 is performed.
[0010]
When the DMA transfer of the PCM audio data in the memory 2 ends, an interrupt signal is sent from the DMAC 4 to the CPU 1. As a result, the CPU 1 stores a predetermined amount of PCM audio data in the memory 2 again, and sets information necessary for DMA transfer control in the DMAC 4. Then, similarly to the above, the DMA transfer of the PCM audio data is performed, and the PCM audio data is converted into an analog audio signal at a fixed sampling frequency. By repeating the above operation, a sound for a long time is reproduced.
[0011]
On the other hand, the process of storing the voice fetched from outside as PCM voice data in a hard disk device or the like is performed as follows. First, as described above, a storage area of a predetermined size in the memory 2 is used as a buffer for temporarily storing PCM audio data, and information designating this storage area is set in the DMAC 4. Further, the initial setting of the CODEC 3 is performed in the same manner as described above.
[0012]
When the initialization is completed, the CODEC 3 generates a clock having the sampling frequency set by the above-described initialization, and in synchronization with this clock, an external analog audio signal is sequentially converted into PCM audio data and stored in the buffer. Stored. When a predetermined amount of PCM audio data is accumulated in the buffer, a signal indicating that fact is sent from CODEC 3 to DMAC 4. As a result, the PCM audio data in the buffer of the CODEC 3 is read by the DMAC 4 and DMA-transferred to the memory 2. Thereafter, similarly, every time a predetermined amount of PCM audio data is accumulated in the buffer of the CODEC 3, DMA transfer of the PCM audio data from the CODEC 3 to the memory 2 is performed.
[0013]
When the storage area for the PCM audio data in the memory 2 is filled with the PCM audio data, the DMAC 4 sends an interrupt signal to the CPU 1. As a result, the PCM audio data in the memory 2 is read by the CPU 1 and sent to a hard disk device or the like. Then, similarly to the above, the DMA transfer of the PCM audio data is performed. By repeating the above operation, a long-lived sound is recorded on the hard disk device or the like.
[0014]
[Problems to be solved by the invention]
By the way, among the above-mentioned conventional techniques, those using DMAC have a problem that the cost is increased due to the complexity of the system. In addition, since control signals are exchanged between the CODEC and the DMAC to perform DMA transfer of PCM voice data by the DMAC, there is a problem that control is complicated and inefficient.
[0015]
The present invention has been made in view of the circumstances described above, and has as its object to provide a codec that can efficiently transmit and receive information to and from the outside and perform codec processing on the information. And
[0016]
[Means for Solving the Problems]
The invention according to claim 1 is connected to a memory via a bus, encodes an analog signal fetched from the outside at a designated sampling frequency, and transmits PCM data obtained by the encoding to the memory via the bus. A codec device that performs a process of supplying and a process of sequentially taking in PCM data from the memory via the bus, converting the PCM data into an analog signal at a specified sampling frequency, and outputting the analog signal to the outside;
First buffer means for storing PCM data obtained by encoding an analog signal taken from the outside;
Second buffer means for storing PCM data to be converted into an analog signal, which is fetched from the memory;
When supplying the PCM data accumulated in the first buffer means to the memory, the CPU connected to the bus secures a memory block of a predetermined size in the memory, and then transmits the data to the first buffer means. Each time a predetermined amount of PCM data is accumulated, the right to use the bus is acquired, and the PCM data is read from the first buffer means until the predetermined amount of free area is secured in the first buffer means. An interrupt signal for requesting the CPU to secure a new memory block when the memory block is filled with PCM data while repeating the process of transferring to the memory block via the bus and releasing the right to use the bus. While sending
When converting the PCM data stored in the second buffer means to an analog signal and outputting the analog signal to the outside, the CPU connected to the bus secures a memory block of a predetermined size in the memory, and After the PCM data is stored in the second buffer means, every time a predetermined amount of free area is secured in the second buffer means, the right to use the bus is acquired, and the predetermined amount of PCM data is accumulated in the second buffer means. Until the PCM data is read from the memory block and transferred to the second buffer means via the bus, the process of releasing the right to use the bus is repeated, and all the PCM data in the memory block is read. When, and a bus controller for sending an interrupt signal for requesting the CPU to store the new PCM data to said memory block And gist codec device, characterized by Bei.
[0017]
In the invention according to claim 2, when the bus controller converts the PCM data stored in the second buffer means into an analog signal and outputs the analog signal to the outside, the bus controller determines the start address of the secured memory block. 2. The codec according to claim 1, wherein information indicating the range is obtained from the CPU, and PCM data is read from the memory block based on the obtained start address and information indicating the range. Make a summary.
[0019]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments will be described to make the present invention easier to understand.
These embodiments show one aspect of the present invention, and do not limit the present invention, and can be arbitrarily changed within the scope of the present invention.
[0020]
FIG. 1 is a block diagram showing the configuration of a personal computer using a CODEC 3a according to an embodiment of the present invention. This embodiment has a configuration in which the DMAC 4 is removed from the configuration shown in FIG. 2 and a CODEC 3 a is used instead of the CODEC 3. The CODEC 3a includes a CPU interface 31, a bus controller 32, a reproduction FIFO 33, a recording FIFO 34, a D / A converter 35, and an A / D converter 36.
[0021]
In the configuration of FIG. 2 described above, control for accessing the memory 2, such as generation of address information, is performed by the DMAC 4. On the other hand, transmission / reception of an analog audio signal with an external device, encoding processing, and decoding processing are performed. Since it is performed by the CODEC 3, it is necessary to frequently exchange control information between the DMAC 4 and the CODEC 3 so that the access to the memory 2 and the processing in the CODEC 3 progress in step with each other. However, in the present embodiment, all of these processes are performed by the CODEC 3a, and control of each process is performed by the bus controller 32. In this embodiment, a high-speed bus such as a PCI bus is used as the bus 5.
[0022]
Hereinafter, the operation of the present embodiment will be described. First, when outputting sound to the outside, the CPU 1 secures a memory block of a predetermined size in the memory 2. Then, a predetermined amount of PCM audio data is read from a hard disk device or the like, and stored in this memory block. Next, the CPU 1 outputs information such as the start address of the memory block, the range, the number of data bits of the PCM audio data, and the sampling frequency when performing D / A conversion, and the information is transmitted to the CPU interface 31 in the CODEC 3a. This is set in the bus controller 32 via
[0023]
When this initialization is completed, the bus controller 32 acquires the right to use the bus 5. Then, read addresses are sequentially output using the start address as an initial value, and the PCM audio data in the memory block is read one byte at a time starting from the first one. The read series of PCM audio data is stored in the reproduction FIFO 33 via the bus 5. When the accumulation of a certain amount of PCM audio data is completed, the bus 5 is released. On the other hand, the bus controller 32 generates a sampling clock having the sampling frequency set by the initial setting. Then, in synchronization with the sampling clock, PCM audio data is extracted from the reproduction FIFO 33, converted into an analog audio signal by the D / A converter 35, and output to an external device. As the output operation proceeds, the number of PCM audio data stored in the reproduction FIFO 33 decreases, but the vacancy state in the reproduction FIFO 33 is monitored by the bus controller 32. When a certain free area is generated in the reproduction FIFO 33, the PCM audio data is read from the memory block again by the bus controller 32 and supplied to the reproduction FIFO 33. Hereinafter, similarly, every time a certain free area is generated in the reproduction FIFO 33, the PCM audio data is read from the memory block and is supplemented to the reproduction FIFO 33.
[0024]
When all the PCM audio data in the memory 2 has been read, an interrupt signal is sent from the bus controller 32 to the CPU 1 via the CPU interface 31. As a result, a predetermined amount of PCM audio data is stored again in the memory block in the memory 2, and information such as the start address and range of the memory block is set in the bus controller 32. Then, as described above, the PCM audio data is supplied to the reproduction FIFO 33, and the PCM audio data is converted into an analog audio signal at a fixed sampling frequency. By repeating the above operation, a sound for a long time is reproduced.
[0025]
On the other hand, the process of storing the voice fetched from outside as PCM voice data in a hard disk device or the like is performed as follows. First, the CPU 1, the memory blocks of a predetermined size in the memory 2 is secured as buffers for temporarily storing PCM audio data. Then, information specifying the start address and range of the memory block, the number of bits of the PCM audio data, and information specifying the sampling frequency at the time of A / D conversion are output and initialized in the bus controller 32 in the CODEC 3a. .
[0026]
When the initialization is completed, the bus controller 32 generates a sampling clock having the sampling frequency set by the initialization. In the A / D converter 36, an external analog audio signal is sequentially converted into PCM audio data in synchronization with the sampling clock, and is stored in the recording FIFO 34. When a predetermined amount of PCM audio data is accumulated in the recording FIFO 34, the bus controller 32 acquires the right to use the bus 5. Then, the PCM audio data in the recording FIFO 34 is read and sequentially written to the memory block via the bus 5. When a certain free area is secured in the recording FIFO 34, the supply of the PCM audio data to the memory block is stopped, and the bus 5 is released. Thereafter, similarly, every time a predetermined amount of PCM audio data accumulates in the recording FIFO 34, the bus controller 32 reads the PCM audio data from the recording FIFO 34 and stores it in a memory block.
[0027]
When the memory block is filled with the PCM audio data, an interrupt signal is sent from the bus controller 32 to the CPU 1 via the CPU interface 31. As a result, the CPU 1 secures another new memory block, and sets information specifying a start address and a range of the memory block in the bus controller 32. Thereafter, the PCM audio data read from the recording FIFO 34 is stored in the newly secured memory block. While the PCM audio data is stored in the new memory block, the PCM audio data is read from the memory block that has been used so far and stored in the hard disk device or the like. When the newly secured memory block is filled with the PCM audio data, the memory block is secured again, and the above operation is repeated.
[0028]
As described above, the configuration in which the reproduction FIFO and the recording FIFO are provided in the CODEC 3a has been described as an example. However, these FIFOs are not provided, and each time a sampling clock is generated, the memory 2 and the D / A converter 35 or A / D converter PCM audio data may be exchanged with the device 36. However, in the case of this configuration, every time transmission and reception of PCM audio data is performed once, control such as acquisition of the right to use the bus is required, and wasteful time during which data cannot be transferred occurs. Further, when another device uses the bus for a long time, the bus controller 32 cannot acquire the right to use the bus, a part of the PCM audio data in the memory is not read (underrun), or the CODEC 3a Some of the PCM audio data generated by the above may not be written to the memory (overrun). Therefore, in order to ensure the bus use efficiency and the operation of reproduction / recording, it is more preferable to provide the FIFO.
[0029]
Although the embodiment in which the present invention is applied to both the reproduction and recording functions of PCM audio data has been described above, the invention may be applied to only the reproduction function. That is, when the PCM audio data is converted to an analog signal and output to the outside, the right to use the bus is acquired under the control of the bus controller, and the PCM audio data to be converted is acquired via the bus. You may. In this case, it is effective to acquire not only the PCM audio data read from the memory but also the PCM audio data generated by the CPU executing the software under the control of the bus controller.
[0030]
【The invention's effect】
As described above, according to the present invention, the acquisition of the right to use the bus necessary for the encoding process and the decoding process, and the transfer of the PCM data to and from the memory are all performed by the bus controller in the codec. Therefore, there is an effect that the encoding process, the decoding process, and the storage and reproduction of the PCM data can be efficiently performed without wasteful control. Further, since there is no need to separately provide a DMAC, there is an effect that the cost of the entire apparatus can be reduced.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a personal computer using a CODEC according to an embodiment of the present invention.
FIG. 2 is a diagram showing a conventional technique.
[Explanation of symbols]
1 ... CPU, 2 ... memory, 5 ... bus,
3a: CODEC (codec), 31: CPU interface,
32 bus controller 33 playback FIFO (buffer means)
34: Recording FIFO (buffer means),
35 D / A converter, 36 A / D converter.

Claims (2)

A process connected to a memory via a bus, encoding an analog signal fetched from outside at a specified sampling frequency, and supplying PCM data obtained by the encoding to the memory via the bus; A codec device for sequentially fetching PCM data from the memory via the memory, converting the PCM data into an analog signal at a designated sampling frequency, and outputting the analog signal to the outside;
First buffer means for storing PCM data obtained by encoding an analog signal taken from the outside;
Second buffer means for accumulating PCM data to be converted into an analog signal, fetched from the memory;
When supplying the PCM data accumulated in the first buffer means to the memory, the CPU connected to the bus secures a memory block of a predetermined size in the memory, and then transmits the data to the first buffer means. Each time a predetermined amount of PCM data is accumulated, the right to use the bus is acquired, and the PCM data is read from the first buffer means until the predetermined amount of free area is secured in the first buffer means. An interrupt signal for requesting the CPU to secure a new memory block when the memory block is filled with PCM data while repeating the process of transferring to the memory block via the bus and releasing the right to use the bus. While sending
When converting the PCM data stored in the second buffer means to an analog signal and outputting the analog signal to the outside, the CPU connected to the bus secures a memory block of a predetermined size in the memory, and After the PCM data is stored in the second buffer means, every time a predetermined amount of free area is secured in the second buffer means, the right to use the bus is acquired, and the predetermined amount of PCM data is accumulated in the second buffer means. Until the PCM data is read from the memory block and transferred to the second buffer means via the bus, the process of releasing the right to use the bus is repeated, and all the PCM data in the memory block is read. When, and a bus controller for sending an interrupt signal for requesting the CPU to store the new PCM data to said memory block Codec device, characterized by Bei. The bus controller, when converting the PCM data stored in the second buffer means into an analog signal and outputting the analog signal to the outside, stores the start address of the secured memory block and the information indicating the range. 2. The codec according to claim 1, wherein the codec is obtained from a CPU, and the PCM data is read from the memory block based on the obtained start address and information indicating the range.

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