JP2001159957A - Method and device for controlling memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve a problem that complicated arbitration processing has to be executed in the case of recording a video/sound signal of variable data length. SOLUTION: An access period is fixed on a fixed value, and when data of transfer time shorter than the fixed period arrive, access is interrupted but the period is held at the fixed period. In the case of access of the succeeding period, the access is performed only in the period that the access is interrupted and the access period is always held at the fixed period similarly to the case interrupting the access.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory control method and apparatus in a digital recording / reproducing apparatus.

[0002]

2. Description of the Related Art A conventional memory control device is disclosed in
An apparatus described in “Digital recording / reproducing apparatus” in JP-A-9-65283 is known. FIG. 6 is a block diagram of a memory control device similar to the conventional memory control device. This memory control device is a DRAM 5 which is a main memory and stores one address and two bytes for storing one frame of data.
1 and a main memory control unit 50 for controlling the DRAM 51
And The control method of the main memory control unit 50 includes an access request signal (FIG. 7) as shown in the timing chart of FIG.
In response to the REQ waveform (high level), an access acknowledgment signal (ACK waveform high level in FIG. 7) is output to write and read data. In the timing chart of "DATA access" in FIG. 7, the hatched portion indicates a period during which data is not written or read, and writing or reading is performed during a white portion without hatching. A signal recording processing unit 52 for converting an analog audio video signal into a sync block and a signal reproduction processing unit 53 for converting a sync block into an analog audio video signal are connected to the main memory control unit 50 via the first adjustment memory 6. Have been.
At the time of the recording operation, the signal recording processing section 52 receives the analog audio video signal, outputs a 77-byte sync block to the first adjustment memory 6 and stores it, and outputs a signal (represented as Req) indicating an access request. Output to the main memory control unit 50. Upon receiving a signal indicating access approval (indicated as Ack) from the main memory control unit 50, the sync block stored in the first adjustment memory 6 is output to the main memory control unit 50. At the time of the reproduction operation, the signal reproduction processing unit 53 outputs the access request signal (Req) to the main memory control unit 50 in advance, and upon receiving the access acknowledgment signal (Ack), transmits the 77-byte sync block output from the DRAM 51 to the first block. 1 is stored in the adjustment memory 6. When necessary, the sync block is input from the first adjustment memory 6 to output an analog audio video signal.

[0003] An inner code parity adding section 54 for adding inner code parity to a sync block to be recorded and an inner code error correction processing section 55 for performing inner code error correction processing of a reproduced sync block are provided with a main code beforehand during a recording operation. An access request signal (Req) is output to the memory control unit 50. Upon receiving the access approval signal (Ack), the 77-byte sync block output from the main memory control unit 50 is stored in the second adjustment memory 7. When necessary, the inner code error correction processor 55 reads out and inputs the sync block from the adjustment memory 7, and outputs an 85-byte sync block to which the inner code parity is added. During the reproducing operation, an 85-byte sync block is input, and the 77-byte sync block after the inner code error correction process is output to the second adjustment memory 7 and stored. Then, it outputs the access request signal (Req) to the main memory control unit 50 and, when receiving the access acknowledgment signal (Ack), outputs the sync block stored in the second adjustment memory 7 to the main memory control unit 50.

[0004]

In this memory control device, it is required that the data length of the video / audio signal processing in the signal recording processing unit 52 and the signal reproduction processing unit 53 be the same as the data length of the recording signal. ing. Therefore, the conventional method has a problem that a video / audio signal having a variable data length such as MPEG cannot be recorded.
Further, there is a problem that a remarkable difference occurs in the data lengths of video and audio, and complicated arbitration processing must be performed for controlling the temporary save memory (DRAM 51 in FIG. 13). SUMMARY OF THE INVENTION An object of the present invention is to simplify the control of a temporary save memory generally realized in an SDRAM when the data length of video / audio signal processing and the data length of a recording signal are different from each other in memory control in a digital recording / reproducing apparatus. I do.

[0005]

A memory control method according to the present invention is a digital recording / reproducing method for digitizing a video signal and an audio signal, temporarily storing the digitized video signal and the audio signal in a memory, and then recording and reproducing the digital signal. Alternatively, the memory is accessed in a predetermined period irrespective of the digital data length from the recording medium. Accordingly, even when the data length of the video / audio signal processing unit and the data length of the recording signal are different from each other, the memory is accessed during a predetermined period, so that the data transfer is always performed at a constant cycle. And the control of the temporary save memory is simplified. A memory control method according to another aspect of the present invention is a digital recording / reproducing method for digitizing a video signal and an audio signal, temporarily storing the digitized video signal and the audio signal in a memory, and then recording and reproducing the video signal and the audio signal in a predetermined period based on a format of the audio signal. A memory is accessed, and the memory is accessed while arbitrating digital data of a video signal or digital data from a recording medium in the predetermined period. A memory control method according to another aspect of the present invention is a digital recording / reproducing method for digitizing a video signal and an audio signal, temporarily storing the digitized video signal and the audio signal in a memory, and then recording and reproducing the video signal and the audio signal in a predetermined period based on a format of the audio signal. A memory is accessed, and access is made so that digital data of a video signal or digital data from a recording medium is intermittently written to the memory. A memory control method according to another aspect of the present invention is a digital recording / reproducing method for digitizing a video signal and an audio signal, temporarily storing the digitized video signal and the audio signal in a memory, and then recording and reproducing the video signal and the audio signal in a predetermined period based on a format of the audio signal. When accessing the memory and intermittently accessing the memory to process digital data of a video signal or digital data from a recording medium, if input / output of the digital data is completed during access, It is characterized in that access is forcibly stopped (data writing and reading are interrupted in the middle of the period). A memory control method according to another aspect of the present invention includes:
In a digital recording / reproducing method for recording and reproducing after digitizing a video signal and an audio signal and temporarily storing the same in a memory, the memory is accessed for a predetermined period based on the format of the audio signal, and the digital data of the video signal or When accessing the memory intermittently to process digital data from a recording medium, if the digital data is terminated in the middle of the access, the access to the memory is forcibly stopped and the access cycle is kept constant while the memory is empty. Access (accessing and writing zero data to memory, and storing read data)
It is characterized by doing. A memory control method according to another aspect of the present invention is a digital recording / reproducing method for digitizing a video signal and an audio signal, temporarily storing the digitized video signal and the audio signal in a memory, and then recording and reproducing the video signal and the audio signal in a predetermined period based on a format of the audio signal. When accessing the memory and intermittently accessing the memory to process digital data of a video signal or digital data from a recording medium, if the digital data ends in the middle of the access, the access to the memory is forcibly performed. In addition to the stop, the idle access is performed while keeping the access cycle constant, and in the digital data access in the next period, the access is performed only to the part not accessed by the forced stop. A memory control method according to another aspect of the present invention is a digital recording / reproducing method for digitizing a video signal and an audio signal, temporarily storing the digitized video signal and the audio signal in a memory, and then recording and reproducing the video signal and the audio signal. When accessing the memory and intermittently accessing the memory to process digital data of a video signal or digital data from a recording medium, if the digital data ends in the middle of the access, the access to the memory is forcibly performed. While stopping, the idle access is performed while keeping the access cycle constant, and in the digital data access in the next period, access is performed only to the part that has not been accessed due to the forced stop, and the access cycle is kept constant. It is characterized in that an empty access is made when digital data is completed. A memory control device according to the present invention includes a first adjustment memory, a video compression processing unit connected to a main memory control unit, and a second adjustment memory, and an audio compression process connected to a main memory control unit. Unit, an SDRAM connected to the main memory control unit, and a modulation processing unit connected to the main memory control unit via a third adjustment memory, wherein the main memory control unit includes the video compression processing unit, The SDRAM is accessed for a predetermined period irrespective of the digital data length in the audio compression processing section or the modulation processing section.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A preferred embodiment of the present invention will be described below with reference to FIGS. The memory control device of each embodiment is used for a digital recording / reproducing device.

FIG. 1 is a block diagram of a memory control device according to a first embodiment. FIG. 2 is a timing chart showing the operation. The first embodiment relates to processing of a video signal. In FIG. 1, a main memory control unit 1 includes a video compression processing unit 2, an audio compression processing unit 3, a modulation / demodulation processing unit 4, an SDRAM 5 as a temporary save memory, a first adjustment memory 6, a second adjustment memory 7, And a third adjustment memory 8 are connected. The main memory controller 1 responds to the access request signal Req (the high-level portion of the waveform REQ in FIG. 2) with the access acknowledgment signal Ack (the waveform AC in FIG. 2).
(High-level portion of K) is output to write and read data. In the timing diagram of "DATA access" in FIG. 2, a hatched portion indicates a period during which data is not written or read, and a white portion without a hatch indicates a period during which data is written or read.

[0008] The video compression processor 2 compresses an analog video signal to 4 Mbps and converts it into digital data.
Similarly, the audio compression processing unit 3 quantizes the analog audio signal with 16 bits, compresses the signal to 18 Kbps, and converts the signal into digital data.

At the time of the recording operation, the video compression processing unit 2
The compressed digital data is written into the adjustment memory 6 of FIG. Similarly, the audio compression processing unit 3 includes the second adjustment memory 7
The compressed digital data is written at a data rate determined by the compression format. The video compression processing unit 2
When digital data is stored in the first adjustment memory 6, an access request signal R is sent to the main memory control unit 1.
eq is output. Similarly, when digital data is stored in the second adjustment memory 7, the audio compression processing unit 3 outputs an access request signal Req to the main memory control unit 1. The main memory control unit 1 sends an access acknowledgment signal Ack to either of the access request of the video compression processing unit 2 and the access request of the audio compression processing unit 3. Thus, the main memory control unit 1 reads the digital data dd from the adjustment memory of the processing unit that has sent the access approval signal Ack, and writes the digital data dd into the SDRAM 5.

In the present invention, the period during which the access acknowledgment signal is issued (hereinafter, referred to as an access period) is set to a predetermined multiple of the basic clock of the apparatus shown in FIG. 1 (hereinafter, referred to as fixed). In this embodiment, the length of the period shown in the access period in FIG. 2 is defined by 16 × 4 = 64 clocks which are four times the length of the quantization bit number 16 of the audio compression processing unit 3. Fixed period. Thereby, the main memory control unit 1 continues the access request signal Req (the high-level portion of REQ in FIG. 2) from the video compression processing unit 2 in which the number of data per unit time is much larger than the audio compression processing unit 3. In this case, as shown by the high level of the ACK signal in FIG. 2, the period of the access acknowledgment signal Ack is fixed to 64 clock periods of the audio compression processing unit 3. As a result, the access acknowledgment signal Ack goes high intermittently, and the digital data dd stored in the first adjustment memory 6 is sequentially written into the SDRAM 5 within each period of the white portion in the DATA access signal of FIG. It is. This allows
Even when the data length of the video signal compression processing unit and the data length of the recording signal are different from each other, data transfer is always performed at a constant cycle. Therefore, control of the temporary save memory shown as SDRAM 5 in FIG. 1 is simplified. At the time of reproduction, the digital data dd stored in the SDRAM 5 is transferred to the first adjustment memory 6 or the audio compression processing unit 3 of the video compression processing unit 2 in response to an access request from the video compression processing unit 2 or the audio compression processing unit 3. Is written to the second adjustment memory 7. That is, since the process is substantially the reverse of the process at the time of recording, detailed description is omitted.

<< Second Embodiment >> The configuration of the memory control device of the second embodiment is the same as that of the first embodiment shown in FIG. 1 and will be described with reference to FIG. The second embodiment relates to processing of an audio signal, and the operation will be described with reference to FIG. The main memory controller 1 writes and reads data by outputting an access acknowledgment signal (high level of the ACK waveform in FIG. 2) in response to the access request signal (high level in the REQ waveform in FIG. 2).

The audio compression processing section 3 quantizes the analog audio signal with 16 bits, compresses the signal to 18 Kbps, and converts it into digital data dd. Similarly, the modulation / demodulation processing unit 4 records and reproduces the digital signal on a recording medium (not shown) at a data rate of 9 Mbps.

At the time of the recording operation, the audio compression processing unit 3
At the data rate of the compressed digital data dd. When the digital data dd is stored in the second adjustment memory 7, the audio compression processing unit 3 sends an access request signal (Req) to the main memory control unit 1.
Is output. When sufficient data is stored in the SDRAM 5, the modulation / demodulation processing unit 4 outputs an access request signal (Req) to the main memory control unit 1.

The main memory control unit 1 sends an access acknowledgment signal (Ack) to one of the audio compression processing unit 3 and the modulation / demodulation processing unit 2 in response to the access request.
When sending an access approval signal (Ack) to the audio compression processing unit 3, the main memory control unit 1 reads the digital data dd from the second adjustment memory 7, writes the digital data dd into the SDRAM 5, and sends the access approval signal to the modulation / demodulation processing unit 4. (Ack)
Is sent, the digital data d
d is read out and written into the third adjustment memory 8. When the digital data dd is stored in the third adjustment memory 8, the modulation / demodulation processing unit 4 reads out the digital data dd and performs processing.

At this time, the period during which the access approval is issued is set to 16 based on the number of quantization bits 16 of the audio compression processing unit 3.
X4 = fixed to a period of 64 clocks (access period in FIG. 2). Thereby, the main memory control unit 1 can send the access approval signal (ACK in FIG. 2) even if the access request signal of the video compression processing unit 2 having a large number of data per unit time is always output (REQ in FIG. 2). In order to fix the period to 64 clocks of the audio compression processing unit 3, the access approval is output intermittently and the digital data dd stored in the first adjustment memory 6 is sequentially written into the SDRAM 5. Thereby, even when the data length of the audio signal processing unit and the data length of the recording signal are different from each other, the data transfer is always performed for a fixed period, so that the control of the temporary save memory shown as the SDRAM 5 in FIG. Be transformed into At the time of reproduction, the digital data dd stored in the SDRAM 5
Is written to the first adjustment memory 6 of the video compression processor 2 or the second adjustment memory 7 of the audio compression processor 3 in response to an access request from the video compression processor 2 or the audio compression processor 3. That is, since the process is substantially the reverse of the process at the time of recording, detailed description is omitted.

<< Third Embodiment >> The configuration of a third embodiment is shown in FIG.
Since this is the same as the first embodiment shown in FIG. FIG. 3 is a timing chart showing the operation. Third
The second embodiment relates to processing of a video signal when the digital data dd compressed by the video compression processor 2 is more than 64 bytes and not a multiple of 64. The main memory control unit 1 outputs an access acknowledgment signal (ACK high level in FIG. 3) in response to the access request signal (REQ high level in FIG. 3) to write and read data. In the timing chart of "DATA access" in FIG. 3, a hatched portion indicates a period during which data is not written or read, and a white portion without a hatch indicates a period during which data is written or read.

The video compression processor 2 compresses an analog video signal to 4 Mbps and converts it into digital data dd. Similarly, the audio compression processing unit 3 quantizes the analog audio signal with 16 bits, compresses the analog audio signal to 18 Kbps, and converts it into digital data dd.

At the time of the recording operation, the video compression processing unit 2
Compressed digital data dd is written into the adjustment memory 6 of FIG. Similarly, the audio compression processing unit 3 includes the second adjustment memory 7
Is written at a predetermined data rate. When the digital data dd is stored in the first adjustment memory 6, the video compression processing section 2 outputs an access request signal (Req) to the main memory control section 1. Similarly, when the digital data dd is stored in the second adjustment memory 7, the audio compression processing unit 3 outputs an access request signal (Req) to the main memory control unit 1. The main memory control unit 1 responds to the access request of the video compression processing unit 2 and the access request of the audio compression processing unit 3,
An access acknowledgment signal (Ack) is sent to either of them, and the digital data dd is read out from the adjustment memory 6 or 7 of the processing unit that sent the access acknowledgment, and written into the SDRAM 5.

At this time, the period during which the access acknowledgment signal is output (Ack in FIG. 3) is fixed to a period of 16 × 4 = 64 clocks (access period in FIG. 3). Thus, even if the access request of the video compression processing unit 2 having a large number of data per unit time is always issued, the main memory control unit 1 sets the period of the access approval signal (ACK in FIG. 3) to the audio compression processing unit. 3 is fixed to 64 clocks, the access approval is output intermittently, and the digital data dd stored in the first adjustment memory 6 is sequentially written to the SDRAM 5.

The data length of the digital data dd compressed by the video compression processor 2 is not always a multiple of 64 bytes. For example, 74 bytes (64 + 1
If there is data of 0), 64 bytes of data are transferred in the first period. In the next period, 10-byte data is transferred. In this case, one of the 64-byte transfer periods is transferred.
Transfer is performed during the period of 0 bytes, and the difference between 64 and 10 is 54
For a period of bytes, no data transfer is performed, an empty access is performed, and a period of 64 clocks is maintained. An empty access refers to accessing the memory but not storing the data, or storing zero-valued data and discarding the read data. Thereby, even when the data length of the video signal processing unit and the data length of the recording signal are different from each other, the data transfer is always performed for a fixed period, so that the control of the temporary save memory shown as the SDRAM 5 in FIG. Be transformed into At the time of reproduction, the digital data dd stored in the SDRAM 5 is transferred to the video compression processing unit 2.
Alternatively, in response to an access request from the audio compression processing unit 3, the data is written to the first adjustment memory 6 of the video compression processing unit 2 or the second adjustment memory 7 of the audio compression processing unit 3. That is, a process substantially the same as the above-described process at the time of recording is performed, and a detailed description thereof will be omitted.

<< Fourth Embodiment >> The configuration of a memory control device according to a fourth embodiment is the same as that of the first embodiment shown in FIG. 1 and will be described with reference to FIG. FIG. 4 is a timing chart showing the operation. The fourth embodiment relates to the processing of an audio signal when the digital data dd compressed by the modulation / demodulation processing unit 4 is more than 64 bytes and not a multiple of 64. The main memory control unit 1 issues an access request signal (FIG. 4)
In response to the high level of REQ, an access acknowledge signal (high level of ACK in FIG. 4) is output to perform data writing and reading. In the timing diagram of "DATA access" in FIG. 4, a hatched portion indicates a period during which data is not written or read, and a white portion without a hatch indicates a period during which data is written or read.

The audio compression processing section 3 quantizes the analog audio signal with 16 bits, compresses the signal to 18 Kbps, and converts it into digital data dd. Similarly, the modulation / demodulation processing unit 4 records and reproduces the digital signal on a recording medium at a rate of 9 Mbps.

At the time of the recording operation, the audio compression processing unit 3
The compressed digital data dd is written into the adjustment memory 7 at a predetermined data rate. When the digital data dd is stored in the second adjustment memory 7, the voice compression processing unit 3
An access request signal (Re
q) is output. Conversely, if sufficient data has been stored in the SDRAM 5, the modulation / demodulation processing unit 4 outputs an access request signal (Req) to the main memory control unit 1.

In response to the access request from the audio compression processing section 3 and the access request from the modulation / demodulation processing section 4, the main memory control section 1 sends an access approval to either of them. When the access approval signal (Ack) is sent to the audio compression
Read digital data dd from the adjustment memory 7 of
Write to DRAM5. When the access approval signal (Ack) is sent to the modulation / demodulation processing unit 4, the digital data dd is read out from the SDRAM 5 and written into the third adjustment memory 8.

When the digital data dd is stored in the third adjustment memory 8, the modulation / demodulation processing section 4 reads out the data and performs processing. At this time, the period for issuing the access approval is 16 × 4 =
It is fixed to a period of 64 clocks (access period in FIG. 4). Therefore, even if the access request signal of the modulation / demodulation processing unit 4 having a large number of data per unit time is always output (high level of REQ in FIG. 4), the main memory control unit 1 performs the audio compression processing on the access approval period. In order to fix to 64 bits of the unit 3, an access acknowledge signal is output intermittently (ACK high level in FIG. 4) and the digital data dd stored in the first adjustment memory 6 is sequentially written to the SDRAM 5 (FIG. 4 DATA access white part).

The data length of the digital data dd compressed by the modulation / demodulation processing unit 4 is not always a multiple of 64. For example, if there is 74 bytes (64 + 10) of data, 64 bytes are transferred in the first period.
In the next period, 10-byte data is transferred. In this case, transfer is performed for a period of 10 bytes out of the 64-byte transfer period, and an empty access is performed for a 54-byte period that is the difference between 64 and 10. And the periodicity of 64 clocks is maintained. As a result, even when the data length of the audio signal processing unit and the data length of the recording signal are different from each other, the data transfer is always performed for a fixed period.
The control of the temporary save memory shown as 5 is simplified.
At the time of reproduction, the digital data dd stored in the SDRAM 5 is transferred to the first adjustment memory 6 or the audio compression processing unit 3 of the video compression processing unit 2 in response to an access request from the video compression processing unit 2 or the audio compression processing unit 3. Is written to the second adjustment memory 7. That is, a process substantially the same as the above-described process at the time of recording is performed, and a detailed description thereof will be omitted.

<< Fifth Embodiment >> The configuration of the memory control device of the fifth embodiment is the same as that of the first embodiment shown in FIG. 1 and will be described with reference to FIG. FIG. 4 is a timing chart showing the operation. The fifth embodiment relates to processing of a video signal when the data amount changes. The main memory control unit 1 outputs an access acknowledgment signal (ACK high level in FIG. 4) in response to the access request signal (REQ high level in FIG. 4) to write and read data.

The video compression processor 2 compresses an analog video signal to 4 Mbps and converts it into digital data dd. Similarly, the audio compression processing unit 3 quantizes the analog audio signal with 16 bits, compresses the signal to 18 Kbps, and converts it into digital data dd.

At the time of the recording operation, the video compression processing unit 2
Compressed digital data dd is written into the adjustment memory 6 of FIG. Similarly, the audio compression processing unit 3 includes the second adjustment memory 7
Is written at a predetermined data rate. When the digital data dd is stored in the first adjustment memory 6, the video compression processing section 2 outputs an access request signal (Req) to the main memory control section 1. Similarly, when the digital data dd is stored in the second adjustment memory 7, the audio compression processing unit 3 outputs an access request signal (Req) to the main memory control unit 1. The main memory control unit 1 responds to the access request of the video compression processing unit 2 and the access request of the audio compression processing unit 3,
An access acknowledgment signal (Ack) is sent to one of them, and the digital data dd is read out from the adjustment memory of the processing unit that sent the access acknowledgment signal (Ack), and written to the SDRAM 5.

At this time, the period for issuing the access acknowledgment signal (Ack) is fixed to a period of 16 × 4 = 64 clocks. The main memory control unit 1 sets the period of the access acknowledgment signal (Ack in FIG. 4) to 16 times even if the access request of the video compression processing unit 2 having a large number of data per unit time is always issued. In order to fix to × 4 bits, the access acknowledge signal is output intermittently (ACK high level in FIG. 4), and the digital data dd stored in the first adjustment memory 6 is sequentially written to the SDRAM 5.

However, the data length of the digital data dd compressed by the video compression processor 2 is not always a multiple of 64 bytes. For example, if there is 74 bytes of data, 64 bytes of the data are transferred in the first period. In the next period, transfer of 10-byte data of the difference between 74 and 64 is performed. In this case, transfer is performed for a period of 10 bytes in the transfer period of 64 bytes, and 64 and 1 are transferred.
In the 54-byte period of the difference of 0, an empty access is performed, and the periodicity of 64 clocks is maintained.

As time advances, the next input digital data d
If d is 80 bytes, the first access
Access is performed during the 54-byte period of the last empty access, and empty access is performed during the 10-byte period.
This maintains the periodicity of 64 clocks. In the next period, access is made to 64 bytes of data out of the remaining 70 bytes of the difference between 80 and 10, and in the next period, the remaining (70-64) = 6 bytes are accessed, and (6)
4-6) = 58 bytes are accessed empty. Thus, the periodicity of 64 clocks is not always broken. At the time of reproduction, the digital data dd stored in the SDRAM 5
Is written to the first adjustment memory 6 of the video compression processor 2 or the second adjustment memory 7 of the audio compression processor 3 in response to an access request from the video compression processor 2 or the audio compression processor 3. That is, a process substantially the same as the above-described process at the time of recording is performed, and a detailed description thereof will be omitted. This allows
Even when the data length of the video signal processing unit and the data length of the recording signal are different from each other, the data transfer is always performed for a fixed period, so that the control of the temporary save memory shown as the SDRAM 5 in FIG. 1 is simplified. .

<< Sixth Embodiment >> The memory control device of the sixth embodiment is the same as that of the first embodiment shown in FIG.
This will be described with reference to FIG. FIG. 5 is a timing chart of the operation. The sixth embodiment relates to processing of an audio signal when the data amount changes. The main memory control unit 1 outputs an access acknowledgment signal (ACK high level in FIG. 5) in response to the access request signal (REQ high level in FIG. 5) to write and read data. "D" in FIG.
In the timing chart of "ATA access", a hatched portion indicates a period during which data is not written or read, and a white portion without a hatch indicates a period during which data is written or read. The audio processing unit 3 quantizes the analog audio signal with 16 bits, compresses the signal to 18 Kbps, and converts the signal into digital data dd. The modulation / demodulation processing unit 4 records and reproduces the digital signal on a recording medium at a rate of 9 Mbps.

At the time of the recording operation, the audio compression processing unit 3
The compressed digital data dd is written into the adjustment memory 7 at a predetermined data rate. The audio compression processing unit 3
When the digital data dd is stored in the adjustment memory 7, an access request signal (Req) is output to the main memory control unit 1. When sufficient data is stored in the SDRAM 5, the modulation / demodulation processing unit 4 outputs an access request signal (Req) to the main memory control unit 1.

The main memory control unit 1 sends an access acknowledgment signal (Ack) to one of the voice compression processing unit 3 and the modulation / demodulation processing unit 2 in response to the access request.
When the access acknowledgment signal (Ack) is sent to the audio compression processing unit 3, the digital data d is read from the second adjustment memory 7.
d is read and written to SDRAM5. When the access approval signal (Ack) is sent to the modulation / demodulation processing unit 4, the SDRA
The digital data dd is read from M5 and written into the third adjustment memory 8. The modulation / demodulation processing unit 4 includes a third adjustment memory 8
When the digital data dd is stored in the memory, it is read out and processed.

At this time, the period for issuing the access acknowledgment signal (Ack) is fixed to a period of 16 × 4 = 64 clocks (access period in FIG. 5). The main memory control unit 1 receives the access acknowledgment signal (FIG. 4
Of the audio compression processing unit 3
In order to fix to 4 bits, an access approval signal (A in FIG. 4)
(CK high level) is output intermittently and the digital data dd stored in the first adjustment memory 6 are sequentially converted to SDRA data.
Write to M5.

However, the data length of the digital data dd compressed by the modulation / demodulation processing unit 4 is not always a multiple of 64. For example, 74 bytes (64 + 1
If there is data of 0), 64 bytes of data are transferred in the first period. In the next period, 10-byte data is transferred. In this case, one of the 64-byte transfer periods is transferred.
Transfer is performed during the period of 0 bytes, and the difference between 64 and 10 is 54
During the byte period, empty access is performed, and the periodicity of 64 clocks is maintained.

As time advances, the next digital data dd
However, if it is 80 bytes, in the first access, access is performed during the 54-byte period of the last empty access, and empty access is performed during the 10-byte period, thereby maintaining the periodicity of 64 clocks. . Then the remaining (80
-10) = 64 bytes of 70 bytes of data are accessed, and in the next period, the remaining (70−64) = 6 bytes of data are accessed.
(64-6) = Empty access is performed for a period of 58 bytes. Thus, the periodicity of 64 clocks is always maintained.
Accordingly, even when the data length of the audio signal processing unit and the data length of the recording signal are different from each other, the data transfer is always performed in a fixed period, so that the control of the temporary save memory is simplified. At the time of reproduction, the digital data dd stored in the SDRAM 5 is transferred to the first adjustment memory 6 or the audio compression processing unit 3 of the video compression processing unit 2 in response to an access request from the video compression processing unit 2 or the audio compression processing unit 3. Is written to the second adjustment memory 7. That is, a process substantially the same as the above-described process at the time of recording is performed, and a detailed description thereof will be omitted.

[0039]

According to the present invention, as described in detail in the above embodiments, the access period is always kept constant even when the data length of the video / audio signal processing and the data length of the recording signal are different. The effect is obtained that control of the temporary save memory can be simplified.

[Brief description of the drawings]

FIG. 1 is a block diagram of a memory control device common to first to sixth embodiments;

FIG. 2 is a timing chart showing the operation of the first and second embodiments.

FIG. 3 is a timing chart of the third and fourth embodiments.

FIG. 4 is a timing chart showing the operation of the fifth embodiment.

FIG. 5 is a timing chart showing the operation of the sixth embodiment.

FIG. 6 is a block diagram of a conventional memory control device.

FIG. 7 is a timing chart showing the operation of the conventional memory control device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Main memory control part 2 Video compression processing part 3 Audio compression processing part 4 Modulation / demodulation processing part 5 SDRAM 6 First adjustment memory 7 Second adjustment memory 8 Third adjustment memory 50 Main memory control part 51 DRAM 52 Signal recording processing Unit 53 signal reproduction processing unit 54 inner code parity adding unit 55 inner code error correction processing unit

 ──────────────────────────────────────────────────の Continued on the front page (72) Inventor Eiji Yamauchi 1006 Kazuma Kadoma, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. F term (reference) 5B065 BA05 CC08 5D044 AB05 AB07 DE02 EF03 FG10 GK08

Claims (13)

[Claims] A digital recording / reproducing method for digitizing a video signal and an audio signal, temporarily storing the digitized video signal and audio signal in a memory, and then recording / reproducing the digital signal. A memory control method, wherein the memory is accessed for a predetermined period. 2. A digital recording / reproducing method for digitizing a video signal and an audio signal, temporarily storing the digitized video signal and the audio signal in a memory, and recording / reproducing the video signal and the audio signal in a predetermined period based on a format of the audio signal. Arbitration of the digital data of the above or the digital data from the recording medium in the predetermined period.
A memory control method for accessing the memory while performing the operations. 3. A digital recording / reproducing method for digitizing a video signal and an audio signal, temporarily storing the digitized video signal and the audio signal in a memory, and then recording / reproducing the digital signal and the audio signal in a predetermined period based on a format of the audio signal. A memory control method characterized by intermittently accessing so that digital data of a signal or digital data from a recording medium is written into said memory. 4. An access method for intermittently writing digital data of a video signal or digital data from a recording medium to a memory during a period different from a predetermined period based on a format of an audio signal. The memory control method according to claim 3. 5. A digital recording / reproducing method for digitizing a video signal and an audio signal, temporarily storing the digitized video signal and the audio signal in a memory, and then recording / reproducing the video signal and the audio signal in a predetermined period based on a format of the audio signal. When accessing the memory intermittently to process digital data of a signal or digital data from a recording medium, if the input / output of the digital data is completed during the access, the access to the memory is forcibly stopped (for a period of time). Stopping data writing and reading in the middle). 6. The method according to claim 1, wherein the memory is intermittently accessed for digital data of the video signal or digital data from the recording medium during a period different from the predetermined period based on the format of the audio signal. 6. The memory control method according to 5. 7. A digital recording / reproducing method for digitizing a video signal and an audio signal, temporarily storing the digitized video signal and the audio signal in a memory, and then recording and reproducing the video signal and the audio signal in a predetermined period based on a format of the audio signal. When accessing the memory intermittently to process digital data of a signal or digital data from a recording medium, if the digital data is terminated in the middle of the access, the access to the memory is forcibly stopped, and the access cycle is reduced. A memory control method characterized by performing empty access (writing zero data to a memory and storing read data) while maintaining a constant value. 8. When a memory is intermittently accessed for digital data of a video signal or digital data from a recording medium in a period different from a predetermined period based on a format of an audio signal, an empty access is performed in a period M. 8. The memory control method according to claim 7, wherein 9. A digital recording / reproducing method for digitizing a video signal and an audio signal, temporarily storing the digitized video signal and the audio signal in a memory, and then recording / reproducing the video signal and the audio signal in a predetermined period based on a format of the audio signal. When accessing the memory intermittently to process digital data of a signal or digital data from a recording medium, if the digital data is terminated in the middle of the access, the access to the memory is forcibly stopped and the access cycle is reduced. A memory control method characterized by performing idle access while keeping constant, and in digital data access in the next period, performing access only to a portion not accessed by the forced stop. 10. When intermittently accessing a memory for digital data of a video signal or digital data from a recording medium in a second period different from the first period based on a format of an audio signal. When the digital data is terminated during access, the access to the memory is forcibly stopped in a third period shorter than the second period, and the remaining second period is kept constant while the second period is kept constant. 10. An idle access is performed only during a period equal to the difference between the second period and the third period, and access is performed during a next period only during a period equal to the difference between the second period and the third period.
3. The memory control method according to 1. 11. A digital recording / reproducing method for digitizing a video signal and an audio signal, temporarily storing the digitized video signal and the audio signal in a memory, and then recording and reproducing the video signal and the audio signal in a predetermined period based on a format of the audio signal. When accessing the memory intermittently to process digital data of a signal or digital data from a recording medium, if the digital data is terminated in the middle of the access, the access to the memory is forcibly stopped and the access cycle is reduced. In the digital data access in the next period, the access is performed only to the portion not accessed due to the forced stop, and the digital data is terminated while the access cycle is maintained constant. A memory control method characterized by performing empty access. 12. A method of intermittently accessing a memory for digital data of a video signal or digital data from a recording medium in a second period different from the first period based on a format of an audio signal. When the digital data is terminated during access, the access to the memory is forcibly stopped in a third period shorter than the second period, and the remaining second period is kept constant while the second period is kept constant. In the next period, access is performed only during the difference between the second period and the third period, and in this case, the access period is kept constant. 12. The memory control method according to claim 11, wherein when the digital data is completed, a null access is performed. 13. A video compression processing section having a first adjustment memory and connected to a main memory control means, an audio compression processing section having a second adjustment memory and connected to a main memory control means, An SDRAM connected to a main memory control unit; and a modulation processing unit connected to the main memory control unit via a third adjustment memory, wherein the main memory control unit includes the video compression processing unit and the audio compression processing. A memory control device for accessing the SDRAM in a predetermined period irrespective of a digital data length in the unit or the modulation processing unit.