JP2001177419A - Error correction device and program recording medium - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an error correction device that can reduce the power consumption and attain high-speed access to memory data. SOLUTION: The error correction device uses a buffer memory 3 having a plurality of banks that consecutively transfers a burst through bank changeover to suppress increase in the memory capacity, access by each of an inner code data rearrangement means 2, an external code correction means 4 and a data rearrangement means 5 to the buffer memory 3 is assigned at least to two banks in the unit of a divided data group and the burst data are consecutively transferred through bank changeover in the unit of a-word (a is a natural number below a data length of inner code data) to reduce the power consumption and to attain high-speed access to memory data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error correction apparatus having a product code composed of an inner code and an outer code, and a program recording medium.

[0002]

2. Description of the Related Art In recent years, digital processing devices for image data have been rapidly digitized.

For example, a commercial VTR uses an analog recording type beta cam to record a non-compressed digital signal.
1, D2, D3, D5, and a digital betacam that compresses and records video signals by high-efficiency coding, DVC
Like PRO, the transition is from analog to digital and from digital uncompressed to compressed. In addition, in consumer VTRs, a transition has been made from analog VHS to compression DV-VTR in which image data is recorded with high efficiency coding using DCT and Huffman coding.

[0004] A technique called error correction is widely used in these digital VTRs. Digital V
In TR, an error correction code is added during recording and recorded.
At the time of reproduction, an error generated in the tape-head system is removed by decoding the error correction code added at the time of recording.

In general, a product code composed of an outer code and an inner code is used as an error correction code of a digital VTR. In DVCPRO, a product code is configured for each track. FIG. 10 is a schematic diagram of a product code of DVCPRO, and an ID (not shown) for identification is added to each sync block. As shown in the figure, data of 138 sync blocks is written in the row direction of the memory in sync block units, and when writing of all the sync blocks is completed, the data is read out in the row direction of the memory for each word. An outer code parity of 11 words is added and the data is written back to the memory again. In the DVCPRO, since one sync block is composed of 77 words, the above operation is performed 77 times to constitute 77 outer codewords. After adding the outer code parity, 77 words are read in the column direction of the memory, and the inner code parity is added with 8 words.
The above operation is performed for (138 + 11) sync blocks to generate a product code, which is recorded on the magnetic tape.

At the time of reproduction, the reverse process to that at the time of recording is performed. In other words, data reproduced from the magnetic tape is subjected to inner code correction in sync block units. The data with the inner code corrected is written to a predetermined position in the memory. At the time of reproduction, one row of the memory corresponds to one sync block, as at the time of recording. When data of 149 sync blocks has been written per track, the data is read out in the row direction of the memory word by word and the outer code is corrected. The outer code corrected data is stored again at the same address in the memory. By repeating these operations 77 times, the outer code correction for one track is completed. The outer code corrected data is read out again in the row direction in sync block units,
Output as a compressed data bus.

[0007]

However, in the conventional error correction apparatus for performing product code correction which is configured to operate as described above, in performing the inner code correction and the outer code correction, the nature of the processing is limited. Conventionally, since a method of accessing data to be corrected is different, it is conventionally necessary to provide several large-capacity external memories in which random access to the data subjected to the product code correction is relatively easy. It is common and its large-capacity external memory is SRAM or DR.
AM was generally used.

In recent years, there has been a strong demand for higher image quality, and there has been a demand for an error correction device capable of responding to a high image quality video signal called HDTV such as HDTV, and accordingly, the amount of data to be handled has been increasing. I have. For example, in DVCPRO, which is a compressed VTR for broadcasting, the transmission rate is 25 Mbps to 100 Mbps.
s, which is four times as large as the standard quality video signal. This also means an increase in memory and an increase in the speed of access to the memory, which implies an increase in power consumption. Further, in recent years, reduction of power consumption, in combination with prevention of environmental destruction, which has been suddenly shouted, has become a major issue when developing such an apparatus.

However, as described above, the conventional error correction device does not require a storage holding operation as an external memory, but requires an SRA which requires a large amount of power consumption.
Burst transfer for continuous input / output of M and a certain number of memory data cannot be performed, so several DRAMs unsuitable for high-speed access were used. There was a problem that high-speed access to was not possible.

SUMMARY OF THE INVENTION An object of the present invention is to provide an error correction device which reduces the circuit size and power consumption and enables high-speed access to memory data, in consideration of the above-mentioned problems of the conventional error correction device. And a program recording medium.

[0011]

To solve this problem, a first invention (corresponding to claim 1) of the present invention is an inner code correcting means for correcting an inner code of at least two series of data having a product code. And the inner code data corrected by the inner code correcting means is divided into at least two data groups in units of the series, and alternately in units of a data in units of a word [a is the data of the inner code data. Inner number data rearrangement means), a buffer memory having a plurality of banks capable of continuous burst transfer by bank switching, and the output data from the inner code data rearrangement means. Reading the inner code data written in the buffer memory alternately in units of the a word in units of the data group, and obtaining a number of outer codes per data group. Outer code correction means for reading out the outer code word after the outer code correction alternately for each data group in units of the a word, and correcting the outer code by the outer code correction means; The data of the outer codewords written back into the inner code data rearranging means are arranged alternately for each data group in the a word unit so as to be the word arrangement of the inner code data inputted to the inner code data rearranging means. Assigning access to the data rearrangement means to be returned, the inner code data rearrangement means, the outer code correction means, the data rearrangement means, and the buffer memory to at least two banks in units of the data group; An error correction device comprising: a memory control unit of the buffer memory that performs continuous burst transfer by bank switching in word units.

As described above, the increase in memory is suppressed by using a large-capacity memory having a plurality of banks, and the divided data groups are stored in different banks, respectively. By making data input / output a continuous burst transfer by alternately switching banks in a-word units, power consumption can be reduced and high-speed access to memory data can be made possible.

In order to solve this problem, a second invention (corresponding to claim 2) of the present invention is to provide at least two reproduction channels having the same azimuth angle so that a plus azimuth angle and a minus azimuth angle are obtained. Inner code correcting means for correcting inner data of data reproduced from a track recorded at each of two azimuth angles; and inner code data corrected by the inner code by the inner code correcting means, for the track on which the data is reproduced. An inner code that is divided into at least two data groups in the series unit according to the azimuth angle, and alternately rearranged and output in a word units [a is a natural number equal to or less than the data length of the inner code data] for each data group. Data rearranging means, a buffer memory having a plurality of banks capable of continuous burst transfer by bank switching, and said inner code data rearranging means Based on et of the output data, the inner code data written in the buffer memory,
Alternately for each data group, read in units of the a word, correct the outer code by a number of outer codewords per data group, and alternately correct outer codewords after outer code correction for each data group, outer code correcting means for reading out in a word units, and the outer code word data which is outer code corrected by the outer code correcting means and written back to the buffer memory, is inputted to the inner code data rearranging means. Alternately for each data group, so that the word sequence of the inner code data,
The data rearranging means for rearranging in a word units, the inner code data rearranging means, the outer code correcting means, the data rearranging means, and the buffer memory are accessed by at least two data groups. And a memory control means for the buffer memory, which is assigned to a bank and performs continuous burst transfer by bank switching in a word units.

As described above, the increase in memory is suppressed by using a large-capacity memory having a plurality of banks, and the divided data groups are stored in different banks, respectively. By making data input / output a continuous burst transfer by alternately switching banks in a-word units, power consumption can be reduced and high-speed access to memory data can be achieved. By using a data group classified according to the category of data reproduced from a track having the same azimuth angle, error correction of data reproduced from a plurality of reproduction channels having the same azimuth can be performed.

[0015]

An invention according to claim 1 of the present invention is an error correction device for at least two series of data having a product code, wherein an inner code correcting means for correcting an inner code of the data, The inner code data corrected by the inner code correcting means is divided into at least two data groups in units of the series, and each data group is alternately a word unit (where a is less than or equal to the data length of the inner code data). Based on the output data from the inner code data rearranging means, a buffer memory having a plurality of banks capable of continuous burst transfer by bank switching, and The inner code data written in the buffer memory is alternately read in units of the a word for each data group, and a number of outer code words per data group are read. Outer code correction, outer codewords after outer code correction are alternately read for each data group in units of the a word, and outer code correction means, and the outer code correction means corrects the outer code, and stores the outer codeword in the buffer memory. The rewritten outer code word data is alternately rearranged in units of the a-word in units of the data groups so as to be in the word sequence of the inner code data input to the inner code data rearranging means. Assigning access to the buffer memory to each of the data rearranging means, the inner code data rearranging means, the outer code correcting means, and the data rearranging means to the at least two banks in units of the data group; And a memory control means for the buffer memory for performing continuous burst transfer by unit bank switching. Use of a large-capacity memory with memory to suppress the increase in memory, store divided data groups in different banks, and switch data input / output to / from a large-capacity memory having a plurality of banks in a word units Thus, the continuous burst transfer has the effect of reducing power consumption and enabling high-speed access to memory data.

[0016] The invention described in claim 2 of the present invention provides:
An error correction device for data reproduced from a track recorded at two azimuth angles of a plus azimuth angle and a minus azimuth angle by at least two reproduction channels having the same azimuth angle, wherein the track has one or more azimuth angles. An inner code correction unit that has at least one series of data having a product code attached to the track, and the data is reproduced by an inner code correction unit that performs inner code correction on the data; The data is divided into at least two data groups in units of the series according to the azimuth angle of the track, and the data groups are alternately output in units of a words (a is a natural number equal to or less than the data length of the inner code data) for each data group. Memory having a plurality of banks capable of continuous burst transfer by bank switching Reading, based on the output data from the inner code data rearranging means, the inner code data written in the buffer memory alternately for each data group in the a-word unit; Outer code correction means for reading out the outer code words after the outer code correction for each of the data groups alternately in units of the a word, and correcting the outer code words by the outer code correction means. The data of the outer codeword written back to the buffer memory is alternately arranged for each data group so that the word sequence of the inner code data input to the inner code data reordering unit is obtained. a data rearranging means for rearranging in a word units, access between the inner code data rearranging means, outer code correcting means, data rearranging means and the buffer memory A memory control means for the buffer memory, which is assigned to at least two banks in units of the data group, and performs continuous burst transfer by bank switching in units of the a word. A large-capacity memory having banks is used to suppress an increase in memory, divided data groups are stored in different banks, and data input / output to / from a large-capacity memory having a plurality of banks is alternately switched in a word units. In this case, continuous burst transfer reduces power consumption and enables high-speed access to memory data. In addition, divided data groups are referred to as data reproduced from tracks of the same azimuth. By grouping data into categories, multiple playback channels with the same azimuth can be It has the effect of enabling error correction of generated data.

The buffer memory used in the present embodiment has a plurality of banks, allows continuous burst transfer of data by switching banks, and periodically performs a storage holding operation to realize low power consumption. Any large-capacity memory may be used, such as a large-capacity SDRAM having a plurality of banks.

An embodiment according to the present invention will be described below with reference to the drawings. (Embodiment 1) Embodiment 1 of the present invention is composed of L [L is a natural number] inner code words and (K × a) [K is a natural number] or less outer code words per series. This is an error correction device for data of a (2 × N) sequence [N is a natural number] having a product code configuration.

FIG. 1 shows a configuration diagram of the error correction device of the present embodiment.

In FIG. 1, reference numeral 1 denotes an inner code correcting means for correcting an inner code of at least two series of data having a product code;
2 divides the inner code data, the inner code of which has been corrected by the inner code correcting means 1, into at least two data groups in units of the series, and alternately for each data group, a word unit [a is the data of the inner code data. Inner code data rearranging means for rearranging by a natural number less than or equal to
Is a buffer memory having a plurality of banks capable of continuous burst transfer by bank switching, and 4 is a memory for storing the inner code data written in the buffer memory 3 based on output data from the inner code data rearranging means 2 in the data group. Alternately read for each a word unit, perform outer code correction by a outer code words per data group, and outer code words after outer code correction are alternately read for each data group, the a word unit Outer code correcting means 5 to be read by
The data of the outer codeword corrected by the outer code and written back to the buffer memory 3 is converted into the word sequence of the inner code data input to the inner code data rearranging means 2 for each of the data groups. Alternately, the data rearranging means for rearranging the data in units of the a word, 6 is an inner code data rearranging means 2, an outer code correcting means 4, and a data rearranging means 5 for accessing the buffer memory 3 with the data. This is a memory control means of the buffer memory 3 which is assigned to at least two banks in group units and performs continuous burst transfer by bank switching in a word units.

FIG. 1 is a block diagram of an error correction apparatus for error-correcting data of a (2 × N) sequence [N is a natural number] having a product code. Get the data.

The operation of the error correction device configured as described above will be sequentially described with reference to the drawings.

FIG. 2 is a memory map showing the minimum structural unit of the buffer memory 3 according to the first embodiment.

FIG. 1 shows data 1 having a product code configuration.
Since the sequence is formed as shown in FIG. 10, K = 10,
FIG. 9 is a diagram schematically illustrating a case where N = 1, where L = 149 and a = 8, and a buffer memory 3 performs digital correction of all series divided into respective data groups when performing error correction. It has as many minimum structural units as needed to store data. In the figure, for example, M (0, 1, 1) in the upper left of the figure represents one sector. Each number appearing in the matrix expression M (0, 1, 1) representing the sector corresponds to each of a bank representing an independent memory cell array, a row representing a bank row, and a column representing a bank column. Then, when applied to the position of each number, M (bank,
Row, column). Also, FIG.
Since the memory map corresponds to burst transfer in word units, the unit of a column in the matrix expression in sector units is 8 words.

It should be noted that at least two data groups divided by the sequence unit by the inner code data rearranging means of the present invention correspond to the data groups divided into the respective sectors shown in FIG. Here, a data group in which the value of the bank in the matrix expression M representing the sector is 0 is 2 as exemplified in the first embodiment.
The data group of one of the series corresponds to the data group of one series, and the data group of which the value of the bank is 1 corresponds to the data group of the other series.

FIG. 3 is an explanatory diagram of the control of writing the inner code data from the inner code data rearranging means 2 to the buffer memory 3 in the first embodiment.

As shown in FIG. 1, the input two-series data is subjected to inner code correction by inner code correcting means 1 respectively.
It is input to the inner code data rearranging means 2. The inner code data input to the inner code data rearranging means 2 is a memory control means for controlling the respective processing blocks of inner code data writing, outer code word reading, outer code word writing, and data reading in a time division manner. In accordance with No. 6, the data of each series is alternately and continuously burst-transferred in the column direction from the inner code data rearranging means 2 by alternate bank switching in sector units according to the ID of the sync block during the inner code data write processing. Then, as shown in FIG.
Is written to.

As described above, the data of each series is alternately
The operation of being transferred in time series corresponds to rearrangement and output in units of a word in the present invention.

Since each sync block is stored in one of the rows in the bank divided for each stream, the details of the inner code data write block representing the inner code data write processing are shown. J in 3 changes by the number of sync blocks in one series, and according to the memory control means 6,
The write process shown as the inner code data write block is repeated a required number of times.

FIG. 4 is a memory map of an outer code word memory (not shown) in the outer code correction means 4.

FIG. 3 is a diagram when the outer code is corrected in the minimum unit. In order to perform outer code correction, from the data area of each series stored in a different bank of the buffer memory 3,
Data of the same column is stored in two rows in the row direction in sector units. In the figure, the number of outer codewords to be corrected is 16 in total, because the unit of one sector is 8 words for each sequence, and thus the outer code is corrected for each of 8 outer codewords. The outer code correction is performed after all the data for which the inner code has been corrected are stored in the buffer memory 3 for each stream, so that it can be performed for each sector regardless of the time series of the data in the sync block. Therefore, as is apparent from FIG. 2, i in the figure is limited to the number of accesses to the buffer memory 3 necessary to burst-transfer all data in one sync block in the column direction in sector units. It can take any value and must be the same within the same series, but between different series,
It is not necessary that they have the same value.

FIG. 5 is an explanatory diagram of the control of reading the outer code word from the buffer memory 3 to the outer code correcting means 4.

As shown in FIG. 1, in order to correct the inner code data after the inner code correction stored in the buffer memory 3 to the outer code, the buffer memory 3
During the outer codeword read process, the outer codewords of the same column in all the rows of each sequence are alternately switched for each sequence from each of the sequences in the two different banks by bank alternate switching in sector units. , And is written in an outer code word memory (not shown) in the outer code correction means 4 as shown in FIG.

Since each sync block is stored in one of the rows in the bank divided for each stream, the details of the outer codeword readout block representing the outer codeword readout process are shown in FIG. K changes by the number of accesses to the buffer memory 3 necessary to burst-transfer the outer codewords of the same column in the row direction in all rows of one series in the unit of row in accordance with the memory control means 6. The read processing shown as the outer codeword read block is repeated the required number of times.

The outer code word after the inner code correction written in the outer code word memory is outer code corrected by the outer code correction means 4 and written back to the outer code word memory again. The outer codeword after the outer code correction written back to the outer codeword memory is the same as the outer codeword read in the outer codeword read processing,
From the outer code correcting means 4 to the memory control means 6, in the outer code word writing block indicating the outer code word writing process, to each of the two sequences, to the same column in all rows of each sequence, By alternate bank switching
The data is continuously burst-transferred in the row direction so as to be alternated for each stream, and is written back to the buffer memory 3.

FIG. 6 is an explanatory diagram of the control of reading data from the buffer memory 3 to the data rearranging means 5.

As shown in FIG. 1, the error-corrected data stored in the buffer memory 3 is stored in a memory controller 6.
In the same manner as when the inner code data is written from the inner code data rearranging means 2 at the time of data reading processing from the buffer memory 3, the data of each series is alternately switched in the column direction by bank alternate switching in sector units. Are successively transferred, and are rearranged so that the word arrangement of each series of data becomes the word arrangement of inner code data, and are output as two series of data.

Since each sync block is stored in one of the rows in the bank divided for each stream, j in FIG. 6 showing the details of the data read block representing the data read process is as follows: It changes by the number of sync blocks in one stream, and the read processing shown as a data read block is repeated by the necessary number of times according to the memory control means 6.

As described above, according to the present embodiment, a large-capacity memory having a plurality of banks is used to suppress an increase in the memory, and the divided data groups are stored in different banks, respectively. By making data input / output to / from the large-capacity memory continuous burst transfer by alternate bank switching in sector units, power consumption can be reduced and high-speed access to memory data can be made possible. (Embodiment 2) In Embodiment 2 of the present invention, at least two reproduction channels having the same azimuth angle are used to reproduce data from a track recorded at two types of azimuth angles, a plus azimuth angle and a minus azimuth angle. (2
.Times.N) an error correcting apparatus for error-correcting data of a series [N is a natural number of 2 or more], wherein the track has at least one series of data having a product code per track, and each track has L It has a configuration of a product code composed of inner code words of [L is a natural number] and outer code words of (K × a) or less [K is a natural number].

FIG. 7 shows a configuration diagram of the error correction device of the present embodiment.

In the figure, reference numeral 7 denotes demodulating means for demodulating data reproduced by each reproducing channel having reproducing heads having a positive azimuth angle and a negative azimuth angle, and 8 a cylinder to which the reproducing head is attached. Other reference numerals are the same as those in the first embodiment, and a description thereof will be omitted.

FIG. 7 is a diagram showing a configuration in which two reproduction channels each having a positive azimuth angle and a negative azimuth angle are provided. Each of the four reproduction channels includes a positive azimuth head P1, P2 and a negative azimuth head S1, S2. The four series of digital data to be reproduced are error-corrected by the above-described means, and output data 1 and 2 are obtained.

The difference from the first embodiment is that N = 1
N = 2, and whether the category of the data group to be divided is data reproduced from a track of the same azimuth.

The operation of the error correction device configured as described above will be sequentially described with reference to the drawings.

FIG. 8 is a memory map showing the minimum structural unit of the buffer memory 3 according to the second embodiment.

FIG. 10 shows that one series of digital data having the structure of a product code is formed as shown in FIG.
FIG. 9 is a diagram schematically illustrating a case where N = 2, where K = 10, L = 149, and a = 8.
When error correction is performed, the number of minimum structural units is sufficient to store the digital data of the entire series of each reproduction channel divided into the respective data groups. In the figure, for example, M (0,1,1) at the upper left of the figure is 1
And has the same data structure as in the first embodiment. In the figure, for example, M (0, j, i) [j = 1
To 149, i = 1 to 10] are one-series data reproduced from a track having a positive azimuth angle, and since there are two reproduction channels of the same azimuth, data reproduced from a recording track of the same azimuth is the same bank. Are stored for two series. In the figure, since the number of sync blocks constituting one sequence is 149, for example, data of two sequences reproduced from the recording track of the same azimuth is stored with an offset of 150 in the row direction. ing.

On the other hand, data reproduced from a track having a minus azimuth angle is stored in a different bank as shown in the figure, and is stored in two banks in the same manner as a bank in which data reproduced from a track having a plus azimuth angle is stored. Have been.

FIG. 9 is an explanatory diagram of the control of writing the inner code data from the inner code data rearranging means 2 to the buffer memory 3 in the second embodiment.

As shown in FIG. 7, the reproduced data of the four channels reproduced from the tracks having the positive azimuth angle and the negative azimuth angle are input to the demodulating means 7 and demodulated for each channel. ID
Is extracted. The data demodulated by the demodulation means 7 is
Each is input to the inner code correction means 1 and is corrected for each reproduction channel. The data of each channel whose inner code has been corrected by the inner code correcting means 1 is input to the inner code data rearranging means 2 for each stream according to the ID of the sync block extracted by the demodulating means 7. The inner code data after the inner code correction input for each series is a memory for controlling the respective processing blocks of writing inner code data, reading outer code word data, writing outer code word data, and reading data in a time-division manner. According to the control means 6, the inner code data rearranging means 2 alternates the data of each series in the column direction by alternately switching banks in sector units according to the ID of the sync block during the inner code data write processing. Burst transfer is performed, and the buffer memory 3 is transferred as shown in FIG.
Is written to.

Since each sync block is stored in one of the rows in the bank divided for each stream, the details of the processing of the inner code data write block representing the inner code data write processing are shown in FIG. J in the figure changes by the number of sync blocks in one series, and according to the memory control means 6,
The writing process shown as the inner code data writing block is repeated the required number of times.

During normal 1 × speed reproduction, the heads P1, P2, S1 and S2 of each reproduction channel are on-track to the recording tracks recorded by the recording heads (not shown) corresponding to the respective azimuths. Therefore, data reproduced from each reproduction channel is data of the same series. Accordingly, the data of each channel whose inner code has been corrected is stored in the buffer memory 3 in the order shown in FIG. 3A without crossing the reproduction channels of the same azimuth.

However, in the case of slow reproduction, which is an essential function in broadcast and commercial VTRs, a fixed head uses a plurality of recording tracks unless dynamic tracking is performed so that the reproduction head moves on-track in accordance with the reproduction speed. For example, in the case where there is one recording head, two reproduction heads having the same azimuth twice as large are mounted on the cylinder 8 and reproduction is performed while complementing recording tracks that cannot scan each other. Thus, slow reproduction from -1x speed to + 1x speed is realized. Therefore, in the case of the slow reproduction by the fixed head as described above, the same recording track is scanned by a plurality of reproduction heads having the same azimuth.
Sync blocks constituting the same stream are reproduced by a plurality of reproduction channels having the same azimuth. Also, the number and order of the plurality of reproducing heads crossing the track to reproduce the recording track depend on the tape speed and phase during slow reproduction. The channels cross each other and are stored in the respective storage locations of the buffer memory 3 in the order shown in (b), (c), and (d) including (a) in FIG.

The inner code data after the inner code correction stored in the buffer memory 3 as shown in FIG. 8 from the inner code data rearranging means 2 is hereinafter referred to as a sequence unit in the divided data group. As in the first embodiment, the outer code is corrected by following the same procedure, the word sequence of the data is rearranged for each sequence, and output data 1 and 2 are output.

As described above, according to the present embodiment, a large-capacity memory having a plurality of banks is used to suppress an increase in the memory, and the divided data groups are stored in different banks, respectively. By making data input / output to / from a large-capacity memory as continuous burst transfer by alternate bank switching in sector units, power consumption can be reduced and high-speed access to memory data can be achieved. The data group that has been categorized in the category of data reproduced from the track of the same azimuth can be used to correct errors in data reproduced from a plurality of reproduction channels having the same azimuth. .

A magnetic disk storing a program and / or data for causing a computer to execute all or a part of the functions of all or part of the error correction device according to any of the above embodiments. A program recording medium such as an optical disk or an optical disk, wherein the program and / or data read by a computer execute the function in cooperation with the computer. Then, by performing the same operation as above using this,
A similar effect can be exhibited.

As described above, in the first embodiment of the present invention, a large-capacity memory having a plurality of banks is used to suppress an increase in memory, and divided data groups are stored in different banks, respectively. Has the advantageous effect of reducing power consumption and enabling high-speed access to memory data by performing continuous burst transfer of data input / output to / from a large-capacity memory having the same number of banks. can get.

According to the second embodiment of the present invention, in addition to the effects obtained in the first embodiment, the divided data groups are further classified by the category of data reproduced from the same azimuth track. By making it a data group,
The advantageous effect that error correction of data reproduced from a plurality of reproduction channels having the same azimuth is also enabled is obtained.

It should be noted that, except for the large-capacity buffer memory according to the present invention, the outer codeword memory used in the outer code correction means can be dramatically reduced, so that the outer codeword memories can be integrated into one and integrated. Since it is easy to realize as a circuit, this makes it possible to promote further low power consumption and cost reduction, and its effect is enormous when considering after-care and maintenance of the device. .

[0059]

As is apparent from the above description, the present invention has the advantages of reducing the circuit size and power consumption as compared with the prior art and enabling high-speed access to memory data.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an error correction device according to a first embodiment of the present invention.

FIG. 2 is a diagram for explaining a memory map indicating a minimum configuration unit of a buffer memory according to the first embodiment;

FIG. 3 is an explanatory diagram of control of writing inner code data from an inner code data rearranging unit to a buffer memory according to the first embodiment;

FIG. 4 is a diagram for explaining a memory map of an outer code memory in an outer code correction unit.

FIG. 5 is an explanatory diagram of reading control of an outer code word from a buffer memory to an outer code correcting unit.

FIG. 6 is an explanatory diagram of control of data reading from a buffer memory to a data rearranging unit;

FIG. 7 is a configuration diagram of an error correction device according to a second embodiment of the present invention.

FIG. 8 is a diagram for explaining a memory map indicating a minimum configuration unit of a buffer memory according to the second embodiment;

FIG. 9 is an explanatory diagram of the control of writing the inner code data from the inner code data rearranging unit to the buffer memory in the second embodiment.

FIG. 10 is a schematic diagram showing an example of a conventional product code.

[Explanation of symbols]

 1. Inner code correction means 2. 2. Internal code data rearranging means Buffer memory 4. Outer code correction means 5. Data rearrangement means 6. 6. Memory control means Demodulation means 8. Cylinder

Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat II (Reference) H03M 7/30 H03M 7/30 Z (72) Inventor Masatoshi Taniguchi 1006 Odakadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. F term (reference) 5B001 AA13 AB01 AD04 AE04 5J064 AA02 BA09 BA16 BB08 BD03 5J065 AA03 AC03 AD13 AE02 AF01 AF03 AH06 AH09 AH17 AH19

Claims (3)

[Claims] 1. An error correction device for at least two series of data having a product code, comprising: an inner code correction unit for correcting an inner code of the data; and an inner code data corrected by the inner code correction unit by the inner code correction unit. Inner code data rearranging means for dividing the data into at least two data groups in the sequence unit and alternately rearranging and outputting the data groups in units of a word [a is a natural number equal to or less than the data length of the inner code data] A buffer memory having a plurality of banks capable of continuous burst transfer by bank switching; and, based on the output data from the inner code data rearranging means, the inner code data written in the buffer memory, The data is read in units of the a word alternately for each group, the outer code is corrected by a number of outer code words per data group, and the outer code after the outer code is corrected. An outer code correcting unit that alternately reads out in units of the a-word for each of the data groups.The outer code word that has been outer code corrected by the outer code correcting unit and written back to the buffer memory, A data rearranging means for alternately rearranging in units of the a word for each data group so as to be substantially the same as a word arrangement of the inner code data inputted to the inner code data rearranging means; The access between the data rearranging unit, the outer code correcting unit, the data rearranging unit, and the buffer memory is allocated to at least two banks in units of the data group, and continuous burst transfer by bank switching in the a word unit is performed. And a memory control means for the buffer memory. 2. An error correction device for data reproduced from a track recorded at two azimuth angles of a plus azimuth angle and a minus azimuth angle by a plurality of reproduction channels having at least two azimuth angles, The track has at least one series of data having a product code per track, an inner code correcting unit for correcting the data by an inner code, and an inner code data corrected by the inner code by the inner code correcting unit. The data is divided into at least two data groups in units of the series according to the azimuth angle of the track on which the data is reproduced, and the data groups are alternately a-word units (a is a natural number less than or equal to the data length of the inner code data) And a plurality of banks capable of continuous burst transfer by bank switching. A buffer memory, based on the output data from the inner code data rearranging means, reading the inner code data written in the buffer memory alternately for each data group in the a word unit, Outer code correction means for performing outer code correction by a outer codewords per group and outer codewords after the outer code correction are alternately read for each of the data groups in units of the a word, and the outer code correction means The data of the outer code word that has been subjected to the outer code correction and written back to the buffer memory is alternately arranged for each of the data groups so that the word sequence of the inner code data input to the inner code data rearranging means is obtained. The data rearranging means for rearranging in a word units; the inner code data rearranging means, the outer code correcting means, the data rearranging means, and the buffer memory. And a memory control means for the buffer memory, wherein access to the memory is allocated to at least two banks in units of the data group, and continuous burst transfer is performed by bank switching in units of the a word. apparatus. 3. A program recording medium which records a program and / or data for causing a computer to execute all or a part of functions of all or a part of the error correction device according to claim 1 or 2. And a computer-readable program recording medium.