JPH09237257A - Signal processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a signal processor capable of eliminating the necessity of a control bus, using the control bus for another purpose and improving reliability by providing the processor with respectively specific operation module, control data generating part, merger and local computer. SOLUTION: In the case of rader signal processing e.g. a received signal is divided into plural signals and the divided signals are simultaneously executed by respectively different processors. In the signal processor, a control data generating part 10 divides a received signal and generates control data for allocating operation modules 13 to 16 for processing the divided signals to the divided signals. The merger 11 merges the received signal and the control data and outputs the merged signal to a bus 12. Each of the modules 13 to 16 has a processor and a memory in its inside to process each received signal. A local computer 17 collects and stores the processing results of the modules 13 to 16 or applies other processing to the processing results.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing device requiring high-speed arithmetic processing in digital signal processing such as image processing and radar signal processing.

[0002]

2. Description of the Related Art If there is a large amount of data and these data are sent in a certain cycle, a high-speed processing method is to divide the input data into units of a certain cycle, and divide each divided data A signal processing device has been proposed in which a plurality of processors are sequentially processed. As such a signal processing device, there is one described below.

The structure of a conventional signal processing apparatus will be described with reference to FIG. FIG. 9 shows, for example, “Highly Parallel Signal Processing” edited by Tatsuo Higuchi, published by Shokodo on August 10, 1992.
It is a figure which shows the structure of the conventional signal processing apparatus shown to the 164th page-the 166th page.

In FIG. 9, 1 is a host CPU that controls the entire processing apparatus, 2 is a data transfer bus for transferring the data stored in a data storage device, which will be described later, to a memory, which will be described later, and 3 stores the data. Data storage device, 4
Is a control bus for the host CPU 1 to control a processor to be described later and a memory to be described later, and 5a to 5d are processor boards connected to the control bus 4.

Further, in FIG. 1, each processor board 5a-5d has an interface 50 for connecting a processor to be described later and the control bus 4, a processor 51 for processing divided data in a pipeline, and a host CPU.
RAMs 52 to 54 for storing instructions from 1 to the processor 51 and processing programs.

Further, in the figure, 6a to 6d are memories for storing the divided data and the processing result of the processor 51, and 7 is a high-speed bus for transferring the contents of the memory between the processor 51 and the memories 6a to 6d. is there.

The above-mentioned conventional signal processing device is provided with a host CP.
U1 transfers data from the data storage device 3 to the memories 6a to 6d, starts processing to the processor 51, the memories 6a to 6d.
The system is such that instructions and control such as data transfer between 6d are performed via the control bus 4.

Next, the operation of the conventional signal processing apparatus will be described. In step A1, the host CPU1
Loads the processing program into the RAMs 52 to 54 of the processor boards 5a to 5d via the control bus 4.

At step A2, the host CPU1
Transfers the data stored in the data storage device 3 to the memory 6a via the data transfer bus 2 and the high speed bus 7.

When the data transfer to the memory 6a is completed in step A3, the host CPU 1 sends a processing start command to the processor 51 of the processor board 5a. Then, the processor 51 starts processing on the data stored in the memory 6a. On the other hand, the host CPU 1
The next signal data is transferred from the data storage device 3 to the memory 6b via the data transfer bus 2 and the high speed bus 7.

When the data transfer to the memory 6b is completed in step A4, the host CPU 1 sends a processing start command to the processor 51 of the processor board 5b. Then, the processor 51 starts processing on the data stored in the memory 6b. On the other hand, the host CPU 1
The next signal data is transferred from the data storage device 3 to the memory 6c via the data transfer bus 2 and the high speed bus 7.

When the data transfer to the memory 6c is completed in step A5, the host CPU 1 sends a processing start command to the processor 51 of the processor board 5c. Then, the processor 51 starts processing on the data stored in the memory 6c. On the other hand, the host CPU 1
The next signal data is transferred from the data storage device 3 to the memory 6d via the data transfer bus 2 and the high speed bus 7.

When the data transfer to the memory 6d is completed in step A6, the host CPU 1 sends a processing start command to the processor 51 of the processor board 5d. Then, the processor 51 starts processing on the data stored in the memory 6d.

At step A7, when the processing of the processor 51 mounted on each of the processor boards 5a to 5d is completed, the processing result is stored in the memory 6 via the high speed bus 7.
a to 6d, and then to the data storage device 3 via the data transfer bus 2.

The conventional signal processing apparatus first executes the steps A1 to A7, and thereafter executes the steps A2 to A7.
By repeatedly executing A7, each processor 51
The processing time was shifted, and the single high-speed bus 7 was used in a time-division manner to proceed the processing in a pipeline manner to speed up the processing.

[0016]

In the conventional signal processing apparatus as described above, when it is necessary to change the processing contents in accordance with the data of radar signal processing or the like, it is necessary to transfer an instruction for individual data transfer or It is necessary to transmit both processing parameters for changing the processing content via the control bus 4. Therefore, the control bus 4 is indispensable for transmitting these commands and parameters, and there is a problem that the control bus 4 cannot be used for other purposes because there is much data to be transferred.

The present invention has been made in order to solve the above-mentioned problems, the control bus can be eliminated, and the control bus can be diverted to other uses to improve the reliability of the apparatus. The purpose is to obtain a signal processing device.

[0018]

A signal processing device according to the present invention includes a plurality of arithmetic modules for processing a received signal input based on composite data, and control data for controlling the plurality of arithmetic modules. A control data generation unit for generating, a merger for combining the received signal and the control data generated by the control data generation unit to output the combined data, and a local computer for receiving a processing result of the arithmetic module. It is a thing.

Further, the signal processing device according to the present invention further comprises a processing result transmission line connecting the local computer and the control data generating section, and the control data is transmitted based on the processing result received by the local computer. The control data generation unit for changing the contents of

Further, the signal processing device according to the present invention includes: an arithmetic module for performing self-diagnosis and outputting the result together with a signal processing result; a local computer for receiving the self-diagnosis result and the processing result; And a control data generation unit that generates control data for allocating the processing of the received signal to a non-faulty operation module based on a failure condition, and performs load distribution without using the faulty operation module.

Further, the signal processing apparatus according to the present invention further comprises a spare module having the same function as that of the arithmetic module, and an arithmetic module for performing self-diagnosis and outputting the result together with a signal processing result, and a self-diagnosis result. A local computer that receives the processing result, a control module that generates control data that allocates the processing of the received signal to the operation module that has not failed and the backup module based on the failure status obtained from the self-diagnosis result, and the failed operation module And a control data generation unit that performs load distribution without using.

Further, the signal processing apparatus according to the present invention has the merger, the modules, and the local computer connected by a bus.

Further, the signal processing apparatus according to the present invention further comprises a synchronization signal line connecting the control data generating section, the merger and the respective modules, monitoring the synchronization signal line, and based on the synchronization signal, The control data is fetched from the data flowing on the bus, the portion of the received signal necessary for processing is fetched from the data flowing on the bus based on its interpretation, and the signal is processed and processed. It is equipped with each module that outputs the result.

Further, the signal processing apparatus according to the present invention takes in the control data from the data flowing in the bus only while the signal is not processed, and based on its interpretation, flows in the control data. It is provided with each module that takes in a portion of the received signal necessary for processing from the stored data, processes the signal, and outputs the processing result.

Further, the signal processing device according to the present invention has the first and second areas for storing the received signal, and processes the signal while not processing the signal and by the next cycle. Only when it is known that the control data is completed, the control data is fetched from the data flowing on the bus, and based on its interpretation, the portion of the received signal necessary for processing is selected from the data flowing on the bus. , When the signal being processed is stored in the second area different from the first area, and the processing of the signal being processed is finished and the output of the processing result is finished, It is provided with each module for starting signal processing.

Further, the signal processing apparatus according to the present invention has first and second processors, the first processor processes the received signal received, and the second processor controls the control. It is provided with each module for taking in data and necessary reception signals from the bus.

Further, the signal processing device according to the present invention synthesizes the received signal and the second control data after a predetermined period from the first control data corresponding to the received signal to synthesize the synthesized data. Is output to the bus.

Further, in the signal processing device according to the present invention, the merger, the arithmetic modules, and the local computer are pipeline-connected.

Further, in the signal processing device according to the present invention, some of the arithmetic modules are bus-connected.

The signal processing apparatus according to the present invention further comprises a spare module, a control bus connecting the spare module, the merger, the arithmetic modules, and the local computer, and the control data generation unit, When a failure occurs in any of the merger, the arithmetic modules, and the local computer,
The spare module substitutes the function of the defective portion.

Further, the signal processing device according to the present invention is
The merger, the arithmetic modules, and a control bus connecting the local computer are further provided, and when any of the merger, the arithmetic modules, or the local computer fails, the control bus is used to The control module is provided with a control data generation section that rewrites the internal data held by the arithmetic module for processing and the control data flowing together with the received signal.

[0032]

BEST MODE FOR CARRYING OUT THE INVENTION A signal processing apparatus according to an embodiment of the present invention is designed to control a control bus when a bus which can be connected to an arithmetic module is limited due to improvement of the reliability of the apparatus or other reasons. It is intended to abolish or divert the control bus to other uses, and in order to solve the above-mentioned problems, the following means are provided, and a system for abolishing the control bus or diverting the control bus is adopted. To do.

The control data generation unit, including load balancing,
The control data for controlling each arithmetic module is generated. Further, the merger merges the generated control data with the signal to be processed and predetermines the merge format so that the arithmetic module can extract the control data from the merged data. Also, a header and a trigger are generated so that the start position of the data and the boundary of each content can be known. Further, the arithmetic module takes out control data from the merged data, takes in signals necessary for processing, processes them according to the instruction of the control data, and outputs the result.

Embodiment 1 Embodiment 1 of the present invention
Take radar signal processing as an example. In the case of radar signal processing, a high-speed signal processing is realized by dividing the received signal into a plurality of pieces and causing each of them to be executed by another processor at the same time.

The configuration of the first embodiment of the present invention will be described with reference to FIG. 1 is a block diagram showing a configuration of a first embodiment of the present invention. In each figure,
The same reference numerals indicate the same or corresponding parts.

In FIG. 1, 10 is a division of the received signal,
A control data generation unit that generates control data for assigning a calculation module, which will be described later, that performs the processing to the divided reception signals, 11 is a merger that combines the reception signals and the control data, and sends the combined product to a bus that will be described later. Reference numeral 12 is an input / output bus, 13 to 16 are arithmetic modules that have a processor and a memory inside, and process received signals. It is a local computer that performs the process of.

The control data generator 10 corresponds to the conventional host CPU 1. The bus 12 corresponds to a combination of the conventional data transfer bus 2 and the high speed bus 7. The arithmetic modules 13 to 16 include the processor boards 5a to 5d and the memories 6a to 6d of the conventional example.
Corresponds to the combination of. Further, the part that receives the processing results of the arithmetic modules 13 to 16 of the local computer 17 corresponds to the conventional data storage device 3.

In the first embodiment, the merger 11 adds control information to the received signal, and the arithmetic modules 13 to 16 interpret the combined data so that a plurality of data can be obtained without a control bus. Arithmetic modules 13-16
Take the method of controlling.

Next, the operation of the first embodiment will be described. In step B1, the control data generator 1
0 determines the processing contents in the arithmetic modules 13 to 16, division of received signals, and allocation to the arithmetic modules 13 to 16. Also, when outputting the processing result to the bus 12, the output timing is adjusted so that data collision does not occur.

The control data generation unit 10 converts the information such as the processing content, the division method, the allocation method, and the output timing obtained as a result into control data and transfers it to the merger 11. As a data division / allocation method, data is divided into four so that the loads of all the arithmetic modules 13 to 16 are uniform.
Divide, and calculate each divided one by one
There is a method of assigning to.

In step B2, merger 11 combines the received signal and control data and outputs the result to bus 12.

In step B3, the arithmetic module 1
3 to 16 take in the control data, analyze it, and obtain the range of the received signal to be processed by the user, the content to be processed for the received signal, and the timing of outputting the processing result of the user. The arithmetic modules 13 to 16 fetch only the required range of the received signal from the bus 12 according to the analysis result of the control data, perform the processing, and output the result to the bus 12 at the designated timing. The arithmetic modules 13 to 16 that have finished outputting the processing results wait for the next control data to flow to the bus 12.

As a method of extracting the control data and the received signal from the data flowing on the bus 12, there are a method using a header and a method in which a signal line for synchronization is provided and the signal line is used for identification. .

In step B4, the local computer 17 collects the processing results output by the arithmetic modules 13 to 16 from the bus 12 and stores or stores them.

As a method of collecting the processing result, a method of setting the time for the output data to flow to the bus 12 in advance, a method of transmitting the timing by using the control data as in the control of the arithmetic modules 13 to 16, and the like. There is.

In the signal processing apparatus according to the first embodiment, by repeating the steps B1 to B4,
A plurality of arithmetic modules 13 to 16 are controlled without a control bus to speed up signal processing.

That is, the signal processing device according to the first embodiment is a signal processing device for processing a signal input at a constant cycle, and processes the signal and the signal input line to which the signal is input. A plurality of arithmetic modules 13 to 16 each including a processor and a memory, a bus 12 that connects the arithmetic modules 13 to 16 in a bus connection type, and a local computer 17 that receives the processing results of the arithmetic modules 13 to 16 via the bus 12. And a control data generation unit 10 for generating data for controlling the plurality of arithmetic modules 13 to 16, a signal from the signal input line and control data from the control data generation unit 10 are combined, and the data is converted into the above-mentioned data. The merger 11 placed on the bus 12 is provided, and the input signal becomes the input of the merger 11 and is created by the control data generation unit 10. Control data is added, distributed / processed to the arithmetic modules 13 to 16 via the bus 12, and collected by the local computer 17 via the bus 12 without using the control bus. Is.

Since the first embodiment adopts the method of transmitting the information for controlling the plurality of arithmetic modules together with the signal to be processed as the control data, compared with the conventional control using the control bus, This has the effect of reducing the number of buses connected to the arithmetic module.

Embodiment 2 The configuration of the second embodiment of the present invention will be described with reference to FIG. 2 is a block diagram showing the configuration of the second embodiment of the present invention.

In FIG. 2, reference numeral 18 denotes a processing result transmission line, which is used by the local computer 17 to control data generator 1
The processing result is transmitted to 0. Other configurations are the same as those in the first embodiment.
Is the same as

In the first embodiment, the local computer 17 collects and stores the processing results of the arithmetic modules 13 to 16 or performs another processing on the processing results. In the second embodiment, the local computer 17 collects the processing results. The processed data or the result after another processing is performed on the control data generation unit 1
By transmitting to 0, the control data generation unit 10 can be made to determine the processing content based on the past processing result.

That is, in the signal processing apparatus according to the second embodiment, the control data generation unit 10 changes the contents of the control data based on the processing result of the signal received by the local computer 17, thereby controlling the control bus. The arithmetic modules 13 to 16 are controlled without using.

In the second embodiment, by receiving information about a signal to be processed from the local computer 17 that receives the result of the signal processing and generating control data, a signal whose situation can be predicted, such as radar signal processing, is generated. In the processing, it is possible to perform processing according to the signal status.

Embodiment 3 FIG. A third embodiment of the present invention will be described with reference to FIG.

In the third embodiment, each of the arithmetic modules 13 to 16 carries out self-diagnosis and transfers the result together with the processing result to the local computer 17 via the bus 12 so that a countermeasure against a failure can be taken. Can be

For example, when a failure occurs in the operation module 16 in the figure, the control data generator 10 receives information from the local computer 17 that the operation module 16 has failed, and then divides the received signal into individual operations. When allocating to the modules 13 to 16, the arithmetic module 16
No processing is assigned to the calculation modules 13 to 15 and the processing is assigned only to the arithmetic modules 13 to 15.

That is, in the signal processing device according to the third embodiment, each of the arithmetic modules 13 to 16 is caused to perform self-diagnosis, the result is output together with the signal processing result, and the local computer 17 processes the self-diagnosis result and processing. By receiving the result and sending the failure status obtained as a result to the control data generation unit 10, the control data generation unit 10 generates the control data that assigns the processing of the input signal only to the non-faulty operation module, and the control bus is generated. The load distribution is performed without using the faulty arithmetic module without using.

In the third embodiment, the self-diagnosis is carried out and the result is transferred together with the signal processing result, so that the control based on the failure condition can be carried out without the control bus.

Embodiment 4 FIG. The configuration of the fourth embodiment of the present invention will be described with reference to FIG. FIG. 3 is a block diagram showing the configuration of the fourth embodiment of the present invention.

In FIG. 3, reference numeral 19 is a spare module connected to the bus 12. Other configurations are the same as those in the second embodiment.
Is the same as

FIG. 3 shows the configuration when a standby system is prepared. In the fourth embodiment, for example, when a failure occurs in the arithmetic module 16 in the figure, the control data generation unit 10 receives the information that the arithmetic module 16 has failed, and then divides the received signal to obtain the arithmetic module. When assigning to 13 to 16, the arithmetic module 16 is not assigned. And the arithmetic module 1
Instead of 6, a spare module 19 is used. Therefore, the processing is assigned to the arithmetic modules 13 to 15 and the spare module 19.

In the fourth embodiment, the self-diagnosis is carried out and the result is transferred together with the result of signal processing, whereby control based on the failure condition can be carried out without the control bus.

Embodiment 5 FIG. The configuration of the fifth embodiment of the present invention will be described with reference to FIG. FIG. 4 is a block diagram showing the configuration of the fifth embodiment of the present invention.

In FIG. 4, 20 is a synchronizing signal line,
By generating a trigger on this synchronization signal line 20,
The data flowing on the bus 12 is synchronized. Other configurations are the same as those in the second embodiment.

Based on the fifth embodiment, the relationship between the data on the bus 12, the arithmetic modules 13 to 16 and the local computer 17 will be described with reference to FIG. FIG. 5 is a time chart showing the operation of the fifth embodiment of the present invention.

In step C1, the merger 11 first causes the merged data of the control data and the received signal to flow through the bus 12. When the control data starts flowing to the bus 12, the merger 11 causes the synchronization signal line 20 to generate a trigger (synchronization signal) indicating that the output of the control data to the bus 12 is started.

By this trigger, each arithmetic module 1
3 to 16 identify the beginning of the control data. In addition, in the fifth embodiment, the amount (length) of control data and received signal
By fixing in advance, the arithmetic modules 13 to 16
Determines the switching position from the control data to the received signal and the end of the data.

In step C2, the processors of the arithmetic modules 13 to 16 detect, capture, and analyze the control data by the trigger. By this analysis, each of the arithmetic modules 13 to 16 has a range necessary for its own processing in the received signal immediately after the control data, the content of the processing executed on the received signal, and the timing of outputting the processing result. Take out.

In step C3, each of the arithmetic modules 13 to 16 subsequently receives the received signal necessary for its own processing from the bus 12, processes it, and outputs it to the bus 12 at a designated timing. To specify this timing, the elapsed time from the trigger occurrence is used.

At step C4, on the other hand, the local computer 17 fetches the processing result from the bus 12 while each of the arithmetic modules 13 to 16 outputs the processing result of the received signal. The time for fetching the processing result is set in advance. The signal processing device repeatedly executes the processes of steps C1 to C4.

That is, in the signal processing apparatus according to the fifth embodiment, the processors of the arithmetic modules 13 to 16 monitor the data sent to the bus 12 by the merger 11 every cycle and fetch the control data from it. Based on the interpretation, the portion of the signal input from the data flowing through the bus 12 necessary for processing is fetched, the signal is processed, and the processing result is output.

In the fifth embodiment, since the signal portion required by the arithmetic module is taken in, even if there is an overlap in the range of signals required for processing by a plurality of arithmetic modules, data is transferred one-to-one. There is no need to repeatedly transfer the same portion as in time, and only the control data and the signal to be processed need be transferred. Further, since the control data is received every cycle, different control can be performed for each cycle.

Embodiment 6 FIG. In the fifth embodiment, the processor of each of the arithmetic modules 13 to 16 fetches the control data and analyzes the data each time the control data flows to the bus 12. However, in the sixth embodiment, the processor itself processes the data. The control data is taken in and analyzed only when there is no signal. The configuration of the sixth embodiment is similar to that of the fifth embodiment.

In the method shown in FIG. 5 showing the operation (time chart) of the fifth embodiment, the processing is completed by the time the next control data is received. However, in the case of the method of the fifth embodiment, when the processing is not completed by the next cycle, an interrupt is generated, and after the control data analysis is completed, the interrupted signal processing is returned to. In the method of the sixth embodiment, the control data is not taken in during the processing of the signal, whereby the processing can be performed without generating the interrupt.

As an example in which the processing of the received signal does not end in one cycle, there is a load distribution system in which different arithmetic modules 13 to 16 are assigned to each received signal and the processing result is obtained after a fixed cycle. This load distribution method is the same as the method used in the conventional example.

That is, in the signal processing apparatus according to the sixth embodiment, the merger 11 is provided only while the processors of the arithmetic modules 13 to 16 are not processing the input signal.
Monitors the data sent to the bus 12, fetches control data from it, and based on its interpretation, fetches the part of the signal that is input to the bus 12 necessary for processing, Is processed and the processing result is output.

In the sixth embodiment, since each arithmetic module does not receive the control data during the signal processing, the processing can be continued without interruption for viewing the control data.

Embodiment 7 FIG. In the sixth embodiment, the processors of the arithmetic modules 13 to 16 fetch and analyze the control data from the bus 12 only when there is no signal to be processed by the processor. Even during the processing of, the processing of the received signal at that point, including the interrupt processing for inputting the received signal in the range necessary for the control data acquisition and analysis and processing, is performed until the next cycle. In the case of ending the above, the control data is taken in and analyzed. In this method, the control data is taken in and analyzed in a cycle immediately before the processing of the received signal and a cycle in which it is not processed.

In this system, by preparing two storage areas for the received signal, the received signal for the next processing is taken in and the output of the received signal for the processing is output without destroying the received signal being processed. When the processing is finished, the processing of the next received signal can be started.

That is, in the signal processing apparatus according to the seventh embodiment, the processors of the respective arithmetic modules 13 to 16 prepare two areas for storing the input signal, and while the input signal is not processed. , And when the processing is known to be completed by the next cycle, the merger 11 causes the bus 1
The data sent to 2 is monitored, the control data is fetched from the data, and based on the interpretation, the part of the signal input from the data flowing to the bus 12 necessary for processing is
By capturing the input signal into another area other than the area where the signal being processed is stored, the processing of the signal being processed is completed, and the processing of the next signal is started from the point when the output is completed. It is a thing.

In the seventh embodiment, each arithmetic module receives the control data in the cycle before the processing is completed, and also acquires the signal to be processed by using the double buffer, thereby acquiring the signal to be processed. Processing can be continued without waiting for.

Embodiment 8 FIG. In the fifth to seventh embodiments, the processors of the arithmetic modules 13 to 16 fetch the control data from the bus 12 and analyze it.
In the eighth embodiment, a child processor is prepared separately from the processor for processing the received signal, and the control data is taken in and analyzed.

Further, as the two storage areas for the received signal are prepared in the seventh embodiment, the storage area for the processing result is also two.
By preparing one and causing the child processor to output the processing result to the bus 12 as in the case of capturing and analyzing the control data, the processor receives the received signal without waiting for the input of the received signal or the output of the processing result. Only the processing of can be continuously executed.

That is, in the signal processing apparatus according to the eighth embodiment, the operation modules 13 to 16 take in the control data and the necessary portions of the signals to be processed from the bus 12 on the operation modules 13 to 16. This processor is provided with a child processor different from the above processor, and is executed by this child processor.

In the eighth embodiment, all the capabilities of the processor are achieved by allowing the child processor, which is different from the processor that processes the signal, to fetch the data from the bus, interpret the control data, and output the processing result. It can be used for signal processing.

Embodiment 9 In the ninth embodiment, the control data is sent ahead by a preset period, and thus the time for interpreting the control data can be secured. For example, when sending one cycle ahead, the control data in the input cycle (1) of FIG. 5 does not control the received signal of the same cycle immediately after that, but the input cycle (2 ), The division of the received signal and the control of the arithmetic modules 13 to 16 are designated.

In this method, since there is a time from the reception of the control data to the input of the reception signal corresponding to the control data, the control data can be analyzed using this time.

That is, in the signal processing device according to the ninth embodiment, not the control of the same cycle as the signal to be merged as the control data but the data for carrying out the control after the preset cycle is postponed. It is controlled by.

In the ninth embodiment, the information for performing the control after several cycles is postponed as the control data, so that the time for interpreting the control data can be secured.

Embodiment 10 FIG. Embodiment 1 of the present invention
The configuration of 0 will be described with reference to FIG. FIG.
[Fig. 13] is a block diagram showing a structure of a tenth embodiment of the present invention. In the drawings, the same reference numerals indicate the same or corresponding parts.

In FIG. 6, reference numeral 10 divides the received signal,
A control data generation unit for generating control data for allocating an arithmetic module, which will be described later, that performs the processing to the divided received signals, 11 is a merger for synthesizing the received signal and the control data, and sending the combined result to the arithmetic module, which will be described later. , 13 to 16 and 21 and 22 have a processor and a memory therein and process a received signal.
Reference numerals 12a and 12b are input / output buses, and 17 is a local computer that collects and stores processing results of the arithmetic module 22 or performs another processing on the processing results.

FIG. 6 shows an embodiment in which pipeline connection and bus connection are combined, and the operation modules 15, 16 and 21 in the figure are bus connections.

In the configuration of FIG. 6, the arithmetic module 1
3 and 14 first take out and interpret the control data for itself from the control data. Based on the received signal, the received signal or the processing result of the upstream arithmetic module 13 is received and processing is performed. After the processing is completed, the control data of the downstream arithmetic modules 14, 15, 16, 21, 22 and the processing result are output. Arithmetic module 15, 1
6 and 21 are arithmetic modules 14 according to the control data.
The processing result of is divided and processed. Then, the arithmetic module 22 collects the outputs of the three arithmetic modules 15, 16 and 21, processes them, and outputs the processing results to the local computer 17.

That is, in the signal processing apparatus according to the tenth embodiment, the buses connected to the arithmetic modules 15, 16 and 21 are divided into the input and output of the arithmetic modules 15, 16 and 21, and the merger 11 and Input bus 12
a, and between the output bus 12b and the local computer 17, a plurality of pipelined arithmetic modules 13, 14 and 22 are provided, and the input signal becomes the input of the merger 11 and the control data is added. And processed through a plurality of pipeline-connected arithmetic modules 13 and 14, and bus-type connected arithmetic modules 15 and 1
In the part where 6 and 21 exist, the respective operation modules 15, 16 and 21 connected in a bus type via the bus 12a.
The processing results are distributed to and processed by the CPU 12, processing results are collected through the bus 12b, processed by the arithmetic module 22 connected to the pipeline, and the processed results are sent to the local computer 17.

In the tenth embodiment, even in the pipeline connection, the device can be controlled by using the data obtained by combining the control data and the processed signal without using the control bus. Further, by providing a bus connection part in a part of the pipeline connection, it is possible to suppress the number of stages of the pipeline in the part where the data to be processed can be divided and processed.

Eleventh Embodiment Embodiment 1 of the present invention
The configuration of No. 1 will be described with reference to FIG. 7. Figure 7
FIG. 20 is a block diagram showing the structure of the eleventh embodiment of the present invention.

In FIG. 7, 18 is a processing result transmission line, 1
Reference numeral 9 is a spare module to which a reception signal is input as in the merger 11, and 23 is a control bus. Other configurations are similar to those of the tenth embodiment.

FIG. 7 is a diagram in which a standby system is added to the above-described tenth embodiment, and the control bus 23 in the drawing is all modules 11, 13 to 16 and 2 except the control data generation unit 10.
It is a bus that is connected to 1, 22, and 17 and can send and receive data.

In the eleventh embodiment, by preparing the control bus 23 and the spare module 19, the same failure countermeasure as shown in the above-mentioned fourth embodiment is connected by the pipeline connection using one spare module 19. This is realized with respect to the tenth embodiment in which the above and bus connection are combined.

For example, when a failure occurs in the arithmetic module 13, the control data generating section 10 generates control data for performing the following processing. The merger 11 sends the output to the arithmetic module 13 to the backup module 19 via the control bus 23. The spare module 19 performs the processing that the arithmetic module 13 should have performed, and sends the result to the arithmetic module 14 via the control bus 23.
The arithmetic module 14 processes the received data and outputs it to the bus 12a. The subsequent processing is the same as that in the tenth embodiment.

Similarly, one spare module 19 controls the control data generator 10, merger 11, arithmetic modules 14 to 16, 21, 22 and local computer 1.
7 failures can be dealt with.

That is, in the signal processing device according to the eleventh embodiment, the control data generator 10, merger 11,
A control bus 23 connected to the local computer 17 and all arithmetic modules 13 to 16, 21, and 22.
And a spare module 19 connected to the bus, and provided with a control data generator 10, merger 11, local computer 17, and all arithmetic modules 13-1.
When a failure occurs in any one of 6, 21, and 22, the spare module 19 substitutes the function of the failed part to maintain the function of the device.

In the eleventh embodiment, the control bus 23 and the spare module 19 connected to the control bus 23 are provided, and the control bus is used for data transfer other than control, so that the spare module calculates the pipeline connection and the bus connection. It is possible to deal with a failure of the module or the control data generation unit.

Twelfth Embodiment Embodiment 1 of the present invention
The configuration of No. 2 will be described with reference to FIG. FIG.
FIG. 20 is a block diagram showing the structure of Embodiment 12 of the present invention.

In FIG. 8, 18 is a processing result transmission line, 2
3 is a control bus. Other configurations are the same as those in the tenth embodiment.
Is the same as

FIG. 8 shows the structure of the twelfth embodiment, in which the control bus 23 and the processing result transmission line 18 are added to the tenth embodiment.

In the case where only the processing result transmission line 18 is added to the configuration of the tenth embodiment and there is no control bus, for example, when a failure occurs in the arithmetic module 21, the fact that the processing result transmission line 18 generates control data is generated. Informed to department 10. The control data generation unit 10 changes the control data to be generated, distributes the processing of the received signal only to the arithmetic modules 15 and 16 without using the arithmetic module 21, and causes the arithmetic processing to be performed. In this case, the received signals being processed by the arithmetic modules 13 and 14 are
Since the control data created before the failure of No. 1 is added, the processing is distributed to the operating module 21 in the failure, and the processing result cannot be obtained.

In the twelfth embodiment, for example, when a failure occurs in the arithmetic module 21, the control data generator 10 that recognizes the failure not only changes the control data to be generated, but also informs the arithmetic modules 13 and 14 of the change. , Instructing rewriting of control data via the control bus 23. As a result, the processing of the received signals being processed by the arithmetic modules 13 and 14 does not use the arithmetic module 21, and
The processing of the received signal is distributed only to the arithmetic modules 15 and 16 to be processed.

Further, for example, when the arithmetic module 16 is not always used, the control data generator 1
0 rewrites the internal information of the arithmetic module 16 via the control bus 23, makes the arithmetic module 16 think "I am the arithmetic module 21", and the arithmetic module 21
It is possible to continue the processing of the received signal by recognizing that "there is a failure, so there is no need to perform processing according to the control data".

That is, in the signal processing device according to the twelfth embodiment, the control data generator 10, the local computer 17, and all the arithmetic modules 13 to 16,
A control bus 23 connected to the control modules 21 and 22 is provided, and when a failure of the arithmetic module is transmitted to the control data generation unit 10, the internal data held by the arithmetic module for processing is transmitted via this control bus 23. The control data flowing with the input signal is rewritten.

In the twelfth embodiment, at the time of failure, the influence range of the failure can be narrowed by rewriting the control data and the internal information of the arithmetic module using the control bus 23.

Embodiment 13 FIG. Embodiments 1 to 12 above
In the above, the description has been given for an architecture having a bus connection, a pipeline connection, and a composite type configuration thereof. However, for other configurations, a module that generates control data based on past processing results at the signal input portion, By preparing a module for merging control data and input signals and a data line for transmitting the processing result to the arithmetic module, and having each arithmetic module perform processing according to the control data, it is possible to use the past without using the control bus. It is possible to perform control based on the processing result.

That is, in the signal processing device according to the thirteenth embodiment, in the signal processing device that changes the processing content of the input signal based on the past processing result, the signal input line to which the signal is input and the plurality of arithmetic operations are performed. A control data generation unit that generates data for controlling the module, a merger that combines a signal input from a signal input line and data sent from the control data generation unit, a merger and a calculation module, calculation modules, A data line for exchanging data between the arithmetic module and the local computer, a plurality of arithmetic modules for processing signals, and a local computer for receiving the processing result, and the local computer controls the past processing result by the control data generating unit. The control data decides the processing content of the input signal based on the content, and the processing content By generating control data to be transmitted to the arithmetic module, the merger combining the control data and the input signal, the arithmetic module takes in the control data from the combined data, and performs the processing according to the control data. Is to control.

In the thirteenth embodiment, control data is generated and added to a signal to be processed, so that control can be performed without a control bus even in other configurations.

[0115]

As described above, the signal processing device according to the present invention is provided with a plurality of arithmetic modules for processing received signals input based on composite data, and control data for controlling the plurality of arithmetic modules. And a merger for synthesizing the received signal and the control data generated by the control data generator to output the synthesized data, and a local computer for receiving the processing result of the arithmetic module. Because I prepared
As compared with the conventional control using the control bus, the number of buses connected to the arithmetic module can be reduced.

As described above, the signal processing apparatus according to the present invention further includes a processing result transmission line connecting the local computer and the control data generating section, and based on the processing result received by the local computer. Since the control data generation unit that changes the content of the control data is provided, it is possible to perform processing according to the signal status in processing of signals whose status can be predicted, such as radar signal processing. Play.

As described above, the signal processing apparatus according to the present invention includes an arithmetic module for performing self-diagnosis and outputting the result together with a signal processing result, a local computer for receiving the self-diagnosis result and the processing result, and And a control data generation unit that generates control data that assigns the processing of the received signal to a computing module that has not failed based on the failure status obtained from the self-diagnosis result, and performs load distribution that does not use the failed computing module. Therefore, by performing self-diagnosis and transferring the result together with the signal processing result, it is possible to perform the control based on the failure condition without the control bus.

Further, as described above, the signal processing apparatus according to the present invention further comprises a spare module having the same function as the above-mentioned arithmetic module, and performs self-diagnosis and outputs the result together with the signal processing result. A local computer for receiving the self-diagnosis result and the processing result, and generating control data for allocating the processing of the received signal to the operation module and the spare module which have not failed based on the failure status obtained from the self-diagnosis result. Since it has a control data generator that does load distribution without using a failed arithmetic module, self-diagnosis is performed and the result is transferred according to the signal processing result. The effect that it is possible to perform the controlled control is achieved.

Further, in the signal processing device according to the present invention, as described above, the merger, the modules, and the local computer are connected to each other by a bus. Therefore, as compared with the conventional control using the control bus, the calculation is performed. The number of buses connected to the module can be reduced.

Further, as described above, the signal processing device according to the present invention further comprises a synchronization signal line connecting the control data generation unit, the merger and each module, and monitors the synchronization signal line, The control data is fetched from the data flowing to the bus based on a synchronization signal, and the portion of the received signal necessary for processing is fetched from the data flowing to the bus based on the interpretation thereof.
Since each module that processes signals and outputs the processing results is provided, even if there is overlap in the range of signals required for processing by multiple arithmetic modules, it is possible to transfer data one-to-one. There is no need to repeatedly transfer the same part, only the control data and the signal to be processed have to be transferred. Also, since control data is received every cycle, different control can be performed for each cycle. Produce an effect.

Further, as described above, the signal processing apparatus according to the present invention takes in the control data from the data flowing on the bus only while the signal is not processed, and based on the interpretation thereof, Since each module that takes in the portion of the received signal necessary for processing from the data flowing on the bus, processes the signal, and outputs the processing result is provided, without interruption for viewing the control data. The effect that the processing can be continued is achieved.

As described above, the signal processing apparatus according to the present invention is the first for storing the received signal.
And having a second region, while not processing the signal,
And only when it is known that the processing is completed by the next cycle, the control data is fetched from the data flowing on the bus, and the received signal of the received signal is extracted from the data flowing on the bus based on the interpretation. Of which, the parts necessary for processing are
The next signal is fetched into the second area different from the first area in which the signal being processed is stored, and the next signal is output from the time when the processing of the signal being processed ends and the output of the processing result ends. Since each module for starting the processing of 1 is provided, there is an effect that the processing can be continued without waiting for the acquisition of the signal to be processed.

As described above, the signal processing device according to the present invention has the first and second processors,
The first processor is provided with the respective modules that process the received signal that has been fetched by the first processor and fetch the control data and the necessary received signal from the bus by the second processor. This has the effect that all of the above capabilities can be used for signal processing.

Further, as described above, the signal processing device according to the present invention synthesizes the received signal and the second control data after a predetermined period from the first control data corresponding to the received signal. Since the merger for outputting the combined data to the bus is provided, it is possible to secure the time for interpreting the control data.

Further, in the signal processing device according to the present invention, as described above, the merger, the respective arithmetic modules, and the local computer are pipeline-connected, so that the control data and the processing are processed without using the control bus. There is an effect that the device can be controlled by using the data in which the signals to be combined are used.

Further, as described above, in the signal processing device according to the present invention, since some of the plurality of arithmetic modules are connected to the bus, the pipe of the portion that can divide and process the data to be processed. The effect that the number of stages of a line can be suppressed is produced.

As described above, the signal processing apparatus according to the present invention further includes a spare module, a control bus connecting the spare module, the merger, the arithmetic modules, and the local computer. When a failure occurs in any of the control data generation unit, the merger, each of the arithmetic modules, and the local computer, the spare module substitutes the function of the failed portion, so that the pipeline connection and the bus connection are performed. It is possible to cope with the failure of the arithmetic module and the control data generation unit.

Furthermore, the signal processing device according to the present invention is
As described above, the merger, the arithmetic modules, and a control bus that connects the local computer are further provided, and when a failure occurs in any of the merger, the arithmetic modules, and the local computer, Since the control data generation unit that rewrites the internal data held by the arithmetic module for processing and the control data flowing together with the received signal through the control bus is provided, it is possible to narrow the influence range of the failure. Produce an effect.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a signal processing device according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a signal processing device according to a second embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a signal processing device according to a fourth embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a signal processing device according to a fifth embodiment of the present invention.

FIG. 5 is a time chart showing the operation of the bus and the modules connected to the bus of the signal processing device according to the fifth embodiment of the present invention.

FIG. 6 is a block diagram showing a configuration of a signal processing device according to Embodiment 10 of the present invention.

FIG. 7 is a block diagram showing a configuration of a signal processing device according to an eleventh embodiment of the present invention.

FIG. 8 is a block diagram showing a configuration of a signal processing device according to a twelfth embodiment of the present invention.

FIG. 9 is a block diagram showing a configuration of a conventional signal processing device.

[Explanation of symbols]

10 control data generation part, 11 merger, 12 input / output bus, 13, 14, 15, 16 arithmetic module, 17 local computer.

Claims (14)

[Claims] 1. A plurality of arithmetic modules that process received signals input based on composite data, a control data generation unit that generates control data for controlling the plurality of arithmetic modules, the received signals and the A signal processing device comprising: a merger for synthesizing the control data generated by a control data generating unit and outputting the synthesized data; and a local computer for receiving a processing result of the arithmetic module. 2. A processing result transmission line connecting the local computer and the control data generating section, wherein the control data generating section is based on a processing result received by the local computer. The signal processing device according to claim 1, wherein 3. The arithmetic module performs a self-diagnosis, outputs the result together with a signal processing result, the local computer receives the self-diagnosis result and the processing result, and the control data generation unit obtains the self-diagnosis result. The signal processing apparatus according to claim 2, wherein control data is generated for allocating the processing of the received signal to an operation module that has not failed based on a failure condition, and load distribution that does not use the failed operation module is performed. . 4. A spare module having a function similar to that of the arithmetic module, wherein the arithmetic module performs self-diagnosis and outputs the result together with a signal processing result, and the local computer outputs the self-diagnosis result and the processing result. Receiving, the control data generation unit generates control data that allocates the processing of the received signal to the operation module that has not failed and the spare module based on the failure status obtained from the self-diagnosis result, and detects the failed operation module. The signal processing device according to claim 2, wherein the load distribution is performed so as not to be used. 5. The signal processing device according to claim 2, wherein the merger, the modules, and the local computer are connected by a bus. 6. A synchronization signal line for connecting the control data generation unit, the merger, and each module is further provided, and each module monitors the synchronization signal line and flows to the bus based on the synchronization signal. The control data is fetched from the stored data, the portion of the received signal necessary for processing is fetched from the data flowing to the bus based on its interpretation, the signal is processed, and the processing result is output. The signal processing device according to claim 5, wherein 7. Each of the modules fetches the control data from the data flowing on the bus only while the signal is not processed, and based on the interpretation, the control data is fetched from the data flowing on the bus. 7. The signal processing device according to claim 6, wherein a portion of the received signal necessary for processing is fetched, the signal is processed, and the processing result is output. 8. Each module has first and second areas for storing the received signal, and the processing is completed while the signal is not processed and by the next cycle. Only when it is known, the control data is fetched from the data flowing on the bus, and based on its interpretation, the portion of the received signal that is necessary for processing is processed from the data flowing on the bus. The signal is stored in the second area different from the first area in which the signal is stored, and the processing of the next signal is started from the time when the processing of the signal being processed is finished and the output of the processing result is finished. The signal processing device according to claim 6, which is started. 9. Each of the modules has a first processor and a second processor, the first processor processes a received signal received, and the second processor receives the control data and the necessary data. 9. The signal processing device according to claim 6, wherein the signal processing device takes in a received signal from the bus. 10. The merger combines the received signal with second control data after a predetermined period from the first control data corresponding to the received signal and outputs the combined data to the bus. The signal processing device according to claim 6, wherein 11. The signal processing device according to claim 2, wherein the merger, the arithmetic modules, and the local computer are pipeline-connected. 12. The signal processing device according to claim 11, wherein a part of the arithmetic modules among the arithmetic modules are bus-connected. 13. A control module, further comprising: a spare module; a control bus connecting the spare module, the merger, the arithmetic modules, and the local computer, and the control data generation unit, the merger, the arithmetic modules, and 13. The signal processing device according to claim 12, wherein when a failure occurs in any of the local computers, the spare module substitutes the function of the failed part. 14. The system further comprises a control bus that connects the merger, the arithmetic modules, and the local computer, and the control data generation unit is provided in any of the merger, the arithmetic modules, and the local computer. 13. The signal processing according to claim 12, wherein when a failure occurs, the internal data held by the arithmetic module for processing and the control data flowing together with the received signal are rewritten via the control bus. apparatus.