JP2000148533A - Tracing method and device to be used for multiprocessor system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the cost of development and to improve tracing performance. SOLUTION: In the tracing method, a certain processor 10-i out of plural processors constituting a multiprocessor system is driven as a tracer. Trace information flowing on a global bus 12 by the operation of plural processors 10-j other than the proces-sor 10-i acting as a tracer is entered into a bus bridge 120-i by a tracer circuit in the processor 10-i, and stored in a CTAG RAM connected to the bus bridge 120-i through a CTAG interface in the bus bridge 120-i to sample the trace information.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a tracing method and a tracing device for sequentially monitoring data and commands in a multiprocessor system.

[0002]

2. Description of the Related Art Conventionally, as this kind of tracing device,
Japanese Patent Application Laid-Open No. 6-223046 (hereinafter abbreviated as a first publication) is provided. In the system described in the first publication, as shown in FIG. 9, trace data processed by the processor 15 in each of the processor modules 31, 32, and 33 and flowing to the local bus 20 is transmitted to each of the processor modules 31, 32, and 33. The trace data is transferred to the trace device 3 via the trace interface 19 therein, and the trace data is transferred to the trace memory 4 via the trace interface 8 and the local bus data input unit 10 and stored in the trace memory 4. Also, based on the timer value set in the trace timer 6 under the control of the trace control unit 5, the trace data processed by the processor 15 of each of the processor modules 31, 32 and 33 and flowing to the common bus 1 via the bus interface 17. Are traced to the trace memory 4 via the buffer circuits 13 and 14 and the common bus data input unit 9 at the same time as the trace data flowing to the local bus 20, or one of the arbitrarily selected trace data is traced to the trace memory 4. Or to be configured. With this configuration, the trace data flowing through the local bus 20 and the trace data flowing through the common bus 1 can be simultaneously traced to the trace memory 4, or one of the arbitrarily selected trace data can be traced to the trace memory 4. .

A tracing device described in Japanese Patent Application Laid-Open No. 9-114695 (hereinafter abbreviated as "second publication") is also known. In this tracing device, as shown in FIG. 10, usually, in order to perform a double check, a master is sent from the master / slave control circuit 1 to the trace writing circuit 8 and a slave is sent to the trace writing circuit 13. A master / slave signal 2 is supplied, and a tracer control signal is supplied from the tracer control circuit 4 to the trace writing circuits 8 and 13 in a mode for instructing normal writing and a trace device control signal for instructing microprogram writing control. Is done. Therefore, the trace writing circuits 8 and 13 write the same trace information to the trace memories 9 and 14 of the processors 5 and 10 via the trace writing circuits 8 and 13 regardless of the master / slave control signal 2.

At the time of debugging or occurrence of a fault, the master / slave signal 2 from the master / slave control circuit 1 to the trace writing circuit 8 and the trace writing circuit 13
Is the same as the case of the double check, except that the tracer control circuit 4 instructs the trace writing circuits 8 and 13 to write only the branch instruction and the tracer control signal 4 to instruct the microprogram write control. Is supplied. Therefore, the trace writing circuit 8
Has been designated as a master, the trace information 7 designated by a normal microprogram is written to the trace memory 9 regardless of the mode designated by the tracer control signal 4, and the trace writing circuit 13 Since the slave is designated, the trace information of only the branch instruction designated by the tracer control signal 4 is written to the trace memory 14. With this configuration, the same trace information can be traced in the trace memory 9 and the trace memory 14, and the trace memory 9 and the trace memory 1 can be traced.
4, the trace information can be traced in different modes. Each of the trace apparatuses disclosed in the first and second publications can trace the trace information in the multi-program system to the trace memory.

[0005]

However, in the conventional tracing apparatus described in the first publication, a tracing apparatus is provided separately from each processor module of the multiprocessor system, and the tracing function is not provided by the multiprocessor. In the tracing device described in the second publication, the tracing function cannot be constructed unless a tracing function is provided for each processor of the multiprocessor system. It is. Therefore, in any of the tracing apparatuses described in the publications, it is necessary to design and implement hardware separately from the multiprocessor system when constructing the tracing apparatus in the multiprocessor system.

Therefore, not only is the development cost required for the design and mounting increased, but also when the trace function is to be mounted on an LSI, there is a restriction on the amount of gates and the like.
There is a problem that a compromise must be made between the memory capacity required for the tracing device, the type of data to be traced, and the like, and the above-mentioned restrictions.

The present invention has been made in view of the above circumstances, and has as its object to provide a tracing method and a tracing apparatus for a multiprocessor system in which the multiprocessor system itself has a tracing function.

[0008]

According to a first aspect of the present invention, there is provided a multi-processor system in which a plurality of processors are connected to a bus. The present invention relates to a tracing method for sequentially tracing data and commands, wherein one of the plurality of processors, which has storage means and can be set to a trace mode, is set to a trace mode, whereby the specific processor is set. Data and commands flowing in the bus are sequentially drawn into the specific processor by the operation of the other processor, and the drawn data and commands are sequentially stored in the storage means of the specific processor to collect trace information. .

According to a second aspect of the present invention, there is provided a trace method used in the multiprocessor system according to the first aspect, wherein the setting of the trace mode is performed via a diagnostic bus of the multiprocessor system. I have.

According to a third aspect of the present invention, there is provided a trace method used in the multiprocessor system according to the first aspect, wherein the setting of the trace mode is performed via a signal line dedicated to the trace mode. I have.

[0011] The invention according to claim 4 is based on claim 1,
4. The tracing method used in the multiprocessor system according to 2 or 3, wherein a tag information storage unit of a bus bridge that connects a local bus in the processor and a global bus of the multiprocessor system is provided in the specific processor and the storage unit. And the trace information is collected.

According to a fifth aspect of the present invention, there is provided a trace apparatus used in a multiprocessor system for sequentially following data and commands flowing through a bus when a processor of the multiprocessor system in which a plurality of processors are connected to a bus is operating. According to the present invention, among a plurality of processors connected to the bus, one specific processor which has storage means and can be set to a trace mode, and the one specific processor connected to the one specific processor and Mode setting means for setting a trace mode; pull-in means connected to the bus for drawing the data or command flowing on the bus to the one specific processor by an operation of a processor other than the one specific processor;
Storage control means for sequentially storing the data and commands which have been drawn into the one specific processor by the pull-in means in the storage means of the specific processor.

According to a sixth aspect of the present invention, there is provided a trace apparatus used in the multiprocessor system according to the fifth aspect, wherein the mode setting means includes a diagnostic bus of the multiprocessor system. And

According to a seventh aspect of the present invention, there is provided a trace device used in the multiprocessor system according to the fifth aspect, wherein the mode setting means includes a signal line dedicated to a trace mode. And

[0015] The invention described in claim 8 is based on claim 5,
8. The tracing device used in the multiprocessor system according to 6 or 7, wherein the bus is a global bus to which a plurality of processors are connected, and wherein the storage means includes a local bus in the processor and the global bus. And a tag information storage means of a bus bridge connected between them.

[0016]

An embodiment of the present invention will be described below with reference to the drawings. The description will be specifically made using an embodiment. FIG. 1 is a block diagram showing an electric configuration of a multiprocessor system including a tracer (trace device) according to a first embodiment of the present invention. FIG. 2 is a block diagram showing a CPU and a multiprocessor operating as the tracer. FIG. 3 is a block diagram showing an electrical configuration of another CPU constituting the processor system, FIG. 3 is a block diagram showing an electrical configuration of a bus bridge in the CPU operating as the tracer, and FIG. 4 is operating as the tracer. FIG. 3 is a detailed diagram of a CTAG interface of a bus bridge in a CPU. The tracer of this example relates to a device that operates one CPU constituting a multiprocessor as a tracer and collects trace information flowing on a global bus of the multiprocessor. As shown in FIG. A plurality of CPUs 1
A CPU 10-i configured to enable tracing among 0-1 to 10-N, and operates only as a tracer when the CPU 10-i is set to perform a tracing function as described later. .

As shown in FIG. 2, the CPU 10-i has a plurality of processor (EPU) groups 105-i to 108-i, a local bus 110-i, and respective processor groups 105-i to 108-i. i and local bus 110-
i, store in-caches 101-i to 104-i, and a bus bridge 120-i connected between the local bus 110-i and the global bus 12; A tracing means for performing a tracing function is constructed in i. The store-in cache 101-i includes a plurality of processor groups 105-i.
The store in cache 102-i is shared by the plurality of processor groups 106.
-I is a shared cache shared by a plurality of processor groups 1
07-i is a shared cache, and the store in cache 104-i is a shared cache shared by a plurality of processor groups 108-i. The CPUs other than the CPU 10-i are, as shown in FIG.
Except for -i, the configuration is the same as that of the CPU 10-i. Therefore, the other CPUs are denoted by reference numerals 10-j (j represents any one of 1, 2,..., N except i), and a plurality of processors (EPUs) are denoted by reference numerals 10-j. , 1
05-j through 108-j, and 11 for the local bus
0-j, each of the processor groups 105-j through 108-
j and the local bus 110-j are denoted by 101-j through 104-j, and the bus bridge connected between the local bus 110-j and the global bus 12 is FIG. 2 shows the CPU 10-j on behalf of the CPU 10-j.

Bus bridge 120-i of CPU 10-i
CPU1 to which the bus bridge 120-i belongs
There is a first operation mode in which a trace function is performed with 0-i designated as a tracer, and a second operation mode in which the CPU 10-i performs a normal operation as a bus bridge. Bus bridge 12 operating in first operation mode
0-i are a global bus interface 121 connected to the global bus 12, a tracer circuit 126 connected to the global bus interface 121, and a diagnostic bus interface 129 connected to the diagnostic bus 22, as shown in FIG. , A CTAG interface 128 connected to the tracer circuit 126 and the diagnostic bus interface 129, and a CTAG memory 130 connected to the CTAG interface 128. The diagnostic bus interface 129 receives a tracer command input from the console of the service processor 26,
, A logic circuit which is set by the tracer command and outputs a 2-bit tracer command signal (CMD) and a 1-bit mode signal (MODE) is provided. CPU 10 placed in this first operating state
-I other circuit parts are in some operation state on the hardware, but are separated from other CPUs on the software, so there is no operation from the viewpoint of the software. CPU 10-
i operates only as a tracer.

The bus bridge 120-i operating in the second operation mode includes a local bus interface 122, a local buffer (L-BUF) 123 in FIG.
Global bus interface 121, global buffer (G-BUF) 124, and CTAG control unit 125
And a CTAG interface 128 are provided. The CTAGRAM 130 is connected to the bus bridge 120-i. The CTAGRAM 130 is an SRA
M. The CTAG control unit 125 is connected to the outputs of the global bus interface 121 and the local bus interface 122 and is also connected to the CTAG interface 128. The CTAG control unit 125 monitors the operations of the global bus 12 and the local bus 110, thereby providing a known bus coherency. Control is performed to maintain the normality of data processing by maintaining it.

The CTAG interface 128 shown in FIG. 3 operates as a trace mode interface for performing a trace function by being designated as a tracer as described above, and a second mode for performing a normal operation. There are cases. As shown in FIG. 4, the configuration of the CTAG interface 128 in the first case is such that an address counter 151 and a diagnostic bus interface 129 are provided.
"1" mode signal (MODE) output from
(“1” indicates a high level indicating a trace operation.) In the normal operation, the count value of the address counter 151 is used as an address instead of the address output from the CTAG control unit 125 in the normal operation, via the output buffer 155. Output selector 152 and diagnostic bus interface 1
A selector 153 that outputs write data transferred from the tracer circuit 126 in place of the write data output from the CTAG control unit 125 in a normal operation in response to the mode signal of “1” output from the selector 29; An input / output buffer 157 connected to the output of
In response to the 2-bit tracer command signal (CMD) output from the diagnostic bus interface 129 and the “1” mode signal, a 2-bit tracer command signal is output to the CTAGRAM 130 via the output buffer 156, and the count-up signal is output. In addition to the output to the address counter 151, an input / output switching signal for designating an operation as an input buffer in the case of a tracer start command is supplied to the input / output buffer 157, and an input / output switching in which a tracer read command does not designate the operation as an input buffer And a controller 154 for supplying signals to the input / output buffer 157. The output of the input / output buffer 157 is connected to the CTAG controller 125 and the diagnostic bus interface 129.

The CTAG interface 128 in the second case is an interface between the CTAG control unit 125 and the CTAG RAM 130 for providing the normal function of the bus bridge 120-i when the CPU is in a normal operation state. Work to take. C in this case
The TAG interface 128 also has a configuration similar to that of the first case, in which the selector 152 and the output buffer 15 are provided.
5, an input / output buffer 157, a controller 154, and an output buffer 156.
The control form differs from the first case as follows. The selector 152 is connected to the diagnostic bus interface 129.
Instead of the address output from the address counter 151 in response to the "0" mode signal ("0" indicates a low level indicating normal operation) output from the CTAG.
The address output from the control unit 125 is stored in the output buffer 1
55, and output to the selector 153.
The CTAG controller 12 replaces the write data transferred from the tracer circuit 126 in response to the “0” mode signal output from the diagnostic bus interface 129.
5 is controlled to output the write data output from the diagnostic bus interface 129, and the controller 154 controls the 2-bit tracer command signal in response to the 2-bit tracer command signal output from the diagnostic bus interface 129 and the “0” mode signal. Through the output buffer 156
In addition to the output to the AM 130 and the input / output switching signal for operating the input / output buffer 157 as an input buffer at the time of a write command instructing the writing to the CTAG RAM 130, the input / output switching signal is supplied to the input / output buffer 157.
Input / output buffer 15 when reading from RAM 130
7 is controlled so as to supply an input / output switching signal to the input / output buffer 157 that does not operate the input / output 7 as an input buffer.

When the CPU 10-i operated as a tracer in this example is supplied with the mode signal "0" as the mode signal and the trace function is released, the CPU 10-i performs the same normal operation as the other CPUs. I do. In that sense, the multiprocessor includes a plurality of CPUs 10-
1 to 10-N, a main storage unit (MMU) 14, a global bus 12 that can mutually connect the plurality of CPUs 10-1 to 10-N and the main storage unit 14, and a plurality of CPUs 1 to 10-N.
Input / output processors (IOPs) 18-1 to 18-N (1
8-2 to 18-N are not shown), and a disk device 20- connected to the input / output processors 18-1 to 18-N.
1 to 20-N (20-2 to 20-N are not shown)
A diagnostic bus 22 connected to each of the plurality of CPUs 10-1 to 10-N; a diagnostic processor (GDP) 24 connected to the diagnostic bus 22; and a service processor (SVP) 26 connected to the diagnostic processor 24. It is composed of

Next, the operation of this example will be described with reference to FIGS. At the start of the operation or when it is desired to collect the trace information in the operating multiprocessor system, a tracer command is input from the console of the service processor 26. The tracer command includes three types of commands, that is, a tracer start command, a tracer stop command, and a tracer read command. At the start of tracing, a tracer start command is input from the console of the service processor 26. This tracer start command is input to each CPU in the multiprocessor system via the diagnostic processor 24 and the diagnostic bus 22. The diagnostic bus interface 129 of the bus bridge 120-i in the CPU 10-i to which the trace function is assigned in advance receives a tracer start command and receives a 2-bit tracer command signal (CMD) and a mode signal (MO) of "1".
DE), a logic circuit for outputting CP
The U10-i operates as a CPU for which a trace is designated by the tracer start command, and outputs a 2-bit tracer start command signal and a mode signal of "1" from the diagnostic bus interface 129 of the bus bridge 120-i. You. The mode signal of "1" is output a predetermined time earlier than the output of the 2-bit tracer start command signal.

The mode signal of "1" is supplied to the selector 15
2 and the selector 153. The selector 152 receiving this mode signal replaces the address input from the CTAG control unit 125 with the address counter 15.
The address output from 1 is output. The address is supplied to the CTAGRAM 130 via the output buffer 155. Also, a selector 153 that receives a mode signal
Is the write data input from or input from the CTAG control unit 125 (the store-in cache 101
Of the tracer circuit 126 in place of
It outputs the write data input from. Also, the 2-bit tracer start command signal output from the diagnostic bus interface 129 and the mode signal of “1” are
The tracer start command signal is supplied to the controller 154 and transmitted from the controller 154 to the CTAGRAM 130 via the output buffer 156. The controller 154 also supplies an address count-up signal to the address counter 151 to cause its count-up operation, and operates the input / output buffer 157 as an input buffer (passes data through the input / output buffer 157 through). The output control signal is sent to the output enable of the input / output buffer 157.

At this time, the write data output from the trace circuit 126 is output to one or more other CPUs constituting the multiprocessor system, that is, one or more CPUs that are performing normal operations other than the CPU designated as the tracer. The processing data (trace information) sequentially generated in time series by the CPU "and flowing on the global bus 12. The processing data flowing on the global bus 12 includes processing data related to cache coherency performed in the bus bridge 120-j in the CPU 10-j. This trace information is drawn into the tracer circuit 126 via the global bus interface 121 in the bus bridge 120-i of the CPU 10-i operating as a tracer. The trace information includes a synchronization signal on the bus, the number of the processor that requested the bus, the number of the processor that acquired the bus, the command address, and the like.
It is not necessary to capture these at once, but a plurality of trace modes may be provided to determine the type of information to be captured for each mode. In addition, the output buffer 15
6, a 2-bit tracer start command signal for instructing the start of writing is supplied to the CTAGRAM 130. Under the control of the 2-bit tracer start command signal, the input / output buffer 157 sends the CTAGRAM 13
Each of the trace information sequentially supplied in time series to 0 is sequentially written to the storage position of the CTAGRAM 130 specified by each address sequentially output in time series from the output buffer 155.

Then, at the end time of the writing of the trace information, a trace stop command is inputted from the console of the service processor 26. This command is received via the diagnostic processor 24 and the diagnostic bus 22 by the CPU 10-i operating as a tracer. The CPU
A 2-bit tracer stop command signal is output from the diagnostic bus interface 129 in the 10-i bus bridge 120-i. The mode signal at this time is
It is in the signal state of the tracer mode by the signal of "1". Upon receiving the 2-bit trace stop command signal, the controller 154 supplies the trace stop command signal to the CTAGRAM 130 via the output buffer 156, and stops writing trace information to the CTAGRAM 130.

After the writing is stopped, a trace read command is input from the console of the service processor 26. This command is sent to the CPU 10-i operating as a tracer via the diagnostic processor 24 and the diagnostic bus 22.
Received at. Bus bridge 1 of the CPU 10-i
A 2-bit tracer read command signal (CMD) is output from the diagnostic bus interface 129 in 20-i. The mode signal at this time is a signal of “1”,
The signal is in the tracer mode. The controller 154 that receives the trace read command signal supplies a count-up signal to the address counter 151 and supplies an address from which trace information is read from the address counter 151 to the CTAGRAM 130 via the output buffer 155. CTAGRAM1 responding to this read address
The trace information is read from 30. CTAGRAM13
The trace information read from 0 is collected by the diagnostic processor 24 via the diagnostic bus interface 129 and the diagnostic bus 22, and is used for verifying the operation of the CPU.

As described above, according to the configuration of this example, the normal operation of the bus bridge in one CPU constituting the multiprocessor system is temporarily canceled, and at the same time, the bus bridge performs the trace function. Since the configuration of the bus bridge is reconfigured, the existing CTAGRAM in the bus bridge can be used as a trace memory in addition to its original storage function in providing a trace function in the multiprocessor system. There is no need to newly equip the processor system with a dedicated memory for tracing, and the cost of providing a tracer in a multiprocessor system can be reduced. In addition, a constraint that occurs when a dedicated memory for tracing is provided in an LSI,
The limitation that only a limited amount of memory can be used for storing trace information due to the limitation of the accommodability of LSI and the cost is greatly eased by sharing the trace memory of the CTAGRAM of the bus bridge. Performance can be improved.

Second Embodiment FIG. 5 is a block diagram showing an electric configuration of a multiprocessor system including a tracer according to a second embodiment of the present invention. FIG. 6 is a diagram showing a CPU and a multiprocessor operating as the tracer. FIG. 7 is a block diagram showing an electrical configuration of another CPU constituting the system, FIG. 7 is a block diagram of an electrical configuration of a bus bridge in the CPU operating as the tracer, and FIG. 8 is a CPU operating as the tracer. FIG. 2 is a detailed view of a CTAG interface of a bus bridge in the embodiment. The configuration of this embodiment is significantly different from that of the first embodiment in that a signal line 22A dedicated to tracing is provided instead of the diagnostic bus 22, and a trace command is transmitted to the bus bridge 120-i through the signal line 22A. The point is that the data is transferred to the interface 129A. That is,
The trace processor command is transferred from the service processor 26 to the diagnostic interface 129A of the bus bridge 120-i via the diagnostic processor 24 and the signal line 22A. The signal line interface 129A outputs a 2-bit trace command signal and a "1" or "0" mode signal corresponding to the type of the trace command in response to the tracer command. The point is that the trace information on the global bus 12 is stored in the CTAGRAM 130 of the bus bridge 120-i according to the trace command signal and the mode signal, so that the bus bridge 120-i is provided with a trace function. In other respects, since the configuration of this example is the same as that of the first embodiment, in FIGS. 5 to 8, the same components as those in FIGS. 1 to 4 are denoted by the same reference numerals. And the description is omitted.

The operation of this example will be described with reference to FIGS. At the start of the trace, the trace start command is transferred to the CPU 10-i to which the trace function in the multiprocessor system is assigned in advance via the diagnostic processor 24 and the signal line 22A, and a 2-bit trace start command is transmitted from the signal line interface 129A. A signal and a mode signal of "1" are output.
The controller 154 responding to these two signals outputs a 2-bit trace start command signal to the output buffer 15.
6, the address is output from the address counter 151, and the address is output to the CTAG RAM 13 via the output buffer 155.
0, and write data from the tracer circuit 126, that is, the trace information, to the input / output buffer 157.
And supplies it to the CTAGRAM 130. This allows
The trace information is written to a storage location of the CTAGRAM 130 specified by the address supplied from the address counter 151. This writing is performed for each piece of processing data flowing on the global bus 12, that is, for each piece of trace information. The end of the writing of the trace information is ended by the trace stop command generated from the service processor 26 in the same manner as in the first embodiment. The reading of the trace information from the CTAGRAM 130 is performed in the same manner as in the first embodiment by a trace read command generated from the service processor 26.

As described above, according to the configuration of this example, the bus bridge in one CPU constituting the multiprocessor system is temporarily released from the normal operation, and the bus bridge is reconstructed into the tracer. In providing a trace function to the multiprocessor system, the existing CTAGRAM in the bus bridge can be used as a trace memory in addition to its original storage function. Is eliminated, and the cost of providing a tracer in a multiprocessor system can be reduced. In addition, a constraint that occurs when a dedicated memory for tracing is provided in an LSI, that is, a constraint that only a memory having a limited capacity can be used for storing trace information due to limitations on the accommodability and cost of the LSI. However, the use of the bus bridge as the trace memory of the CTAGRAM is greatly eased, so that the performance as a tracer can be improved.

Although the embodiments of the present invention have been described in detail with reference to the drawings, the specific structure of the present invention is not limited to these embodiments, and departs from the gist of the present invention. Even if there is a change in the design within the range not to be included, the present invention is included. For example, although the CPU has a configuration including a bus bridge, each CPU in the multiprocessor system includes a memory, and the memory is connected to a bus to which the CPU is connected via an interface. The memory is used for purposes other than tracing,
A multiprocessor system may be configured such that when the CPU is designated as a tracer, the memory can be switched to be used for tracing purposes.
Also in this case, it is optional whether the trace command is transferred to the CPU that can function as a tracer via the diagnostic bus, or transferred to the CPU via a signal line dedicated to trace.

[0033]

As described above, according to the configuration of the present invention, the normal operation of one processor constituting the multiprocessor system is temporarily canceled, and at the same time, the processor is reconfigured as a tracer. Therefore, when providing the trace function in the multiprocessor system, the memory of the CPU can also be used as a trace memory.
There is no need to newly equip U with a dedicated memory for tracing, and the cost of providing a tracer in a multiprocessor system can be reduced. In addition, when a dedicated memory for tracing is to be provided in an LSI on which a CPU is mounted, only a limited amount of memory is used for storing trace information due to limitations in LSI storability and costs. The constraint that it can not be
The use of the memory incorporated in the U as the trace memory is greatly eased, so that the performance as a tracer can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an electrical configuration of a multiprocessor system including a tracer according to a first embodiment of the present invention.

FIG. 2 is a block diagram illustrating an electrical configuration of a CPU that operates as the tracer and another CPU that configures a multiprocessor system.

FIG. 3 is a block diagram of an electrical configuration of a bus bridge in a CPU that operates as the tracer.

FIG. 4 is a detailed view of a CTAG interface of a bus bridge in the CPU operating as the tracer.

FIG. 5 is a block diagram showing an electrical configuration of a multiprocessor system including a tracer according to a second embodiment of the present invention.

FIG. 6 is a block diagram illustrating an electrical configuration of a CPU that operates as the tracer and another CPU that configures a multiprocessor system.

FIG. 7 is a block diagram of an electrical configuration of a bus bridge in the CPU that operates as the tracer.

FIG. 8 is a detailed diagram of a CTAG interface of a bus bridge in a CPU that operates as the tracer.

FIG. 9 is an explanatory diagram for explaining a conventional technique.

FIG. 10 is an explanatory diagram for explaining another conventional technique.

[Explanation of symbols]

10-i CPU (processor) 10-j CPU (processor) 12 Global bus (bus) 22 Diagnostic bus (part of mode setting means) 22A Signal line dedicated to tracer (part of mode setting means) 24 Diagnostic processor (mode 26 Service processor (part of mode setting means) 121 Global bus interface (part of pull-in means) 126 Tracer circuit (part of pull-in means) 128 CTAG interface (remaining part of pull-in means) 129 Diagnostic bus Interface (remaining mode setting means) 129A Signal line interface (remaining mode setting means) 130 CTAGRAM (storage means) 151 Address counter (part of storage control means) 152 Selector (part of storage control means) 153 Selector (storage) Control means 154 Controller (part of storage control means) 155 Output buffer (part of storage control means) 156 Output buffer (part of storage control means) 157 I / O buffer (remaining storage control means)

Claims (8)

[Claims] 1. A tracing method for sequentially following data and commands flowing through a bus when a processor of a multiprocessor system in which a plurality of processors are connected to a bus is operating. By setting one specific processor that can be set to the trace mode to the trace mode, data and commands flowing through the bus by the operation of a processor other than the specific processor are sequentially drawn into the specific processor. A tracing method used in a multiprocessor system, wherein the acquired data and commands are sequentially stored in storage means controlled by the specific processor to collect trace information. 2. The tracing method according to claim 1, wherein the setting of the trace mode is performed via a diagnostic bus of the multiprocessor system. 3. The tracing method according to claim 1, wherein the setting of the trace mode is performed via a signal line dedicated to the trace mode. 4. The specific processor causes the specific processor to use the tag information storage means of the bus bridge connecting the local bus in the specific processor and the global bus of the multiprocessor system as the storage means, and collects the trace information. 4. The method according to claim 1, wherein:
A tracing method used in the described multiprocessor system. 5. A tracing device used in a multiprocessor system for sequentially following data and commands flowing on a bus when a processor of the multiprocessor system in which a plurality of processors are connected to a bus is operating, One of the plurality of processors connected to the storage device and having a storage unit and capable of being set in a trace mode; and being connected to the one specific processor and setting the one specified processor in a trace mode. Mode setting means, connected to the bus, and a pull-in means for pulling the data or command flowing through the bus to the specific processor by an operation of a processor other than the one specific processor; The data or command Tracer for use in a multiprocessor system characterized in that a storage control means for sequentially stored in the storage means of the constant-processor. 6. The tracing apparatus according to claim 5, wherein said mode setting means includes a diagnostic bus of a multiprocessor system. 7. The trace apparatus used in a multiprocessor system according to claim 5, wherein said mode setting means includes a signal line dedicated to a trace mode. 8. The bus is a global bus to which a plurality of processors are connected, and the storage means is a bus bridge connected between a local bus in the one specific processor and the global bus. 8. A trace device used in a multiprocessor system according to claim 5, wherein said tag information storage means is used.