JPH0923352A - Horizontal synchronization detecting circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To correctly acquire the synchronization again even at the time of erroneously detecting the synchronization of a half H phase. SOLUTION: A synchronization detection pulse output part 2 detects a synchronizing part to generate a pulse, and this pulse is supplied to an H counter 5, which generates a half H killer, a reload signal, and a horizontal synchronizing signal, as the load signal through a load mask part 3 which takes the name H killer signal as the mask control signal. When the H counter 5 is operated by the synchronization of the half H phase, the synchronization detection pulse is supplied to a circuit part 10, which outputs a pulse in the low level at the time of synchronization detection in the period of the low level of the half H killer, and a circuit part 11 which outputs a pulse in the high level at the time of synchronization detection in the period of the high level of the half H killer. A reset pulse and a clock pulse are supplied to a reload mask detection counter 12, and the reload signal is masked when the output of the counter 12 is 2 or larger, thus acquiring the synchronization of the normal phase again.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a horizontal sync detection circuit, and more particularly to an NTSC composite signal horizontal sync detection circuit.

[0002]

2. Description of the Related Art FIGS. 10 and 11 show NTSC (Nation
al Television System Committee) shows a conventional circuit configuration for generating a horizontal synchronizing signal from a composite signal.

The detection of the synchronization part of the NTSC composite signal (digitally encoded NTSC composite signal) is generally performed by detecting that the sync slice level or less continues. Here, as the sync slice level value, in the case of the D2 format, since the pedestal level is h3C (h indicates hexadecimal display) and the sync chip level is h04, a value in between, especially an intermediate value h20, etc. Is used.

Since the color phase of four cycle period is superimposed during the video period, it is unlikely that the sync slice level and below will continue continuously. Therefore, this is used to detect the synchronization part.

Referring to FIG. 10, the pulse output unit 2 upon synchronization detection considers that the input data of the NTSC composite signal is below the sync slice level for a certain number of clocks and determines that the input data is synchronous, and outputs a pulse output of one clock. Assumed to be performed. This becomes a load signal of the H counter 5 for counting 1H (one horizontal period), and the H counter 5 generates a horizontal synchronizing signal.

The above-mentioned pulse output from the pulse output unit 2 upon synchronization detection is normally output once per 1H (one horizontal period), but is output twice per 1H during the vertical synchronization period or equalization pulse period. Become.

At this time, the load signal detected in the half H (= 1 / 2H) phase becomes a problem.

If the load signal detected in the half H phase is used as it is, the H counter 5 malfunctions.
The half H killer generation unit 6 generates a half H killer signal and masks this load signal.

With this configuration, the H counter 5 can be rotated by one load to 1H (counting up from 0), and the horizontal synchronization generator 7 can output the horizontal synchronization signal synchronized with the input signal. .

However, in the conventional horizontal synchronizing circuit shown in FIG. 10, since there is no mechanism for reloading by itself, it is not possible to perform free run, and when there is no input signal, the horizontal synchronizing signal cannot be generated. .

On the other hand, in the conventional horizontal synchronizing circuit shown in FIG. 11, even if the synchronizing portion is not detected, 1H
Since (one horizontal period) is 910 samples, 9
It is provided with a reload generator 8 that generates a reload signal so as to rotate in 10 cycles.

Normally, it is locked to the input, and while the half H phase synchronization is not supplied to the H counter 5 as a load signal as in FIG. 10, it is configured so as to be free-run even when there is no NTSC composite signal input. A sync signal is output.

[0013]

As described above, the conventional horizontal synchronizing circuit shown in FIG. 10 does not control the reloading of the H counter by itself and always relies on the input. There was a problem.

Although the conventional horizontal synchronizing circuit shown in FIG. 11 can perform free-running as compared with the conventional example shown in FIG. 10, for example, when the power is turned on, the half-H phase synchronization is wrong and the load signal of the H counter is mistaken. If it is supplied as, on the contrary, half H is applied to the original normal phase synchronization.
I will put a mask on with a killer, and as a result,
There is a problem that the input cannot be locked forever. Furthermore, the Half H Killer
1 that is detected synchronously from the vertical sync period or equivalent pulse period
If the gate (load mask part 3) is opened at a position (time point) that does not match the load signal to the H counter 5 twice for H, the load signal is supplied to the H counter 5 twice for 1H. Therefore, there is a problem that it causes a malfunction.

Recently, not only NTSC standard video data but also compressed data, user data, etc.
It is often applied during the video data period of the composite signal, and in such a case, there is a pattern that is detected as being synchronized even during the video data period, and synchronization false detection frequently occurs. There is a point.

Therefore, it is an object of the present invention to solve the above problems and provide a horizontal synchronizing circuit which enables correct synchronization even if the half H phase synchronization is erroneously detected.

[0017]

In order to achieve the above object, the present invention provides means for inputting an NTSC composite signal to generate a pulse signal at the time of synchronization detection, and inputting the pulse signal to mask a half H killer signal. Load mask means for masking the pulse signal as a control signal, H counter means for starting the count operation when the load terminal is active, and half H killer for receiving the output of the H counter means and generating the half H killer signal. Generating means, reload generating means for receiving the output of the H counter means and generating a reload signal for the H counter, and the H
Horizontal sync generation means for inputting the output of the counter means and outputting a horizontal sync signal, reload mask means for masking transmission of the reload signal to the H counter, and mask control of the reload signal for the reload mask means. A reload mask detecting means for supplying a signal, the output of the load mask means and the output of the reload mask means are connected to a load terminal of the H counter, and the reload mask detecting means is configured to detect the half H killer signal. When the pulse signal is obtained during the active period, the pulse signal is counted, and when the count value is a predetermined number or more,
A horizontal synchronizing circuit is provided, which outputs a signal for controlling the reload mask means to mask the reload signal.

In the present invention, preferably, the reload mask detecting means includes a counter, and means for supplying a reset signal to the counter when the pulse signal is obtained during a period when the half H killer signal is inactive. , Means for supplying the counter as a clock signal when the pulse signal is obtained while the half H killer signal is active, and means for detecting whether or not the output of the counter is 2 or more. A signal for masking the reload signal is output when it is detected that the output of the counter is 2 or more.

According to the present invention, means for inputting an NTSC composite signal to generate a pulse signal at the time of synchronization detection, half H killer mask means for masking transmission of a half H killer signal, and inputting the pulse signal, the half H killer A load mask means for masking the pulse signal using the output of the killer mask means as a mask control signal, an H counter means for starting a count operation when the load terminal is active, and an output of the H counter means for inputting a half H killer signal. , A half H killer generating means, a reload generating means for inputting the output of the H counter means to generate a reload signal of the H counter, and a horizontal synchronizing means for inputting the output of the H counter means and outputting a horizontal synchronizing signal. Generating means and a mass of the half H killer signal to the half H killer mask means. Half H killer mask detection means for supplying a control signal, the output of the load mask means and the output of the reload generation means are connected to the load terminal of the H counter, and the half H killer mask detection means When the pulse signal is obtained while the half H killer signal is active, the pulse signal is counted, and when the counted value is equal to or more than a predetermined number, the half H killer mask means is operated to the half H killer mask means. Provided is a horizontal synchronizing circuit which outputs a signal for controlling so as to mask the signal.

In the present invention, preferably, the half H killer mask detecting means supplies a reset signal to the counter and the counter when the pulse signal is obtained during a period when the half H killer signal is inactive. Means and
Means for supplying a clock signal to the counter when the pulse signal is obtained while the half H killer signal is active, and means for detecting whether the output of the counter is 2 or more. A signal for masking the half H killer signal is output when it is detected that the output of the counter is 2 or more.

The present invention comprises means for inputting an NTSC composite signal and generating a pulse signal at the time of synchronization detection, and load mask means for masking the pulse signal with a data killer signal for masking the pulse signal during a data period as a mask control signal. And H counter means for starting the counting operation when the load terminal is active, data killer generating means for inputting the output of the H counter means and generating the data killer signal, and inputting the output of the H counter means for inputting the data. Reload generation means for generating a reload signal of the H counter, horizontal synchronization generation means for receiving the output of the H counter means and outputting a horizontal synchronization signal, and reload mask means for masking transmission of the reload signal to the H counter. And mask control of the reload signal with respect to the reload mask means. And a reload mask detecting means for supplying a signal, the output of the load mask means and the output of the reload mask means are connected to the load terminal of the H counter, and the reload mask detecting means outputs the data killer signal. When the pulse signal is obtained during the active period, the pulse signal is counted, and when the count value is a predetermined number or more, the reload mask means is controlled to mask the transmission of the reload signal. Provided is a horizontal synchronizing circuit characterized by outputting a signal.

In the present invention, preferably, the reload mask detecting means includes a counter, and means for supplying a reset signal to the counter when the pulse signal is obtained during a period in which the data killer signal is inactive. A means for supplying the counter as a clock signal when the pulse signal is obtained while the data killer signal is active, and a means for detecting whether or not the output of the counter is 2 or more. When detecting that the output of the counter is 2 or more, a signal for masking the data killer signal is output.

The present invention comprises means for inputting an NTSC composite signal and generating a pulse signal at the time of synchronization detection, data killer mask means for masking transmission of a data killer signal for masking the pulse signal during a data period, and the data killer. A load mask means for masking the pulse signal by using the output of the mask means as a mask control signal, an H counter means for starting a count operation when the load terminal is active, and an output of the H counter means for inputting a data killer signal. Data killer generation means, a reload generation means for inputting the output of the H counter means to generate a reload signal of the H counter, and a horizontal synchronization generation means for inputting the output of the H counter means to output a horizontal synchronization signal. , The mass of the data killer signal relative to the data killer mask means A data killer mask detecting means for supplying a control signal, the output of the load mask means and the output of the reload generating means are connected to a load terminal of the H counter, and the data killer mask detecting means When the pulse signal is obtained while the killer signal is active, the pulse signal is counted, and when the counted value is a predetermined number or more, the data killer signal is masked by the data killer mask means. Provided is a horizontal synchronizing circuit which outputs a signal for controlling the horizontal synchronizing circuit.

In the present invention, preferably, the data killer mask detecting means includes a counter, and means for supplying a reset signal to the counter when the pulse signal is obtained while the data killer signal is inactive. A means for supplying the counter as a clock signal when the pulse signal is obtained while the data killer signal is active, and a means for detecting whether or not the output of the counter is 2 or more. And the output of the counter is 2
When the above is detected, a signal for masking the data killer signal is output.

According to the present invention, free running is also possible, and when the half H phase is erroneously supplied as the load signal of the H counter when the power is turned on, or when the half H phase is applied.
Even if the killer opens the gate at a position where the load signal to the H counter is not applied twice at 1H that is synchronously detected from the vertical sync period or the equivalent pulse period, the compressed data and user data will still be sent to the NTSC. The horizontal sync signal can be output correctly in any case, such as when it is placed during the video data period of the composite signal.

[0026]

BEST MODE FOR CARRYING OUT THE INVENTION Preferred embodiments of the present invention will be described below with reference to the drawings.

Referring to FIG. 1, according to the first embodiment of the present invention, an input NTSC composite signal (1) is input.
On the other hand, means (2) for generating a pulse signal when detecting synchronization
A means (3) for masking the pulse signal with a half H killer signal, an H counter means (5) for turning a pulse signal obtained without masking from the mask means (3) as a load signal, and an H counter (5). Means (6, 7, 8) for generating a half H killer signal, a horizontal synchronizing signal and a reload signal, and for masking the pulse signal when the pulse signal is obtained during the period when the half H killer signal is "L". A means (10) for supplying a reset signal to a counter (12) for deciding whether to mask the half H killer signal and a clock signal for the counter (12) when a pulse signal is obtained during the period when the half H killer signal is "H". Means (11) for supplying power, means (13) for detecting whether the output of the counter (12) is 2 or more, and means (4) for masking the reload signal if the output is 2 or more. Characterized in that it comprises a.

Referring to FIG. 4, in the second embodiment of the present invention, the input NTSC composite signal (1) is used.
On the other hand, means (2) for generating a pulse signal at the time of synchronization detection
A means (3) for masking the pulse signal with a half H killer signal, an H counter means (5) for turning a pulse signal obtained without masking from the mask means (3) as a load signal, and an H counter means (5). ), Each means (6, 7, 8) for generating a half H killer signal, a reload signal, and a horizontal synchronizing signal, and a pulse signal is masked when a pulse signal is obtained during the period when the half H killer signal is “L”. Means (10) for supplying a reset signal to a counter (15) for deciding whether to mask the half H killer signal
And a means (11) for supplying a clock signal to the counter (15) when the pulse signal is obtained during the period when the half H killer signal is "H", and it is detected whether the output of the counter (15) is 2 or more. Means (13) and means (14) for masking a half H killer signal for masking a pulse signal if the number is 2 or more are provided.

Referring to FIG. 6, in the third embodiment of the present invention, the input NTSC composite signal (1) is used.
On the other hand, means (2) for generating a pulse signal at the time of synchronization detection
A means (3) for masking the pulse signal with a data killer signal for masking during the data period, and a mask means (3)
H counter means (5) for rotating a pulse signal obtained without masking as a load signal, and means (16, 7, 8) for generating a data killer signal, a horizontal synchronizing signal, and a reload signal from the H counter means (5). ), A means (17) for supplying a reset signal to a counter (12) for deciding whether to mask the reload signal when a pulse signal is obtained while the data killer signal is "L", and a data killer signal is "H". When the pulse signal is obtained during the period of
Means (18) for supplying a clock signal to 2) and means (1) for detecting whether the output of the counter (12) is 2 or more.
3) and means (4) for masking the reload signal if the number is 2 or more.

Referring to FIG. 8, in the fourth embodiment of the present invention, the input NTSC composite signal (1) is used.
On the other hand, means (2) for generating a pulse signal at the time of synchronization detection
A means (3) for masking the pulse signal with a data killer signal for masking during the data period, and a mask means (3)
H counter means (5) for rotating a pulse signal obtained without masking as a load signal, and means (16, 7, 8) for generating a data killer signal, a horizontal synchronizing signal, and a reload signal from the H counter means (5). ), And a means (17) for supplying a reset signal to a counter (20) for deciding whether to mask the data killer signal when the pulse signal is obtained while the data killer signal is “L”; A means (18) for supplying a clock signal to the counter (20) when a pulse signal is obtained while the killer signal is "H", and a means (13) for detecting whether the output of the counter (20) is 2 or more. If the number is 2 or more, a means (19) for masking the data killer signal for masking the pulse signal is provided.

[0031]

First Embodiment FIG. 1 is a diagram showing the configuration of a horizontal sync detection circuit according to a first embodiment of the present invention.

Referring to FIG. 1, in the NTSC composite signal input 1, a pulse output section 2 at the time of synchronization detection (also referred to as "pulse output section 2") detects that it is a synchronization section.

The pulse signal generated by the pulse output unit 2 upon synchronization detection is supplied to the H counter 5 as a load signal via the load mask unit 3 for masking the load signal.

The output of the H counter 5 is input to the half H killer generation unit 6, the half H killer generation unit 6 outputs a half H killer signal, and the half H killer signal is input to the load mask unit 3 and the load mask unit. 3 indicates that when the half H killer signal is active, the output from the pulse output unit 2 upon synchronization detection is the H counter 5 as a load signal of the half H phase.
Control so that it is not transmitted to the load control terminal of.

The reload generator 8 outputs a reload signal, and the reload signal is supplied as a load signal for the H counter 5 through the reload mask unit 4 for masking the reload signal.

Then, the horizontal synchronization signal output 9 is obtained by the horizontal synchronization generator 7.

The pulse signal of the pulse output unit 2 at the time of synchronization detection is a half H killer “L” period “L” pulse output unit at the time of synchronization detection (also referred to as “reset pulse output unit”) 10,
It is also supplied to the “H” pulse output unit 11 (also referred to as “clock pulse output unit”) during synchronization detection of the half H killer “H” period, and the reset pulse output unit 10 outputs the half H killer signal during the “L” level period. , A reset pulse is output to the reload mask detection counter 12 at the time of synchronization detection, and the clock pulse output unit 11 outputs the half H killer signal as “H”.
During the level period, the pulse signal from the synchronous detection pulse output section 2 is supplied to the reload mask detection counter 12 as a clock pulse.

Then, the reload mask detection counter 12
The output of 1 is masked by the reload mask section 4 from the reload generation section 8 to the H counter 5 when two or more detection sections 13 detect two or more.

The specific operation of this embodiment will be described below. In the following, the operation that is correctly synchronized when the power is turned on will be described with reference to FIG.

The detection of the synchronizing portion of the NTSC composite signal is generally carried out by detecting that the sync slice level or less continues, as shown in the conventional example. Here, it is assumed that synchronization is performed below the 8-clock continuous sync slice level and pulse output of 1 clock is performed.

The pulse output at the time of synchronization detection is passed through the load mask section 3 by the half H killer signal, and then the H counter 5
And the H counter 5 is turned (counting operation).

Since the H counter 5 completes one cycle in 910 cycles, it generates a reload signal by itself and supplies it to the load of the H counter 5 via the reload mask unit 4,
Free-running is possible without the input of a TSC composite signal.

In the vertical synchronization period or the equivalent pulse period, the synchronization is detected in the half H phase, but it is not supplied to the load of the H counter 5 by the half H killer signal.

Further, the synchronization detected by the pulse output unit 2 upon detection of synchronization is such that the reload mask detection counter 12 is set in the cycle of the normal phase when the half H killer signal is in the "L" (= inactive) period. If the half H killer signal is reset and is in the “H” (= active) period, a clock is given to the reload mask detection counter 12 in synchronization with the half H phase.

As a result, the reload mask detection counter 12 within 1H during the vertical synchronization period or the equivalent pulse period.
The counter value of 0 repeats 0 and 1, and is always 0 in other periods.

From now on, the reload mask detection counter 1
Since the count value of 2 does not become 2 or more, the reload signal is not masked, the H counter 5 correctly counts by loading and reloading by the synchronization detection, and the horizontal synchronization generator 7 outputs the horizontal synchronization signal. can do.

Next, regarding the specific operation of this embodiment,
An operation in which the H counter 5 starts the counting operation in synchronization with the half H phase when the power is turned on, and then corrects synchronization again will be described with reference to FIG.

In the vertical synchronization period or the equivalent pulse period, the pulse for synchronization detection is generated twice during 1H, but half H
When the H counter 5 is operated by using the pulse generated by the phase synchronization as the load signal, the pulse generated by the normal phase synchronization is masked by the half H killer signal, and the H counter 5 is activated in 910 cycles. Is equipped with a reload generator 8 for controlling the circuit to go around once, the H counter 5 remains forever shifted in phase by half H.
Turns around.

Therefore, in the present embodiment, correction is made from the phase relationship between the pulse generated at the time of synchronization detection and the half H killer.

After 10H, the pulse generated at the time of synchronization detection should originally be output during the period when the half H killer signal is "L" as shown in FIG. At that time, the reload mask detection counter 12 is always reset.

However, in the state in which the phase is shifted by half H, as shown in FIG. 3, the pulse generated at the time of synchronization detection after 10H is output during the period when the half H killer signal is "H", and the reload mask is used. The detection counter 12 is supplied with a clock and starts counting up.

Therefore, normally, the count value of the reload mask detection counter 12 cannot be detected other than 0 and 1, while the count output of the reload mask detection counter 12 is detected to be 2 or more. Become.

When this happens, it is apparent that the synchronization is wrong, and the 2 or more detection section 13 outputs a signal for masking the reloading of the H counter 5 to the reload masking section 4.

Then, the H counter 5 counts up to 910 or more.

Naturally, the half H killer signal is not output with such a value (count value of 910 or more), and the pulse generated by the pulse output unit 2 at the next synchronization detection is the load signal of the H counter 5. Supplied as.

As a result, the normal phase can be synchronously pulled in, and thereafter, the H counter 5 can properly perform the counting operation and output the horizontal synchronizing signal synchronized with the input.

[0057]

Second Embodiment FIG. 4 shows a horizontal sync detection circuit according to a second embodiment of the present invention.

Referring to FIG. 4, in the NTSC composite signal input 1, the pulse output section 2 at the time of synchronization detection detects that it is the synchronization section. The pulse generated by the pulse output unit 2 at the time of synchronization detection is supplied to the H counter 5 as a load signal through the load mask unit 3 that masks the load signal.

The output of the H counter 5 is input to the half H killer generation unit 6, the half H killer generation unit 6 outputs a half H killer signal, and the half H killer signal is loaded via the half H killer mask unit 14. The half H-phase load signal that is input as a mask control signal to the mask unit 3 and that is input to the load of the H counter 5 is masked.

Further, the reload generator 8 outputs a reload signal from the output of the H counter 5 and is supplied as a load signal of the H counter 5.

Then, the horizontal synchronization signal output 9 is obtained by the horizontal synchronization generator 7.

The pulse of the pulse output unit 2 at the time of synchronization detection is a half H killer “L” period. The pulse output unit at the time of synchronization detection “L” (also called “reset pulse output unit”) 10 and the half H killer “H” period. "H" pulse output section 11 when synchronization is detected
(Also called "clock pulse output section"),
The reset pulse output unit 10 outputs a reset pulse to the half H killer mask detection counter 15 during synchronization detection while the half H killer signal is "L", and the clock pulse output unit 11 outputs the half H killer signal "H". In the period "", the pulse output at the time of synchronization detection is supplied to the half H killer mask detection counter 15 as a clock pulse.

Next, a specific operation of this embodiment will be described below. FIG. 5 shows an operation in which the H counter 5 starts the counting operation in synchronization with the half H phase when the power is turned on, and then resynchronizes correctly.

Referring to FIG. 5, this embodiment basically performs the same operation as that of the first embodiment, but is different from the first embodiment in that a synchronization error is made. This is a correction method.

That is, in the first embodiment, the reload signal is masked and the pulse generated by the pulse output unit 2 upon synchronization detection is waited for. However, in the present embodiment, the half H killer signal for masking the load signal is used. It is configured to mask itself.

Referring to FIG. 5, in the state where the phase is shifted by half H, the pulse generated at the time of synchronization detection after 10H is output during the period when the half H killer signal is "H", and the half H killer mask is generated. The detection counter 15 is supplied with a clock and starts a count-up operation.
Although detection other than 0 and 1 is not possible, a value of 2 or more is detected in the count output of the half H killer mask detection counter 15, and the 2 or more detection unit 13 outputs a mask signal to the half H killer mask unit 14. However, for example, at 11H, the half H killer signal is masked (not output to the load mask unit 3). Therefore, thereafter, the H counter 5 correctly counts the pulse output at the time of synchronization detection as a load signal and synchronizes with the input. The horizontal synchronizing signal can be output.

According to this embodiment, the H counter 5 has 91
Only when counting up to 0, there is no need to consider (circuit configuration) when counting up more, and the horizontal synchronizing signal synchronized with the input can be output as in the first embodiment.

[0068]

Third Embodiment FIG. 6 shows the configuration of a horizontal sync detection circuit according to a third embodiment of the present invention.

Referring to FIG. 6, in the NTSC composite signal input 1, the pulse output section 2 at the time of synchronization detection detects that it is the synchronization section. The pulse generated by the pulse output unit 2 upon synchronization detection is supplied as a load signal for the H counter 5 through the load mask unit 3 that masks the load signal.

The output of the H counter 5 is input to the data killer generator 16 for masking the data period, and the data killer generator 16 outputs the data killer signal. The data killer signal is masked to the load mask unit 3. , And the load signal in the data phase input to the load of the H counter 5 is masked.

Further, the reload signal is output from the reload generation section 8 which receives the output of the H counter 5 and is supplied as the load signal of the H counter 5 through the reload mask section 4 which masks the reload signal.

Then, the horizontal synchronizing signal output 9 is obtained by the horizontal synchronizing generator 7.

The pulse of the pulse output section 2 at the time of synchronization detection is the "L" pulse output section 1 at the time of synchronization detection in the data killer "L" period.
7 is also supplied to the data killer “H” period synchronous detection “H” pulse output unit 18, and if the data killer is the “L” period, the reload mask detection counter 12 is reset pulse and the data killer is “H”. In the period of, the reload mask detection counter 12 is supplied as a clock pulse.

Then, the reload mask detection counter 12
When 2 or more are detected by the detection section 13, the reload mask section 4 masks the reload signal to the H counter 5 output from the reload generation section 8.

Next, a specific operation of this embodiment will be described below.

Referring to FIG. 7, for the example in which not the NTSC color data but arbitrary data, particularly all "L" are superposed on the data phase, synchronous detection is performed from the data phase at power-on. In the case where the H counter 5 starts to rotate due to this, the operation of resynchronizing correctly will be described.

The fact that arbitrary data is superimposed during the data period corresponds to the presence of a pattern that is detected as being synchronized even during the data period, and it is necessary to prevent it from being mistakenly determined to be synchronous from these patterns. .

Therefore, in the first embodiment, the half H
The control using the half H killer signal for masking only the phase has been acceptable, but in the present embodiment, a data killer signal for masking the entire data period is required.

In FIG. 7, it is determined that the synchronization is in the data period, and the normal synchronization is continuously masked. However, when the equivalent pulse region is entered, the reload signal is masked as in the first embodiment. Can be synchronized to the input.

In the present embodiment, the phase is shifted by half H and is synchronized. However, this is exactly the same as the situation shown in the first embodiment, and thereafter, the horizontal synchronization signal synchronized with the input can be output by the same operation as in the first embodiment. As shown in FIG. 7, in 1H after the video data period, the pulse generated during the synchronization detection is output during the period when the data killer signal is “H”,
A clock is supplied to the reload mask detection counter 12 to start a count-up operation, and the count value is 0,
Although a value other than 1 is not possible, a value of 2 or more is detected, and the 2 or more detection unit 13 outputs a signal for masking the reload signal output from the reload generation unit 8 to the reload mask unit 4. To do.

[0081]

Fourth Embodiment FIG. 8 shows the configuration of a horizontal sync detection circuit according to a fourth embodiment of the present invention.

Referring to FIG. 8, in the NTSC composite signal input 1, the pulse output unit 2 upon synchronization detection detects that it is a synchronization unit. The pulse generated by the pulse output unit 2 upon synchronization detection is supplied as a load signal for the H counter 5 through the load mask unit 3 that masks the load signal.

The output of the H counter 5 outputs a data killer in the data killer generator 16 which masks the data period, and the load mask unit 3 masks the load signal in the data phase input to the load of the H counter 5. To do.

The reload generator 8 outputs a reload signal, which is supplied as a load signal for the H counter 5.

Then, the horizontal synchronization signal output 9 is obtained by the horizontal synchronization generator 7.

The pulse of the pulse output section 2 at the time of synchronization detection is the "L" pulse output section 1 at the time of synchronization detection in the data killer "L" period.
7 and the data killer “H” period synchronous detection “H” pulse output section 18, and when the data killer is the “L” period, the data killer mask detection counter 20 outputs a reset pulse to the data killer “H”. In the "period, it is supplied to the data killer mask detection counter 20 as a clock pulse.

The output of the data killer mask detection counter 20 masks the data killer in the data killer mask 19 when the two or more detection sections 13 detect two or more, and the pulse of the synchronous detection pulse output section 2 is It is not masked by the load mask unit 3 and supplied to the load of the H counter 5.

Next, the specific operation of this embodiment will be described.

Referring to FIG. 9, synchronization detection is performed from the data phase when the power is turned on for an example in which not the NTSC color data but arbitrary data, particularly all “L”, is superposed on the data phase. Then, the H counter starts to rotate, and then the operation of resynchronizing correctly will be described.

As shown in FIG. 9, this embodiment basically operates in the same manner as the third embodiment, but the difference from the third embodiment is that the synchronization is wrong. This is a correction method.

That is, in the third embodiment, the reload signal is masked and the pulse generated by the synchronization detection is waited for. However, in the present embodiment, the data killer itself that masks the load signal is masked. is there.

In the present embodiment, the H counter 5 counts only up to 910, and it is not necessary to consider when the counter is more than 910, and the horizontal synchronizing signal synchronized with the input is output as in the third embodiment. can do.

Although the present invention has been described above with reference to the above-described embodiments, the present invention is not limited to the above-mentioned aspects, and it goes without saying that it includes various aspects according to the principle of the present invention.

[0094]

As described above, according to the present invention,
Free run is also possible, and if half H phase synchronization is mistakenly supplied as the load signal of the H counter at power-up, or half H killer is synchronously detected from the vertical synchronization period or equivalent pulse period. In any case, such as when the gate is opened at a position where the load signal to the H counter is not applied, the compressed data, user data, etc. can be placed during the video data period of the NTSC composite signal. However, there is an effect that the horizontal synchronizing signal can be correctly output. In particular, according to the present invention, even when data of any combination is inserted during the data period, it has an advantage that a correct horizontal synchronizing signal can be output by pulling in the synchronizing signal of a normal phase.

[Brief description of drawings]

FIG. 1 is a block diagram illustrating a configuration of a first exemplary embodiment of the present invention.

FIG. 2 is a first timing chart for explaining the operation of the first embodiment of the present invention.

FIG. 3 is a second timing chart for explaining the operation of the first embodiment of the present invention.

FIG. 4 is a block diagram illustrating a configuration of a second exemplary embodiment of the present invention.

FIG. 5 is a timing chart for explaining the operation of the second exemplary embodiment of the present invention.

FIG. 6 is a block diagram showing a configuration of a third exemplary embodiment of the present invention.

FIG. 7 is a timing diagram for explaining the operation of the third embodiment of the present invention.

FIG. 8 is a block diagram showing a configuration of a fourth exemplary embodiment of the present invention.

FIG. 9 is a timing chart for explaining the operation of the fourth embodiment of the present invention.

FIG. 10 is a block diagram showing a configuration of a conventional horizontal synchronizing circuit.

FIG. 11 is a block diagram showing another configuration of a conventional horizontal synchronizing circuit.

[Explanation of symbols]

1 NTSC composite signal input unit 2 Sync detection pulse output unit 3 Load mask unit 4 Reload mask unit 5 H counter unit 6 Half H killer generation unit 7 Horizontal synchronization generation unit 8 Reload generation unit 9 Horizontal synchronization signal output unit 10 Half H killer "L" period sync detection "L" pulse output section 11 Half H Killer "H" period sync detection "H" pulse output section 12 Reload mask detection counter section 13 2 or higher detection section 14 Half H Killer mask section 15 Half H Killer mask detection counter section 16 Data killer generation section 17 Data killer “L” pulse output section during “L” period synchronization detection 18 Data killer “H” period synchronization detection “H” pulse output section 19 Data killer mask section 20 Data killer Mask detection counter section

Claims (8)

[Claims] 1. A means for inputting an NTSC composite signal to generate a pulse signal at the time of synchronization detection, a load mask means for inputting the pulse signal and masking the pulse signal using a half H killer signal as a mask control signal, and a load. H counter means for starting the counting operation when the terminal is active, half H killer generation means for inputting the output of the H counter means and generating the half H killer signal, and H counter means for inputting the output of the H counter means Reload generating means for generating a reload signal of the counter; horizontal synchronization generating means for receiving the output of the H counter means and outputting a horizontal synchronizing signal; and reload mask means for masking transmission of the reload signal to the H counter. Supplying a mask control signal of the reload signal to the reload mask means A reload mask detecting means, wherein an output of the load mask means and an output of the reload mask means are connected to a load terminal of the H counter, and the reload mask detecting means is in a period during which the half H killer signal is active. When the pulse signal is output to, the pulse signal is counted, and when the count value is a predetermined number or more, a signal for controlling the reload mask means to mask the reload signal is output. Horizontal synchronization circuit characterized by. 2. The reload mask detection means, a counter, a means for supplying a reset signal to the counter when the pulse signal is obtained during a period when the half H killer signal is inactive, and the half H killer. A counter for supplying a clock signal to the counter when the pulse signal is obtained while the signal is active; and a means for detecting whether or not the output of the counter is 2 or more. 2. The horizontal sync detection circuit according to claim 1, wherein a signal for masking the reload signal is output when it is detected that the output is two or more. 3. A means for inputting an NTSC composite signal to generate a pulse signal at the time of synchronization detection, a half H killer mask means for masking transmission of a half H killer signal, and a half H killer mask for receiving the pulse signal. A load mask means for masking the pulse signal using the output of the means as a mask control signal, an H counter means for starting a counting operation when the load terminal is active, and an output of the H counter means for inputting a half H killer signal. Half H killer generation means, a reload generation means for inputting the output of the H counter means to generate a reload signal of the H counter, and a horizontal synchronization generation means for inputting the output of the H counter means and outputting a horizontal synchronization signal. And mask control of the half H killer signal to the half H killer mask means. Half H killer mask detecting means for supplying a signal, the output of the load mask means and the output of the reload generating means are connected to the load terminal of the H counter, and the half H killer mask detecting means is When the pulse signal is obtained while the half H killer signal is active, the pulse signal is counted, and when the counted value is a predetermined number or more, the half H killer signal is sent to the half H killer mask means. A horizontal synchronizing circuit, which outputs a signal for controlling so as to mask. 4. The half H killer mask detection means includes: a counter; a means for supplying a reset signal to the counter when the pulse signal is obtained during a period when the half H killer signal is inactive; A means for supplying a clock signal to the counter when the pulse signal is obtained while the H killer signal is active, and a means for detecting whether or not the output of the counter is 2 or more, The horizontal synchronization detection circuit according to claim 3, wherein a signal for masking the half H killer signal is output when it is detected that the output of the counter is 2 or more. 5. A means for inputting an NTSC composite signal to generate a pulse signal at the time of synchronization detection, and a load mask means for masking the pulse signal using a data killer signal for masking the pulse signal during a data period as a mask control signal. H counter means for starting the counting operation when the load terminal is active, data killer generation means for inputting the output of the H counter means and generating the data killer signal, and H counter for receiving the output of the H counter means Reload generating means for generating the reload signal, horizontal synchronization generating means for receiving the output of the H counter means and outputting a horizontal synchronizing signal, and reload mask means for masking transmission of the reload signal to the H counter. A mask control signal of the reload signal is supplied to the reload mask means. And a reload mask detecting means for supplying the output of the load mask means and an output of the reload mask means to a load terminal of the H counter, wherein the reload mask detecting means activates the data killer signal. When the pulse signal is obtained during the period, the pulse signal is counted, and when the count value is a predetermined number or more, a signal for controlling the reload mask means to mask transmission of the reload signal is supplied. A horizontal synchronizing circuit characterized by outputting. 6. The reload mask detection means includes a counter, means for supplying a reset signal to the counter when the pulse signal is obtained during a period when the data killer signal is inactive, and the data killer signal The counter output includes means for supplying the counter as a clock signal when the pulse signal is obtained during the active period, and means for detecting whether or not the output of the counter is 2 or more. 6. The horizontal synchronization detecting circuit according to claim 5, wherein a signal for masking the data killer signal is output when it is detected that the value is 2 or more. 7. A means for inputting an NTSC composite signal to generate a pulse signal at the time of synchronization detection, a data killer mask means for masking transmission of a data killer signal for masking the pulse signal during a data period, and the data killer mask means. Load mask means for masking the pulse signal by using the output of the above as a mask control signal, H counter means for starting the count operation when the load terminal is active, and data for inputting the output of the H counter means to generate a data killer signal. A killer generation means, a reload generation means for inputting an output of the H counter means to generate a reload signal of the H counter, a horizontal synchronization generation means for inputting an output of the H counter means and outputting a horizontal synchronization signal, Mask control of the data killer signal for the data killer mask means Data killer mask detection means for supplying a signal, the output of the load mask means and the output of the reload generation means are connected to a load terminal of the H counter, and the data killer mask detection means When the pulse signal is obtained while the signal is active, the pulse signal is counted, and when the count value is a predetermined number or more, the data killer signal is masked by the data killer mask means. A horizontal synchronization circuit characterized by outputting a control signal. 8. The data killer mask detection means, a counter, a means for supplying a reset signal to the counter when the pulse signal is obtained during the inactive period of the data killer signal, and the data killer signal. When the pulse signal is obtained during the active period, means for supplying the counter as a clock signal, and means for detecting whether or not the output of the counter is 2 or more, 8. The horizontal sync detection circuit according to claim 7, wherein a signal for masking the data killer signal is output when it is detected that the output is two or more.