JP3321509B2 - Frame pulse generation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame pulse generating circuit, and more particularly to a frame pulse generating circuit for generating a frame pulse synchronized with an externally supplied reference clock.

[0002]

2. Description of the Related Art FIG. 10 is a diagram showing an example of a clock supply system to which the present invention is applied, and FIG. 11 is a diagram showing an example of a conventional frame pulse generation circuit.

In FIG. 10, a reference clock source (1)
Supplies a reference clock signal (CF _S ) to a plurality of clock supply devices (4) each including a frame pulse generation circuit (2) and a clock signal generation circuit (3).

[0004] A reference clock signal (CF _S ) is obtained by adding a bipolar clock signal having a predetermined speed (for example, 64 kilobits per second) to a fixed period (for example, 8 clock periods).
A frame pulse having a predetermined speed (for example, 8 kilobits per second) is superimposed by performing a violation in a bipolar format every time.

In each clock supply device (4), a frame pulse generation circuit (2) and a clock signal generation circuit (3) are separated from a reference clock signal (CF _S ) supplied from a reference clock source (1). Separating the frame pulse (F _A ) and the separated clock signal (C _A ),
An output frame pulse (F _O ) synchronized with the separation frame pulse (F _A ) and an output clock signal (C _O ) synchronized with the separation clock signal (C _A ) are generated. ).

Conventional frame pulse generation circuit (2)
Is, as shown in FIG. 11, a signal conversion unit (21) and F
It comprises a P extraction unit (22) and an FP generation counter (23). [However, the signal conversion unit (21) is shared with the clock signal generation circuit (3). The signal converter (21) receives the reference clock signal (CF _S ) supplied from the reference clock source (1), converts the signal from the bipolar signal format (BP) to the unipolar signal format (UP), and then extracts the FP. (22).

An FP extracting section (22) extracts a separated frame pulse (F _A ) from the reference clock signal (CF _S ),
This is transmitted to the FP generation counter (23). The FP generation counter (23) repeatedly counts the output clock signal (C _O ) generated by the clock signal generation circuit (3) by a predetermined number of clocks, and outputs an output frame pulse (F _O ) every cycle.
The output phase of the output frame pulse (F _O ) is synchronized with the separated frame pulse (F _A ) transmitted from the FP extraction unit (22).

If the separated frame pulse (F _A ) is interrupted for some reason, the FP generation counter (23) counts the separated clock signal (C _A ) and autonomously outputs the output frame pulse (F _O ). I do.

In such a clock supply system, when a signal line connecting the reference clock source (1) and the clock supply device (4) is attached or detached while supplying the reference clock signal (CF _S ), If transient noise is induced from the outside of the line, the reference clock signal (CF _S ) in bipolar signal format (BP) may be disturbed, and the separated frame pulse (F _A ) may also be disturbed.

Such a disturbance disappears after the signal line is securely connected or after the transient induction noise source disappears, and the supply of the normal reference clock signal (CF _S ) is resumed. Until the reference clock signal (CF _S ) is normalized, the separated frame pulse (F _A ) extracted by the FP extraction unit (22) also suffers from a disturbance, and accordingly, the FP generation counter (23) receives each received signal. The output frame pulse (F _O ) supplied to the device (5) is also affected by the disturbed separated frame pulse (F _O ).
_A ) will be phase-synchronized, which will have a significant effect on the operation of each supplied device (5).

[0011]

As is apparent from the above description, in the conventional frame pulse generation circuit,
Separated frame pulse (F _A ) extracted from the reference clock signal (CF _S ) supplied from the reference clock source (1)
Since the output frame pulse (F _O ) is phase-synchronized with the reference clock signal (CF _S ), when the reference clock signal (CF _S ) is disturbed,
The output frame pulse (F _O ) also suffers from the same disturbance, and has a problem of seriously affecting the operation of each of the supplied devices (5).

An object of the present invention is to make it possible to supply a normal output frame pulse as much as possible even when a frame pulse supplied from the outside is disturbed.

[0013]

FIGS. 1 (a) and 1 (b) show the principle of the present invention. FIG. 1 (a) is a diagram showing the principle of the present invention, FIG. 1 (b) is a diagram showing the claims 2 and 3, and FIG. ) Shows the principle of claim 4, and FIG. 4 (d) shows the principle of claim 5.

In FIG. 1, reference numeral 100 denotes a frame pulse generating means for maintaining synchronization provided according to the present invention (claim 1). Reference numeral 200 denotes an output frame pulse generator provided according to the present invention (claims 1 to 5).

Reference numeral 300 denotes comparison means provided according to the present invention (claims 1 to 5). Reference numeral 400 denotes a synchronization switching unit provided according to the present invention (claim 1). 500
Is a counting means provided according to the present invention (claims 2 to 4).

Reference numeral 601 denotes a first synchronization means provided according to the present invention (claims 2 and 3). 602 is a second synchronization means provided according to the present invention (claims 4 and 5).

Reference numeral 700 denotes a time limit means provided according to the present invention (claim 5).

[0018]

Function: frame pulse generating means for maintaining synchronization (100)
Generates a frame pulse for maintaining synchronization with a predetermined period synchronized with the input external frame pulse, and when the external frame pulse being input is interrupted, the synchronization is maintained for a predetermined period while maintaining the phase immediately before the interruption. Frame pulses are continuously generated.

Output frame pulse generating means (200)
Generates an output frame pulse of a predetermined cycle synchronized with the input external frame pulse, and when the external frame pulse being input is interrupted, outputs the output frame pulse of the predetermined cycle while maintaining the phase immediately before the interruption. Generate continuously.

In the present invention (claim 1), the comparing means (300) compares the phase of the external frame pulse with reference to the synchronizing frame pulse generated by the synchronizing frame pulse generating means (100). Further, in the present invention (claims 2 to 5), the phases of the external frame pulses are compared with reference to the output frame pulse generated by the output frame pulse generating means (200).

The synchronization switching means (400) is provided with a comparing means (3).
00) detects that an external frame pulse having the same phase as the frame pulse for synchronizing has not been input, the frame for synchronizing without inputting the external frame pulse to the output frame pulse generating means (200). The pulse signal is input to the pulse generation means (100), and is compared to the comparison means (3
00) detects that an external frame pulse having the same phase as the synchronization maintaining frame pulse has been input,
The external frame pulse is input to the output frame pulse generating means (200) without being input to the synchronization maintaining frame pulse generating means (100).

The counting means (500) is provided with a comparing means (30).
0) is counted the number of times continuously detecting that no external frame pulse having the same phase as the output frame pulse was input.

The first synchronizing means (601) inputs an external frame pulse to the output frame pulse generating means (200) when the count value of the counting means (500) reaches a predetermined number. When the count value of the counting means (500) falls below a predetermined number, the input of the external frame pulse to the output frame pulse generating means (200) is stopped.

The first synchronizing means (601) inputs the external frame pulse to the output frame pulse generating means (200) at the time when the output frame pulse generating means (200) starts operating, and performs counting. When the count value of the means (500) falls below a predetermined number, stopping input of the external frame pulse to the output frame pulse generating means (200) is considered.

In the present invention (claim 4), the second synchronizing means (602) detects that the external frame pulse having the same phase as the output frame pulse was not inputted by the comparing means (300). In this case, the input of the external frame pulse to the output frame pulse generation means (200) is stopped, and when the count value of the counting means (500) reaches a predetermined number, the external frame pulse is output. It is input to the frame pulse generating means (200).

The time limit means (700) includes a comparing means (30).
0) starts when it detects that an external frame pulse having the same phase as the output frame pulse has not been input, and starts and stops after a lapse of a predetermined time.

In the present invention (claim 5), the second synchronizing means (602) is connected to the external frame pulse output frame pulse generating means (200) when the time limit means (700) is activated. Is stopped and the time limit means (7
00), the external frame pulse is input to the output frame pulse generating means (200).

Therefore, according to the present invention (claim 1), when the external frame pulse is disturbed, the input of the external frame pulse is immediately stopped from the output frame pulse generating means for generating the output frame pulse, and the output is stopped. After the recovery of the stability of the external frame pulse is confirmed by the synchronization maintaining frame pulse generating means provided separately from the frame pulse generating means for output, the frame pulse is output to the output frame pulse generating means. Can always generate an output frame pulse synchronized with a stable external frame pulse.

Further, according to the present invention (claims 2 and 3), the output frame pulse generating means autonomously generates the output frame pulse without receiving the external frame pulse, and outputs the external frame pulse to the external frame pulse. The phase change of the external frame pulse is monitored by comparing with the frame pulse, and when a predetermined number of consecutive phase changes are detected, it is determined that a steady phase change has occurred in the external frame pulse, and the output frame pulse is determined. Since the phase of the output frame pulse is input to the generating means and the phase of the output frame pulse is synchronized, it is possible to prevent the phase of the output frame pulse from being synchronized with the disturbed external frame pulse.

According to the present invention (claims 4 and 5), the external frame pulse is compared with the output frame pulse generated by the output frame pulse generating means to which the external frame pulse is input. The input of the external frame pulse to the output frame pulse generating means is stopped immediately when the phase change is detected, and after the phase change of the external frame pulse is determined to be stationary, Since the phase of the output frame pulse is inputted to the frame pulse generating means and the phase of the output frame pulse is synchronized with the new external frame pulse, it is possible to prevent the phase of the output frame pulse from being synchronized with the disturbed external frame pulse.

[0031]

An embodiment of the present invention will be described below with reference to the drawings. 2 is a diagram showing a frame pulse generation circuit according to an embodiment of the present invention (claim 1), FIG. 3 is a diagram showing an example of a signal waveform in FIG. 2, and FIG. 3 is a diagram showing a frame pulse generating circuit according to an embodiment of the present invention, FIG. 5 is a diagram showing an example of a signal waveform in FIG. 4, and FIG. 6 is a diagram showing a frame according to an embodiment of the present invention (claim 4). 7 is a diagram illustrating a pulse generation circuit, FIG. 7 is a diagram illustrating an example of a signal waveform in FIG. 6, and FIG. 8 is a diagram illustrating a frame pulse generation circuit according to an embodiment of the present invention (claim 5); FIG. 9 is a diagram showing an example of the signal waveform in FIG. The same reference numerals indicate the same objects throughout the drawings. The target clock supply system is as shown in FIG.

First, an embodiment of the present invention (claim 1) will be described with reference to FIGS. In FIG. 2, FIG.
The frame pulse generating means (10) for maintaining synchronization in (a).
1), a pseudo-synchronous counter (26) and a decoder (27) are provided, and an FP generation counter (23) is provided as an output frame pulse generating means (200) in FIG. 1 (a). 1), a comparing section (24) is provided as the comparing means (300).
The switching unit (2) as the synchronization switching unit (400) in (a)
5) is provided.

Referring to FIGS. 2 and 3, the signal converter (2
1) and the FP extraction unit (22) are provided from the reference clock signal (CF _S ) supplied from the reference clock source (1) (see FIG. 10) as in the conventional frame pulse generation circuit (see FIG. 11). The separation frame pulse (F _A ) is extracted and transmitted to the comparison unit (24) and the switching unit (25).

The switching unit (25) is controlled by a coincidence detection signal (e) transmitted from the comparison unit (24) (the coincidence detection signal (e) will be described later), and an input terminal (25).
-1) is switched and connected to one of the output terminals (25-2) and (25-3), and the separated frame pulse (F) inputted from the FP extraction unit (22) to the input terminal (25-1) is connected.
_A ) is output to one of the connected output terminals (25-2) and (25-3), and is input to the FP generation counter (23) or the pseudo synchronization counter (26).

The FP generation counter (23) is a
Same as in the frame pulse generation circuit (see FIG. 11)
Then, the clock signal generation circuit (3) (see FIG. 10) generates
Output clock signal (C_O) Is repeated a predetermined number of clocks
Count and output the output every period (for example, 8 kilobits per second).
Lame pulse (F_O) Is output, but the switching unit (25)
Frame pulse (F_A) Is entered
Is the output frame pulse (F_O) Output phase
Pulse (F_A), But the switching unit (25)
Frame pulse (F_A) Is not entered
Is the separated frame pulse input immediately before switching.
(F_A), The output frame pulse (F _O)
Maintain and autonomously output frame pulses (F_O) Is output
You.

As with the FP generation counter (23), the pseudo-synchronous counter (26) also has a clock signal generation circuit (3).
The output clock signal (C _O ) generated by [see FIG. 10] is repeatedly counted by a predetermined number of clocks, and a frame pulse (F _C ) for maintaining synchronization is obtained every one cycle (for example, 8 kilobits per second).
The signal is output via a decoder (27).
When the separation frame pulse (F _A ) is input from the switching section (25), the output phase of the synchronization maintaining frame pulse (F _C ) is synchronized with the separation frame pulse (F _A ). When the pulse (F _A ) is not input, the synchronization maintaining frame pulse (F _C ), which is phase-synchronized with the separated frame pulse (F _A ) input immediately before switching, is maintained, and the synchronization is maintained autonomously. outputs frame pulses (F _C).

The output synchronization holding frame pulse from the pseudo-synchronization counter (26) (F _C) comprises a decoder (2
The information is transmitted to the comparison unit (24) via 7). Comparison section (2
4) is a decoder (2) from the pseudo-synchronous counter (26).
7) transmitted through the frame pulse (F)
And phase _C), compares the phase of the FP extractor (22) separating frame pulse transmitted from (F _A), synchronization holding frame pulse (F _C) and phase matched separated frame pulses (F _A ) Is not transmitted, the coincidence detection signal (e) to be output is set to a non-coincidence state (for example, e = logic "0"), and the frame pulse (F
_When the separated frame pulse (F _A ) whose phase matches that of _C ) is transmitted, the match detection signal (e) to be output is set to a match state (for example, e = logic “1”), and the switching unit (25)
To communicate.

When the coincidence detection signal (e) transmitted from the comparison unit (24) is set to the coincidence state (= "1"), the switching unit (25) inputs the input terminal (25-1). connected to the output terminal (25-2), but enter separate frame pulses transmitted from the FP extractor (22) to (F _a) to the FP generation counter (23), is transmitted from the comparator (24) When the coincidence detection signal (e) is set to a non-coincidence state (= "0"), the input terminal (25-1) is connected to the output terminal (2).
Switch connected to 5-3), and inputs the separation frame pulses transmitted from the FP extractor (22) to (F _A) to the pseudo-synchronous counter (26).

Immediately after the start of the start of the frame pulse generation circuit (2) [time (t ₁ )], the pseudo-synchronous counter (26) generates and transmits it to the comparison unit (24) via the decoder (27). synchronization holding frame pulse (F _C)
And the separated frame pulse (F _A ) transmitted from the FP extraction unit (22) to the comparison unit (24), the phases are normally inconsistent, and the comparison unit (24) outputs a coincidence detection signal set to a non-coincidence state. (E = “0”) is output and transmitted to the switching unit (25).

As a result, the switching unit (25) inputs the separated frame pulse (F _A ) transmitted from the FP extraction unit (22) to the pseudo synchronization counter (26), and the pseudo synchronization counter (26) generates. The phase of the synchronization maintaining frame pulse (F _C ) is synchronized with the separation frame pulse (F _A ).

When the synchronizing frame pulse (F _C ) is phase-synchronized with the separation frame pulse (F _A ), the comparing section (2)
4) detects that the separated frame pulse (F _A ) having the same phase as that of the synchronization maintaining frame pulse (F _C ) is transmitted, and the coincidence detection signal (e =
"1") is transmitted to the switching unit (25).

As a result, the switching unit (25) switches and inputs the separated frame pulse (F _A ) transmitted from the FP extraction unit (22) to the FP generation counter (23), and the FP generation counter (23) The phase of the output frame pulse (F _O ) to be synchronized is synchronized with the separation frame pulse (F _A ) (time (t ₂ )).

On the other hand, the pseudo-synchronous counter (26)
(25) is the separation frame pulse (F _A) Generate FP Cow
After switching and inputting to the switch (23),
Separated frame pulse (F_A)
Frame pulse (F _CMaintain) and autonomously
Frame pulse (F_C) Generate and decoder
The signal is transmitted to the comparison unit (24) via (27).

The separation frame pulse (F_A) Phase is constant
If the switching time (t₁)
Pulse (F_A) Is the frame pulse for maintaining synchronization
(F_C) Should be in phase synchronization with the comparator (24).
The match detection signal (e) continues to be in the match state [= logic
"1"] and the switching unit (25) also
Pulse (F _A) Is continuously input to the FP generation counter (23).
I can.

In this state, when the reference clock signal (CF _S ) is disturbed at the time (t ₃ ) and the separation frame pulse (F _A ) is also disturbed, the comparing section (24) sets the synchronization-maintaining frame pulse. It detects that the separated frame pulse (F _A ) in phase with (F _C ) has not been transmitted, and sets the coincidence detection signal (e) to be output to a non-coincidence state [= logic “0”].

When the switching unit (25) detects that the coincidence detection signal (e) transmitted from the comparison unit (24) has been set to a non-coincidence state [= logic "0"], the FP generation counter ( The separated frame pulse (F _A ) input to (23) is switched and input to the pseudo-synchronous counter (26).

[0047] FP generation counter (23), even after no longer enter the separation frame pulse (F _A), the phase of the output frame pulses synchronized with the phase of the immediately preceding separation frame pulse (F _A) (F _O) Maintain and autonomously generate and output an output frame pulse (F _O ).

On the other hand, the pseudo-synchronous counter (26) synchronizes the phase of the synchronizing frame pulse (F _C ) that is being generated autonomously with the separated frame pulse (F _A ) that has begun to be input. While the frame pulse (F _C ) continues to be generated at a predetermined cycle, the separated frame pulse (F _C )
_{Since A} ) is temporarily disturbed, the comparison unit (24) cannot detect that the separated frame pulse (F _A ) having the same phase as the synchronization maintaining frame pulse (F _C ) has been transmitted. The output of the coincidence detection signal (e) is kept in a non-coincidence state [= logic “0”].

In the meantime, the FP generation counter (23) maintains the phase of the output frame pulse (F _O ) synchronized with the phase of the separation frame pulse (F _A ) immediately before the cutoff, and autonomously outputs the output frame pulse (F _O). ) Is generated and output.

In a state where the disturbance that the separation frame pulse (F _A ) transiently suffers at time (t ₄ ) disappears and the separation frame pulse (F _A ) becomes only a steady frame pulse, the pseudo the synchronous counter (26) is phase locked to the separate frame pulse (F _a), comparator unit (24) is the synchronization holding frame pulse (F _C) and phase matched separated frame pulses (F _a) is transmitted Can be detected and the coincidence detection signal (e) is set to the coincidence state [= logic “1”]. Therefore, the switching unit (25) outputs the separated frame pulse (F _A ) input to the pseudo-synchronous counter (26). the inputs switched to FP generation counter (23) [time (t _5)].

The FP generation counter (23) synchronizes the phase of the output frame pulse (F _O ) which has been autonomously generated until now with the stationary separation frame pulse (F _A ) which has begun to be input.

As is apparent from the above description, according to the embodiment of the present invention [claim 1], the comparison section (24) generates the stationary synchronization holding frame pulse (F) generated by the pseudo synchronization counter (26). based on the _C), monitoring the phase of the separation frame pulse (F _a), while the synchronization hold frame pulse (F _C) and phase matched steady separation frame pulse (F _a) is detected , The separation frame pulse (F _A ) is input to the FP generation counter (23), but immediately after the separation frame pulse (F _A ) whose phase does not coincide with the synchronization maintaining frame pulse (F _C ) is detected. FP generation counter for separated frame pulse (F _A ) (2
3) The input to the FP is stopped, the FP generation counter (23) autonomously continuously generates a steady output frame pulse (F _O ), and the separation frame pulse (F _A ) is a pseudo-synchronous counter (26). the switching input, the synchronization holding frame pulse (F _C) is phase locked to the separate frame pulse (F _a) the notwithstanding et al, monitors the separated frame pulse (F _a), separating the frame pulse (F _a) is stabilized Wait, FP again
An output frame pulse (F _O ) generated by the FP generation counter (23) for switching input to the generation counter (23)
In addition, it is possible to prevent the adverse effect of the separation frame pulse (F _A ) which becomes abnormal transiently.

Next, an embodiment of the present invention (claims 2 and 3) will be described with reference to FIGS. In FIG. 4, an FP generation counter (23) is provided as the output frame pulse generation means (200) in FIG. 1B, and a comparison unit (24) is provided as the comparison means (300) in FIG. A non-coincidence counter (2A) is provided as a counting means (500) in FIG. 1 (b), and a first synchronization means (601) in FIG. 1 (b) is further provided.
_A gate portion (28 _A ) is provided.

In the embodiment of the present invention [claim 3], the initial setting section (29) plays a role of controlling the gate section (28 _A ) when the frame pulse generating circuit is initialized. The decoder (27) plays a role of transmitting the output frame pulse (F _O ) output from the FP generation counter (23) to the comparison unit (24).

In FIGS. 4 and 5, the signal converter (2)
1) and the FP extraction section (22), as described above, separate the separated frame pulse (F _A ) from the reference clock signal (CF _S ) supplied from the reference clock source (1) (see FIG. 10).
Is extracted and transmitted to the comparison unit (24) and the gate unit ( _28A ).

As described above, the FP generation counter (23) repeatedly counts the output clock signal (C _O ) generated by the clock signal generation circuit (3) (see FIG. 10), and sets a predetermined speed (for example, 8 kilobits per second). Output frame pulse (F _O ), the gate section (28 _A ) is set to the conductive state, and the separation frame pulse (F _A ) is input via the gate section (28 _A ). Synchronizes the output phase of the output frame pulse (F _O ) with the separation frame pulse (F _A ), but the gate section (28 _A ) is set to the cut-off state, and the separation frame pulse (F _A ) is not input. In this case, the output frame pulse (F) synchronized in phase with the separated frame pulse (F _A ) input immediately before the cutoff
_O ) is maintained and the output frame pulse (F _O ) is output autonomously.

Output from FP generation counter (23)
Output frame pulse (F_O) Via the decoder (27)
Then, it is transmitted to the comparison unit (24). The comparison unit (24)
From the FP generation counter (23) via the decoder (27)
Output frame pulse (F_O) And F
Separated frame pulse transmitted from P extractor (22)
(F_A) And compare with the output frame pulse
(F _O) And the separated frame pulse (F_A)
Match detection signal output when is not transmitted
(E) is set to a mismatch state (for example, e = logic “0”)
Output frame pulse (F_O) And in phase
Separated frame pulse (F_A) Is transmitted,
The coincidence detection signal (e) is set to a coincidence state [for example, e = logic
"1"] and transmits it to the mismatch counter (2A).
You.

The non-coincidence counter (2A) is provided by the comparing unit (2
4) counts the number of times the coincidence detection signal (e) is continuously set to the non-coincidence state [= "0"], and outputs when the count value reaches a predetermined value. When the gate control signal (g _2A ) is set to a conductive state (for example, g _2A = logic “1”) and the gate control signal (g _2A ) is set to a conductive state (= “1”), the comparison unit (24) ) Is set to the matching state [= “1”], the output gate control signal (g _2A ) is set to the cutoff state (eg, g _2A = logic “0”). I do.

On the other hand, when the frame pulse generating circuit is activated, the initial setting unit (29) initializes the inside of the frame pulse generating circuit and transmits a gate control signal (g ₂₉ ) to the gate unit (28 _A ). In a conducting state [for example, g
₂₉ = logic "1"], and after a predetermined time has elapsed after the start and the frame pulse generation circuit has continued its stable operation, the gate control signal (g ₂₉ ) is cut off (for example, g ₂₉ =
Logic "0"].

The gate section (28 _A ) includes an initial setting section (2
When the gate control signal (g ₂₉ ) transmitted from 9) or the gate control signal (g _2A ) transmitted from the non-coincidence counter (2A) is set to the conducting state (= “1”), FP The separation frame pulse (F _A ) transmitted from the extraction unit (22) is input to the FP generation counter (23), and the gate control signal (g ₂₉ ) transmitted from the initialization unit (29) and the mismatch counter ( gate control signal transmitted from 2A) (g _2A) are both shut-off state (= "0")
When the value is set to, the separation frame pulse (F _A ) transmitted from the FP extraction unit (22) is cut off and is not input to the FP generation counter (23).

At the time (t ₁ ) at which the frame pulse generation circuit (2) starts to be activated, the FP generation counter (2)
3) generated by the comparator (2) through the decoder (27).
Although the output frame pulse (F _O ) transmitted to 4) and the separated frame pulse (F _A ) transmitted by the FP extraction unit (22) to the comparison unit (24) usually have inconsistencies in phase, the initial setting unit Since (29) sets the gate control signal (g ₂₉ ) transmitted to the gate section (28 _A ) to the conducting state [= "1"], the gate section (28 _A ) is set to the conducting state.

As a result, the separation frame pulse (F _A ) transmitted from the FP extraction unit (22) is input to the FP generation counter (23), and the FP generation counter (23) generates the output frame pulse (F _O). ) Is synchronized with the separated frame pulse (F _A ) [time (t ₂ )].

When the output frame pulse (F _O ) is phase-synchronized with the separation frame pulse (F _A ), the comparison unit (24)
Detects that the separated frame pulse (F _A ) in phase with the output frame pulse (F _O ) has been transmitted, and outputs a match detection signal (e = “1”) set to the match state to the non-match counter ( 2A).

As a result, the count value of the non-coincidence counter (2A) becomes zero, and the output gate control signal (g _2A ) is set to the cutoff state [= "0"]. On the other hand, the initial setting unit (2
9), as described above, the frame pulse generating circuit (2) has passed a predetermined time from the time you start (t ₁₎ [time (t _3)], the gate control signal transmitted to the gate portion (28 _A) ( g ₂₉ ) is set to the cutoff state [= "0"].

The gate unit (28 _A ) sets the initial setting unit (2 _A ) in a state where the gate control signal (g _2A ) transmitted from the mismatch counter (2A) is set to the cut-off state [= "0"].
When the gate control signal (g ₂₉ ) transmitted from 9) is set to the cutoff state [= "0"], the gate control signal (g29) is set to the cutoff state, and F
The separation frame pulse (F _A ) input from the P extraction unit (22) to the FP generation counter (23) is cut off.

The FP generation counter (23) determines when the input separation frame pulse (F _A ) is interrupted (t).
₃ ) Thereafter, the output frame pulse (F _O ), which is phase-synchronized with the separation frame pulse (F _A ) input immediately before the cutoff, is maintained, and the output frame pulse (F _O ) is generated and output autonomously. Along with the decoder (27)
To the comparison section (24).

When the phase of the separation frame pulse (F _A ) is constant, the separation frame pulse (F _A ) remains in phase with the output frame pulse (F _O ) even after the switching time (t ₃ ). And the comparison unit (24) also continues to set the coincidence detection signal (e) to the coincidence state [= "1"],
The non-coincidence counter (2A) also maintains the gate control signal (g _2A ) in the cut-off state [= "0"], and holds the gate section ( _28A ) in the cut-off state.

In this state, when the reference clock signal (CF _S ) is disturbed at the time (t ₄ ) and the separated frame pulse (F _A ) is also disturbed, the comparison unit (24) outputs the output frame pulse (F F). _O) and detects that matched separated frame pulse of the phase (F _a) is not transmitted, and sets the output to match detection signal (e) the mismatch condition [= "0"] [time (t ₅₎ ].

The non-coincidence counter (2A) includes a comparator (2
The gate control which counts the number of times the coincidence detection signal (e) transmitted from 4) is continuously set to the non-coincidence state [= "0"] and outputs when the count value reaches a predetermined value The signal (g _2A ) is set to the conductive state [= “1”], and the gate (28 _A ) is set to the conductive state [time (t ₆ )].

[0070] Note that the predetermined number, transient disturbances disappear suffer separation frame pulse (F _A) is, in consideration of the up count value stable separation frame pulse (F _A) is transmitted again It is determined.

When the gate section (28 _A ) is set to the conductive state, the FP generation counter (23) autonomously changes the phase of the output frame pulse (F _O ) being generated to the separated frame pulse that has begun to be input. (F _A ) [time (t
₇ )]. When the FP generation counter (23) synchronizes the output frame pulse (F _O ) with the separation frame pulse (F _A ), the comparison unit (24) outputs the output frame pulse (F _O ).
Since it is possible to detect that the separated frame pulse (F _A ) having the same phase as the transmitted signal is transmitted, and to set the coincidence detection signal (e) to the coincidence state [= "1"], the non-coincidence counter (2
A) is a state in which the gate control signal (g _2A ) is cut off [= "0"]
, The gate (28 _A ) is set to the cut-off state, and F
The separation frame pulse (F _A ) input to the P generation counter (23) is cut off.

The FP generation counter (23) determines when the input separation frame pulse (F _A ) is cut off (t).
₇ ) Thereafter, the output frame pulse (F _O ), which is phase-synchronized with the separation frame pulse (F _A ) input immediately before the cutoff, is maintained, and the output frame pulse (F _O ) is generated and output autonomously. Along with the decoder (27)
To the comparison section (24).

As is clear from the above description, the present invention
According to the embodiment of the claims 2 and 3], the comparison unit (24)
Stationary output frame generated by the FP generation counter (23)
Pulse (F_O), The separated frame pulse
(F_A) And monitor the output frame pulse (F_O)
And the stationary separation frame pulse (F_A)
Is detected, the separated frame pulse (F_A)
Cut off from the FP generation counter (23),
From the output frame pulse (F)_OAutonomously)
The output frame pulse (F_O) And phase
Separated frame pulse (F_A)
When the constant is detected, the separated frame pulse (F_A) Stable
Is determined to have occurred and the separated frame pulse
(F_A) Is input to the FP generation counter (23), and
Lame pulse (F_O) Is separated from the frame pulse (F_A)
While synchronizing the phase, the separated frame pulse (F_AMonitor
And the separated frame pulse (F_AWait for) to stabilize
And the separated frame pulse (F _A) FP generation counter
(23) To cut off the input to FP again, FP generation counter
The output frame pulse (F) generated by (23)_O)
The separated frame pulse (F_A) Adverse effects
Can be prevented.

Next, an embodiment of the present invention (claim 4) will be described with reference to FIG.
This will be described with reference to FIG. In FIG. 6, FIG.
Output frame pulse generating means in (c) (200)
1 is provided with an FP generation counter (23).
a comparing unit (24) as a comparing means (300) in (c);
And counting means (500) in FIG. 1 (c).
1 is provided with a mismatch counter (2A).
A gate section ( _28B ) is provided as the second synchronization means (602) in (c).

In FIGS. 6 and 7, the signal converter (2
1) and the FP extraction section (22), as described above, separate the separated frame pulse (F _A ) from the reference clock signal (CF _S ) supplied from the reference clock source (1) (see FIG. 10).
Is extracted and transmitted to the comparison unit (24) and the gate unit ( _28B ).

As described above, the FP generation counter (23) repeatedly counts the output clock signal (C _O ) generated by the clock signal generation circuit (3) (see FIG. 10), and outputs a predetermined speed [for example, 8 kilobits per second]. Output frame pulse (F _O ) is output, but when the gate (28 _B ) is set to the conductive state and the separation frame pulse (F _A ) is input via the gate (28 _B ). Synchronizes the output phase of the output frame pulse (F _O ) with the separation frame pulse (F _A ), but the gate section (28 _B ) is set to the cutoff state, and the separation frame pulse (F _A ) is not input. In this case, the output frame pulse (F) synchronized in phase with the separated frame pulse (F _A ) input immediately before the cutoff
_O ) is maintained and the output frame pulse (F _O ) is output autonomously.

Output from FP generation counter (23)
Output frame pulse (F_O) Via the decoder (27)
Then, it is transmitted to the comparison unit (24). The comparison unit (24)
From the FP generation counter (23) via the decoder (27)
Output frame pulse (F_O) And F
Separated frame pulse transmitted from P extractor (22)
(F_A) And compare with the output frame pulse
(F _O) And the separated frame pulse (F_A)
Match detection signal output when is not transmitted
(E) is set to a mismatch state (for example, e = logic “0”)
Output frame pulse (F_O) And in phase
Separated frame pulse (F_A) Is transmitted,
The coincidence detection signal (e) is set to a coincidence state [for example, e = logic
"1"] and transmits it to the mismatch counter (2A).
You.

The mismatch counter (2A) sets the output gate control signal (g _2A ) to a conductive state (eg, g _2A = logic “1”) in the initial setting state. Is set to a non-coincidence state [= "0"], the output gate control signal (g _2A ) is set to a cut-off state (for example, g _2A = logic "0"). At the same time, the number of times that the coincidence detection signal (e) is continuously set to the non-coincidence state [e = "0"] is counted, and when the count value reaches a predetermined value, the interruption state [=
The gate control signal (g _2A ) being set to “0”] is again set to the conductive state [= “1”].

When the gate control signal (g _2A ) transmitted from the mismatch counter (2A) is set to the conducting state (= “1”), the gate section (28 _B ) sets the FP extraction section (22). ) Transmitted from the separation frame pulse (F _A )
Is input to the FP generation counter (23). When the gate control signal (g _2A ) transmitted from the mismatch counter (2A) is set to the cut-off state (= “0”),
The separated frame pulse (F) transmitted from the extraction unit (22)
_A ) is shut off and is not input to the FP generation counter (23).

At the time (t ₁ ) when the frame pulse generation circuit (2) starts to be activated, the mismatch counter (2A)
Sets the gate control signal (g _2A ) transmitted to the gate section (28 _B ) to the conductive state [= “1”], the gate section (28 _B ) is set to the conductive state, and the FP is extracted. separating frame pulse transmitted from part (22) (F _a) is input to the FP generation counter (23), FP
The generation counter (23) synchronizes the phase of the output frame pulse (F _O ) to be generated with the separated frame pulse (F _A ) (time (t ₂ )).

When the output frame pulse (F _O ) is phase-synchronized with the separation frame pulse (F _A ), the comparator (24)
Detects that the separated frame pulse (F _A ) in phase with the output frame pulse (F _O ) has been transmitted, and outputs a match detection signal (e = “1”) set to the match state to the non-match counter ( 2A).

As a result, the count value of the non-coincidence counter (2A) becomes zero, and the output gate control signal (g _2A ) is maintained in the conductive state [= "1"]. In such a state, at time (t ₃ ), the reference clock signal (CF _S ) is disturbed,
When the separation frame pulse (F _A ) is also disturbed, the comparison unit (24) detects that the separation frame pulse (F _A ) in phase with the output frame pulse (F _O ) is not transmitted, and outputs the signal. coincidence detection signal to the (e) is set to mismatch condition [= "0"] [time (t _4)].

The non-coincidence counter (2A) includes a comparator (2
When the coincidence detection signal (e) transmitted from 4) is set to the non-coincidence state [= "0"], the output gate control signal (g _2A ) is set to the cut-off state [= "0"], and the gate is output. Section (28 _B ) is set to the cutoff state, and the FP generation counter (2) is set.
3) The separation frame pulse (F _A ) being input to (3) is cut off.

The FP generation counter (23) determines when the input separation frame pulse (F _A ) is interrupted (t).
₄ ) Thereafter, the output frame pulse (F _O ), which is phase-synchronized with the separated frame pulse (F _A ) input immediately before the cutoff, is maintained, and the output frame pulse (F _O ) is generated and output autonomously. Along with the decoder (27)
To the comparison section (24).

The non-coincidence counter (2A) counts the number of times that the coincidence detection signal (e) transmitted from the comparison section (24) is continuously set to the non-coincidence state [= "0"]. when it reaches the predetermined number, the gate control signal being set to the cutoff state [= "0"] and (g _2A), is again set to the conductive state [= "1"] [time (t ₅₎ ].

Note that the predetermined numerical value is determined in consideration of the count value until the disturbance that the separation frame pulse (F _A ) transiently suffers disappears and a stable separation frame pulse (F _A ) is transmitted again. It is determined.

When the gate section (28 _B ) is set to the conductive state, the FP generation counter (23) automatically determines the phase of the output frame pulse (F _O ) being generated autonomously by the separated frame pulse that has begun to be input. (F _A ) [time (t
₆ )].

When the FP generation counter (23) synchronizes the phase of the output frame pulse (F _O ) with the separation frame pulse (F _A ), the comparator (24) outputs the output frame pulse (F _O ).
_O ), it is possible to detect that the separated frame pulse (F _A ) having the same phase as the transmitted one is transmitted, and to set the coincidence detection signal (e) to the coincidence state [= "1"], the non-coincidence counter (2A) The gate control signal (g _2A ) is turned on [=
Maintained at "1"], sets the gate portion (28 _B) in the conductive state, the to FP generation counter (23) continues to input a separation frame pulse (F _A).

As is apparent from the above description, according to the embodiment of the present invention [Claim 4], the comparing section (24) controls the stationary output frame pulse (F _O ) generated by the FP generation counter (23). With reference to the separation frame pulse (F _A )
During the monitoring phase, the output frame pulse (F _O) and phase matched steady separation frame pulse (F _A) has been detected, the separation frame pulse (F _A) the FP generation counter (23) Fill in, although is outputted separate frame pulse (F _a) to the phase-synchronized with the output frame pulse (F _O) from FP generating counter (23), matched separated frames of the output frame pulse (F _O) and phase When the pulse (F _A ) is no longer detected, the input of the separation frame pulse (F _A ) to the FP generation counter (23) is immediately cut off, and the coincidence detection signal set to the non-coincidence state [e = "0"] counts the number of times of continuously detecting (e), the continuous detection times reaches a predetermined number, determines that stable phase changes in the separation frame pulse (F _a) has occurred, the separation frame pulse (F _a) Reenter the P generation counter (23), in order to phase lock the output frame pulse (F _O) for separating the frame pulse (F _A), the output frame pulse FP generating counter (23) is produced (F _O),
It is possible to prevent the adverse effect of the separated frame pulse (F _A ) that becomes transiently abnormal.

Next, an embodiment of the present invention (claim 5) will be described with reference to FIG.
This will be described with reference to FIG. In FIG. 8, FIG.
Output frame pulse generating means in (d) (200)
1 is provided with an FP generation counter (23).
a comparing unit (24) as a comparing means (300) in (d);
And a time limit means (700) in FIG. 1 (d).
A time limit section (2B) is provided as a second section, and a gate section (2) is provided as a second synchronization means (602) in FIG.
8 _B) are provided.

Referring to FIGS. 8 and 9, the signal converter (2
1) and the FP extraction section (22), as described above, separate the separated frame pulse (F _A ) from the reference clock signal (CF _S ) supplied from the reference clock source (1) (see FIG. 10).
Is extracted and transmitted to the comparison unit (24) and the gate unit ( _28B ).

As described above, the FP generation counter (23) repeatedly counts the output clock signal (C _O ) generated by the clock signal generation circuit (3) (see FIG. 10) and outputs a predetermined speed [for example, 8 kilobits per second]. Output frame pulse (F _O ) is output, but when the gate (28 _B ) is set to the conductive state and the separation frame pulse (F _A ) is input via the gate (28 _B ). Synchronizes the output phase of the output frame pulse (F _O ) with the separation frame pulse (F _A ), but the gate section (28 _B ) is set to the cutoff state, and the separation frame pulse (F _A ) is not input. In this case, the output frame pulse (F) synchronized in phase with the separated frame pulse (F _A ) input immediately before the cutoff
_O ) is maintained and the output frame pulse (F _O ) is output autonomously.

Output from FP generation counter (23)
Output frame pulse (F_O) Via the decoder (27)
Then, it is transmitted to the comparison unit (24). The comparison unit (24)
From the FP generation counter (23) via the decoder (27)
Output frame pulse (F_O) And F
Separated frame pulse transmitted from P extractor (22)
(F_A) And compare with the output frame pulse
(F _O) And the separated frame pulse (F_A)
Match detection signal output when is not transmitted
(E) is set to a mismatch state (for example, e = logic “0”)
Output frame pulse (F_O) And in phase
Separated frame pulse (F_A) Is transmitted,
The coincidence detection signal (e) is set to a coincidence state [for example, e = logic
"1"] and transmits it to the time limiter (2B).

In the initial setting state, the time control section (2B) sets the output gate control signal (g _2B ) to a conductive state (eg, g _2B = logic “1”).
When the coincidence detection signal (e) transmitted from 4) is set to a non-coincidence state [= "0"], the output gate control signal ( _g2B ) is turned off (for example, _g2B = logic "0"). When the elapsed time reaches a predetermined time (T), the gate control signal (g _2B ) being set to the cut-off state [= "0"] is turned on again. [=
"1"].

In the gate section (28 _B ), the gate control signal (g _2B ) transmitted from the time limit section ( _2B ) is in a conducting state (=
If “1” is set, the FP extraction unit (2
2) The separated frame pulse (F _A ) transmitted from
The gate control signal (g _2B ) transmitted from the time limiter (2B) is input to the generation counter (23).
“0”), the FP extraction unit (2
The separation frame pulse (F _A ) transmitted from 2) is cut off and is not input to the FP generation counter (23).

At the time (t ₁ ) at which the frame pulse generation circuit (2) starts to be activated, the timed section (2B) turns on the gate control signal (g _2B ) transmitted to the gate section (28 _B ) [= “ 1 "], the gate (2
8 _B) is set to the conductive state, FP extractor (2
The separation frame pulse (F _A ) transmitted from 2) is FP
Input to the generation counter (23), the FP generation counter (23) synchronizes the phase of the output frame pulse (F _O ) to be generated with the separated frame pulse (F _A ) (time (t ₂ )).

When the output frame pulse (F _O ) is phase-synchronized with the separation frame pulse (F _A ), the comparison section (24)
Detects that the separated frame pulse (F _A ) having the same phase as the output frame pulse (F _O ) is transmitted, and outputs the coincidence detection signal (e = “1”) set to the coincidence state to the time limiter ( 2B).

As a result, the timed section (2B) maintains the output gate control signal (g _2B ) in the conductive state [= "1"]. In such a state, at time (t ₃ ), the reference clock signal (CF _S ) is disturbed and the separated frame pulse (F _A )
When the disturbance also occurs, the comparison unit (24) detects that the separated frame pulse (F _A ) in phase with the output frame pulse (F _O ) has not been transmitted, and outputs a coincidence detection signal (e). setting the mismatch condition [= "0"] [time (time point (t _4)].

In the time limit section (2B), the coincidence detection signal (e) transmitted from the comparison section (24) is in a non-coincidence state [= "0"].
, The gate control signal (g _2B ) to be output is set to the cut-off state [= "0"], the gate section (28 _B ) is set to the cut-off state, and is being input to the FP generation counter (23). Of the separation frame pulse (F _A ).

The FP generation counter (23) determines the time (t) at which the input separation frame pulse (F _A ) is cut off.
₄ ) Thereafter, the output frame pulse (F _O ), which is phase-synchronized with the separated frame pulse (F _A ) input immediately before the cutoff, is maintained, and the output frame pulse (F _O ) is generated and output autonomously. Along with the decoder (27)
To the comparison section (24).

When the coincidence detection signal (e) transmitted from the comparison unit (24) is continuously set to a non-coincidence state [= "0"], the time period unit (2B) starts counting time, When the time reaches a predetermined time (T), the gate control signal (g _2B ) being set to the cut-off state [= "0"] is set to the conductive state [= "1"] again [ point in time (t _5)].

The predetermined time (T) means that the disturbance which the separation frame pulse (F _A ) transiently receives disappears,
It is determined in consideration of the count value until the stable separated frame pulse (F _A ) is transmitted again.

When the gate section (28 _B ) is set to the conductive state, the FP generation counter (23) autonomously changes the phase of the output frame pulse (F _O ) being generated to the separated frame pulse that has begun to be input. (F _A ) [time (t
₆ )].

When the FP generation counter (23) synchronizes the phase of the output frame pulse (F _O ) with the separation frame pulse (F _A ), the comparator (24) outputs the output frame pulse (F F).
_O ), it is possible to detect that the separated frame pulse (F _A ) having the same phase as the transmitted one is transmitted, and to set the coincidence detection signal (e) to the coincidence state [= logic “1”].
B) keeps the gate control signal (g _2B ) in the conducting state [= "1"] without setting time, sets the gate section (28 _B ) in the conducting state, and sets the FP generation counter (2).
The separation frame pulse (F _A ) is continuously input to 3).

As apparent from the above description, according to the embodiment of the present invention [Claim 5], the comparing section (24) uses the stationary output frame pulse (F _O ) generated by the FP generation counter (23). With reference to the separation frame pulse (F _A )
During the monitoring phase, the output frame pulse (F _O) and phase matched steady separation frame pulse (F _A) has been detected, the separation frame pulse (F _A) the FP generation counter (23) Fill in, although is outputted separate frame pulse (F _a) to the phase-synchronized with the output frame pulse (F _O) from FP generating counter (23), matched separated frames of the output frame pulse (F _O) and phase When the pulse (F _A ) is no longer detected, the input of the separated frame pulse (F _A ) to the FP generation counter (23) is immediately cut off, and time measurement is started, and when the elapsed time reaches a predetermined time. , Separation frame pulse (F _A )
Is determined, a separated frame pulse (F _A ) is input again to the FP generation counter (23), and the output frame pulse (F _O ) is phase-synchronized with the separated frame pulse (F _A ). Therefore, the FP generation counter (2
3) It is possible to prevent the output frame pulse (F _O ) generated by 3) from being adversely affected by the separation frame pulse (F _A ) which becomes transiently abnormal.

FIGS. 2 to 9 are merely examples of the present invention. For example, the configuration of the frame pulse generating circuit is not limited to the illustrated one, and various other modifications are considered. However, the effect of the present invention does not change in any case. The clock supply system to which the present invention is applied is shown in FIG.
However, the present invention is not limited to the one shown in FIG. 0 and many other modifications are considered, but the effect of the present invention does not change in any case.

[0107]

As described above, according to the present invention (claim 1), when the external frame pulse is disturbed, the input of the external frame pulse is immediately stopped by the output frame pulse generating means for generating the output frame pulse. After the recovery of the stability of the external frame pulse is confirmed by the synchronization-maintaining frame pulse generator provided separately from the output frame pulse generator, the frame pulse is output to the output frame pulse generator. The generation unit can always generate an output frame pulse synchronized with a stable external frame pulse.

Further, according to the present invention (claims 2 and 3), the output frame pulse generating means autonomously generates the output frame pulse without receiving the external frame pulse, and simultaneously outputs the external frame pulse with the external frame pulse. The phase change of the external frame pulse is monitored by comparing with the frame pulse, and when a predetermined number of consecutive phase changes are detected, it is determined that a steady phase change has occurred in the external frame pulse, and the output frame pulse is determined. Since the phase of the output frame pulse is input to the generating means and the phase of the output frame pulse is synchronized, it is possible to prevent the phase of the output frame pulse from being synchronized with the disturbed external frame pulse.

According to the present invention (claims 4 and 5), the external frame pulse is compared with the output frame pulse generated by the output frame pulse generating means to which the external frame pulse is input, thereby comparing the external frame pulse. The input of the external frame pulse to the output frame pulse generating means is stopped immediately when the phase change is detected, and after the phase change of the external frame pulse is determined to be stationary, Since the phase of the output frame pulse is inputted to the frame pulse generating means and the phase of the output frame pulse is synchronized with the new external frame pulse, it is possible to prevent the phase of the output frame pulse from being synchronized with the disturbed external frame pulse.

[Brief description of the drawings]

1 (a) is a diagram showing the principle of the present invention, FIG. 1 (a) is a diagram of claim 1, FIG. 1 (b) is a diagram of claims 2 and 3, and FIG. (d) shows the principle of claim 5 respectively.

FIG. 2 is a diagram showing a frame pulse generation circuit according to an embodiment of the present invention (claim 1);

FIG. 3 is a diagram showing an example of a signal waveform in FIG. 2;

FIG. 4 is a diagram showing a frame pulse generation circuit according to an embodiment of the present invention (claims 2 and 3);

FIG. 5 is a diagram showing an example of a signal waveform in FIG. 4;

FIG. 6 is a diagram showing a frame pulse generation circuit according to an embodiment of the present invention (claim 4);

FIG. 7 is a diagram showing an example of a signal waveform in FIG. 6;

FIG. 8 is a diagram showing a frame pulse generating circuit according to an embodiment of the present invention (claim 5);

9 is a diagram showing an example of a signal waveform in FIG.

FIG. 10 is a diagram illustrating an example of a clock supply system to which the present invention is applied;

FIG. 11 is a diagram showing an example of a conventional frame pulse generation circuit.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 reference clock source 2 frame pulse generation circuit 3 clock signal generation circuit 4 clock supply device 5 supplied device 21 signal conversion unit 22 FP extraction unit 23 FP generation counter 24 comparison unit 25 switching unit 26 pseudo-synchronous counter 27 decoder 28 _A , 28 _B gate unit 29 Initial setting unit 2A Non-coincidence counter 2B Timed unit 100 Synchronization holding frame pulse generation unit 200 Output frame pulse generation unit 300 Comparison unit 400 Synchronization switching unit 500 Counting unit 601 First synchronization unit 602 Second synchronization Means 700 timed means

──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Shinichi Fukumoto 1015 Uedanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Inside Fujitsu Limited (72) Inventor Tatsugo Fukui 1-6-1 Uchisaiwaicho, Chiyoda-ku, Tokyo Nippon Telegraph and Telephone (56) References JP-A-6-177870 (JP, A) JP-A-5-30100 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04L 7/08 H04L 7/00 H04L 7/033

Claims (5)

(57) [Claims] 1. A synchronizing frame pulse having a predetermined period synchronized with a phase of an input external frame pulse is generated.
When the external frame pulse being input is interrupted, the frame holding pulse generating means for continuously generating the frame holding pulse for the predetermined period while maintaining the phase immediately before the interruption is provided, and An output frame pulse of a predetermined cycle synchronized with the frame pulse is generated, and when the external frame pulse being input is interrupted, the output frame pulse of the predetermined cycle is continuously generated while maintaining the phase immediately before the interruption. An output frame pulse generating unit; a comparing unit that compares the phase of the external frame pulse with reference to the synchronization maintaining frame pulse generated by the synchronization maintaining frame pulse generating unit; When detecting that the external frame pulse in phase with the frame pulse has not been input, The external frame pulse is input to the synchronizing frame pulse generating unit without being input to the output frame pulse generating unit, and the comparing unit outputs the external frame pulse whose phase coincides with the synchronizing frame pulse. And a synchronous switching unit for inputting the external frame pulse to the output frame pulse generating unit without inputting the external frame pulse to the synchronous holding frame pulse generating unit when detecting the input. Pulse generation circuit. 2. An output frame pulse having a predetermined period synchronized with a phase of an input external frame pulse is generated, and when the external frame pulse being input is interrupted, the output frame pulse of the predetermined period is held in a state where the phase immediately before the interruption is maintained. Output frame pulse generating means for continuously generating an output frame pulse; comparing means for comparing the phase of the external frame pulse with reference to the output frame pulse generated by the output frame pulse generating means; Counting means for counting the number of times that the means has continuously detected that the external frame pulse in phase with the output frame pulse has not been input; and the count value of the counting means has reached a predetermined number. In this case, the external frame pulse is input to the output frame pulse generation unit, and the count value of the counting unit is If you drop than the number defined because, first frame pulse generating circuit and providing a synchronized means for stopping the input to the output frame pulse generating means of the external frame pulse. 3. The first synchronizing means inputs the external frame pulse to the output frame pulse generating means when the output frame pulse generating means starts operation, and 3. The frame pulse generating circuit according to claim 2, wherein the input of the external frame pulse to the output frame pulse generating means is stopped when the numerical value falls below the predetermined number. 4. An output frame pulse having a predetermined period synchronized with the input external frame pulse is generated, and when the external frame pulse being input is interrupted, the output frame pulse of the predetermined period is held in a state where the phase immediately before the interruption is maintained. Output frame pulse generating means for continuously generating an output frame pulse; comparing means for comparing the phase of the external frame pulse with reference to the output frame pulse generated by the output frame pulse generating means; Counting means for counting the number of times that the means has continuously detected that the external frame pulse in phase with the output frame pulse has not been input; and the external means in which the comparing means has the phase in agreement with the output frame pulse. When detecting that a frame pulse has not been input, the output of the external frame pulse is performed. A second synchronizing unit for stopping the input to the frame pulse generating unit and for inputting the external frame pulse to the output frame pulse generating unit when the count value of the counting unit reaches a predetermined number; And a frame pulse generating circuit. 5. An output frame pulse having a predetermined cycle synchronized with the input external frame pulse is generated. When the external frame pulse being input is interrupted, the output frame pulse of the predetermined cycle is maintained in a state where the phase immediately before the interrupt is maintained. Output frame pulse generating means for continuously generating an output frame pulse; comparing means for comparing the phase of the external frame pulse with reference to the output frame pulse generated by the output frame pulse generating means; Means for starting when the means detects that the external frame pulse having the same phase as the output frame pulse is not input, and starting and stopping after elapse of a predetermined time; Stop inputting the external frame pulse to the output frame pulse generating means, If the unit is designated start, frame pulse generating circuit, characterized in that providing a second synchronization means for inputting the external frame pulse to said output frame pulse generating means.