JPH09232522A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device and a manufacturing method thereof whereby nearly a constant resistance is obtained under a gate bias voltage, without being influenced by the bias voltage between the drain and source of a field-effect transistor(FET) when it is used a variable resistance element. SOLUTION: A resistance element 20 (resistance R2 ) is connected between the source and drain of a junction EFT (JFET)10. When the JFET 10 is set on, the channel resistance between the source drain shows a low value R1 and source-drain combined resistance R is (R1 ×R2 )/(R1 +R2 ), constant. When the JFET 10 is set off, the source-drain channel resistance is higher than R2 and hence the resultant resistance R is nearly equal to R2 , substantially constant. Thus, a variable resistance element showing constant resistance at the on- and off-starts of the JFET 10, irrespective of the source-drain bias is realizable.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a variable resistance element using a field effect transistor and a method of manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, a field effect transistor (hereinafter referred to as FET) has been used as a variable resistance element.
That. ) Is known. In this method, the bias voltage applied to the gate of the FET is changed to change the channel resistance value between the source and the drain, and this is used as a variable resistance element. In this case, the channel resistance value changes not only with the bias voltage of the gate but also with the bias voltage between the source and the drain. This is because generally in the FET, when the bias voltage between the source and the drain is changed in a state where the bias voltage is applied to the gate, the channel resistance value changes except in the saturation region. Particularly, when the channel resistance value is high, the fluctuation of the channel resistance value due to the change of the bias voltage between the source and the drain becomes large.

[0003]

FIG. 11 shows a general FET.
FIG. 12 shows element characteristics when this FET is used as a variable resistance element. In FIG.
The horizontal axis represents the source-drain (SD) bias voltage of the FET, and the vertical axis represents the channel resistance value R.

[0004] As shown in FIG. 12, in a state (V _G = 0V) is not applied gate bias voltage, source
The fluctuation of the channel resistance value with respect to the fluctuation of the bias voltage between the drains is small. For example, the channel resistance value is almost constant in the range of the bias voltage between the source and the drain of about 0.2V to 1.2V. However, as a gate bias voltage of 1 V (V _G = 1 V) is applied,
In the state where the channel resistance value between the drains is increased, the channel resistance value is greatly changed with the change of the bias voltage between the source and the drain, and it cannot be used as a resistance element.

The fluctuation of the channel resistance value due to the fluctuation of the bias voltage between the source and the drain appears as the distortion of the waveform of the output signal with respect to the waveform of the input signal. The distortion of the output waveform becomes a problem in many fields including optical communication.

The present invention has been made in view of the above problems, and when the FET is used as a variable resistance element, it is applied without being affected by the fluctuation of the source-drain bias voltage of the FET. Another object of the present invention is to provide a semiconductor device and a manufacturing method thereof, which can obtain an output signal waveform having a substantially constant resistance value under a certain gate bias voltage and less distortion with respect to an input signal waveform.

[0007]

A semiconductor device according to the present invention includes a field effect transistor in which a channel resistance value between a source and a drain changes according to a bias voltage applied to a gate, and an on-state of the field effect transistor. And a resistance element having a resistance value higher than a channel resistance value between the source and the drain at the time and connected between the source and the drain of the field effect transistor.

The semiconductor device manufacturing method according to the present invention includes a field effect transistor in which a channel resistance value between a source and a drain changes according to a bias voltage applied to a gate, and when the field effect transistor is turned on. A resistance value higher than a channel resistance value between a source and a drain of the field effect transistor, and a resistance element connected between the source and the drain of the field effect transistor. Also, the layer to be the drain extraction electrode and the layer to be the resistance element are formed in the same step.

Another method of manufacturing a semiconductor device according to the present invention is a field effect transistor in which a channel resistance value between a source and a drain changes according to a bias voltage applied to a gate, and when the field effect transistor is on. And a resistance value higher than a channel resistance value between the source and the drain of the field effect transistor, and a resistance element connected between the source and the drain of the field effect transistor. The extraction electrode layer and the resistance element layer are formed in the same step.

In the semiconductor device of the present invention, when the field effect transistor is turned on, the combined resistance value (almost constant value) of the resistance value of the resistance element and the channel resistance value of the field effect transistor is set as a variable resistance element. The resistance value of the resistance element (almost constant value) becomes the resistance value of the variable resistance element when the field effect transistor is off.

In the method of manufacturing a semiconductor device of the present invention, the layer to be the resistance element is simultaneously formed in the step of forming the source / drain lead-out electrodes. In another method of manufacturing a semiconductor device, the layer to be the resistance element is simultaneously formed in the step of forming the gate extraction electrode.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a circuit configuration of a semiconductor device according to an embodiment of the present invention. This semiconductor device
For example, a junction field effect transistor (JFET) 10
And the source (S) and drain (D) of this JFET 10.
And a resistance element 20 having a fixed resistance value that is connected in parallel. The resistance element 20 is formed of, for example, a polycrystalline silicon film, as described later.

Here, when the JFET 10 is turned on, the channel resistance value between the source and the drain is R ₁ , and the resistance element 2
The resistance value of 0 is R ₂ . R ₁ and R ₂ are constant values and satisfy the following expression (1). R ₂ > R ₁ (1)

Next, the operation of the semiconductor device having the above-mentioned structure will be described with reference to FIG. In this figure, the horizontal axis represents the bias voltage between the source and drain (SD) of the FET, and the vertical axis represents the combined resistance value of the channel resistance value between the source and drain of the JFET 10 and the resistance value of the resistance element 20. R
Is shown.

First, when the bias voltage is not applied to the gate (V _G = 0V), the JFET 10 is turned on, and the channel resistance value R ₁ between the source and drain at that time is low. At this time, the combined resistance value R between the source terminal 11 and the drain terminal 12 is expressed by the following equation (2). R = (R ₁ × R ₂ ) / (R ₁ + R ₂ ) ... (2) As is clear from this equation (2), since both R ₁ and R ₂ are constant values, the combined resistance value R is also constant. And becomes as shown in FIG.

On the other hand, when a bias voltage is applied to the gate (V _G > V _P ), the JFET 10 is turned off, and the channel resistance value between the source and drain thereof is lower than the resistance value R ₂ of the resistance element 20. It shows a sufficiently high value R ₁ ′.
However, V _P is the drain voltage when the pinch-off voltage, that is, the channel disappears near the drain when the difference from the gate voltage becomes small near the drain by increasing the drain voltage. At this time, the combined resistance value R between the source terminal 11 and the drain terminal 12 is expressed by the following equation (3). R = (R ₁ ′ × R ₂ ) / (R ₁ ′ + R ₂ ) = R ₂ / (1 + R ₂ / R ₁ ′) ≈R ₂ (3) As is clear from the equation (3), the resistance is Since the resistance value R ₂ of the element 20 is constant, the combined resistance value R is also constant,
It becomes as shown in FIG.

That is, whether the channel resistance value of the JFET 10 is high or low, the combined resistance value R hardly changes regardless of the fluctuation of the bias voltage between the source and the drain. Therefore, it is possible to configure a variable resistance element having a substantially constant resistance value according to the gate voltage, regardless of the variation of the bias voltage between the source and the drain.

FIGS. 3A and 3B show a concrete element structure of the semiconductor device shown in FIG. Here, FIG. 6B shows the planar structure of the main layer, and FIG.
3 shows a cross-sectional configuration along the line AA ′ in FIG.

As shown in these figures, an n-type single crystal silicon semiconductor layer 32 formed by an epitaxial growth method is formed on a p-type silicon substrate 31. An n ⁺ buried region 33 containing a high concentration of n-type impurities is selectively formed near the boundary between the silicon substrate 31 and the single crystal silicon semiconductor layer 32 in the region where the JFET 10 (FIG. 1) is to be formed. . In a predetermined region away from the formation region of JFET10, as shown in FIG. 3 (b), n ⁺ buried reaching the region 33 n ⁺ -type electrode extraction region 51 is selectively formed.

In the vicinity of the surface of the single crystal silicon semiconductor layer 32, except for the region where the JFET 10 is to be formed, an element isolation region 34- formed of a thick silicon oxide film by a selective oxidation method (LOCOS (Local Oxidation of Silicon) method).
1, 34-2 are formed. Further, p ⁺ regions 35-1 and 35-2 containing high-concentration p-type impurities are formed below the element isolation regions 34-1 and 34-2 so as to reach the silicon substrate 31, respectively. .

The JFET 10 is formed near the surface of the single crystal silicon semiconductor layer 32 in the region where the JFET 10 is to be formed.
P ⁺ diffusion regions 36-1 serving as the source and drain regions of
36-2 and these p ⁺ diffusion regions 36-1 and 36-2
P-type channel region 3 arranged so as to be sandwiched by
7 and an n-type gate region 38 arranged near the surface of the central portion of the channel region 37 are formed. An n-type impurity region 40 is connected between the channel region 37 and the n ⁺ buried region 33. The n-type impurity region 40 serves as a back gate of the JFET 10, and its presence can improve the characteristics of the JFET 10 (for example, how to close the channel is good) and stabilize the characteristics.

An insulating layer 39 made of a silicon oxide film or the like is formed on the element isolation regions 34-1 and 34-2 except the region where the JFET 10 is to be formed.
P is provided on the insulating layer 39 and the region where 10 is to be formed.
Polycrystalline silicon layers 41-1 to 41-3 containing type impurities are selectively formed. Of these, the polycrystalline silicon layers 41-1 and 41-2 have p ⁺ diffusion regions 36-
1, 36-2, and the other end of each insulating layer 39.
It extends upward and becomes a source extraction electrode and a drain extraction electrode of the JFET 10, respectively. The polycrystalline silicon layer 41-3 is entirely formed on the insulating layer 39 and functions as the resistance element 20 (FIG. 1).

An insulating layer 42 made of a silicon oxide film or the like is formed on the entire surface so as to cover the above element structure. And
An opening 43 reaching the surface of the single crystal silicon semiconductor layer 32 is formed through the insulating layer 39 and the insulating layer 42, and a sidewall 44 made of an insulating film such as a silicon oxide film is formed on the inner side surface thereof. There is. Channel region 37
Is formed in the area defined by the opening 43,
The gate region 38 is formed in a region defined by the sidewall 44.

A second polycrystalline silicon layer 46 is selectively formed on the gate region 38 and the insulating layer 42 in the region where the JFET 10 is formed. The polycrystalline silicon layer 46 is connected to the gate region 38,
It functions as a gate extraction electrode.

Insulating layer 42 has contact holes 48- that reach polycrystalline silicon layers 41-1 and 41-2, respectively.
1, 48-2, contact holes 48-3, 48-4 reaching the polycrystalline silicon layer 41-3, and a contact hole 48-5 reaching the n ⁺ -type electrode lead-out region 51. Then, on the insulating layer 42 and the polycrystalline silicon layer 46, metal wiring layers 49-1 to 49-4 made of aluminum (Al) or the like are formed and patterned into a predetermined shape.

Among them, the metal wiring layer 49-1 includes the polycrystalline silicon layer 41-1 (source of the JFET 10) and the polycrystalline silicon layer 41-3 (resistive element) via the contact holes 48-1 and 48-4. 20) and one end thereof, and is also connected to a signal source, a power source, or the like, not shown, and the metal wiring layer 49-2 has a contact hole 48-.
2, 48-3 via the polycrystalline silicon layer 41-2 (J
Drain of FET 10) and polycrystalline silicon layer 41-3
It is connected to the other end of the (resistive element 20) and is also connected to ground or a power source. That is, the resistance element 20
Are connected in parallel between the source and drain of the JFET 10. In addition, as shown in FIG. 3B, the metal wiring layer 4
9-3 is connected to the n ⁺ -type electrode lead-out region 51 via a contact hole 48-5. Metal wiring layer 49
-4 is a polycrystalline silicon layer 4 as a gate extraction electrode
6 is connected.

Next, with reference to FIGS. 4 and 5 and FIG. 3A, a method of manufacturing the semiconductor device having the above-described structure will be described.

In FIG. 4A, the n-type single crystal silicon semiconductor layer 32 is formed on the p-type silicon substrate 31, and the boundary portion between the silicon substrate 31 and the single crystal silicon semiconductor layer 32 in the FET formation region. An n ⁺ buried region 33 is selectively formed in the vicinity, element isolation regions 34-1 and 34-2 are formed in regions other than the JFET formation region, and further below these element isolation regions 34-1 and 34-2. This shows a state in which p ⁺ regions 35-1 and 35-2 containing high-concentration p-type impurities are formed so as to reach the silicon substrate 31 on the side. On the other hand, although not shown in FIG.
An n ⁺ -type electrode lead-out region 51 (see FIG. 3B) that reaches the n ⁺ buried region 33 is selectively formed in a predetermined region away from the formation region of. Since the method is a known method up to this point, a detailed description thereof will be omitted and the following steps will be described in detail.

That is, as shown in FIG. 3A, the insulating layer (silicon oxide film) 39 is selectively formed in the region excluding the JFET formation region by, for example, the thermal oxidation method. next,
For example, after a polycrystalline silicon layer containing p-type impurities is formed on the entire surface by the CVD (Chemical Vapor Deposition) method, this is patterned and the polycrystalline silicon layer 41 serving as the source (drain) extraction electrode of the JFET 10 is formed.
-1 (41-2) and a polycrystalline silicon layer 41-3 to be the resistance element 20 are formed. At that time, it is possible to give an arbitrary resistance value to the polycrystalline silicon layer 41-3 by selecting the impurity concentration, the aspect ratio of the pattern, and the like.
The impurity concentrations of the polycrystalline silicon layer 41-1 (41-2) and the polycrystalline silicon layer 41-3 do not necessarily have to be the same, and may be different as necessary. However, in this case, the impurity introduction step has two steps.

Next, as shown in FIG. 3B, after an insulating layer 42 made of a silicon oxide film or the like is formed on the entire surface,
The insulating layer 42 and the polycrystalline silicon layer 41-1 are formed in the central portion of the JFET formation region (region to be the channel region 37).
An opening 43 which penetrates (41-2) and reaches the single crystal silicon semiconductor layer 32 is formed. To form the opening 43, for example, the insulating layer 42 is first selectively etched by dry etching to provide a window, and then the polycrystalline silicon layer 41-1 (41-2) is selectively etched through this window. Do that. In this case, the polycrystalline silicon layer 41-
The etching of 1 (41-2) is performed by wet etching using, for example, a KOH (potassium hydroxide) solution or an APW solution (a mixed solution of ethylenediamine, pyrocatechol and H ₂ O). Note that the opening 43 is formed by selectively etching the insulating layer 42 by dry etching to provide a window, and then using the same resist mask used for this, by the RIE (reactive ion etching) method to form the polycrystalline silicon layer 41. -1 (41-2) may be formed by etching.

Next, as shown in FIG. 5A, the opening 4
3, p-type impurities such as BF ₂ ⁺ (boron fluoride) or B ⁺ (boron) are ion-implanted near the surface of the single crystal silicon semiconductor layer 32. At this time, the implantation energy of BF ₂ ⁺ is, eg, 150 keV, and the dose amount is, eg, 1.5 × 10 ¹² / cm ² . In the case of B ⁺ , the implantation energy is, for example, 60 keV, and the dose amount is 1.5 ×
It is 10 ¹² / cm ² . Further, an n-type impurity such as P (phosphorus), As (arsenic) or Sb (antimony) is added to the deep portion (n ⁺ buried region 33) of the single crystal silicon semiconductor layer 32.
And a channel region 37).
However, when the n-type impurity region 40 as the back gate is not provided, this n-type impurity ion implantation is not performed.

Next, as also shown in FIG. 5 (a),
By performing heat treatment, the ion-implanted p-type impurities are activated to form the p-type channel region 37. At this time, at the same time, the p-type impurities in the polycrystalline silicon layers 41-1 and 41-2 are thermally diffused into the single crystal silicon semiconductor layer 32, and p ⁺ diffusion regions 36-1 and 36 3 serving as a source and a drain are formed.
6-2 is formed, and the n-type impurity ion-implanted for forming the back gate is activated to form the n-type impurity region 40 connecting the n ⁺ buried region 33 and the channel region 37. .

Next, as shown in FIG. 2B, an insulating film made of a silicon oxide film or the like is formed on the entire surface by, for example, the CVD method, and then this is formed by RIE (Reactive Ion Etching).
Then, the side wall 44 is formed on the inner surface of the opening 43 by the anisotropic etching method. Subsequently, a second-layer polycrystalline silicon layer 46 containing an n-type impurity such as As or P is formed on the entire surface, or a polycrystalline silicon layer containing no impurity is formed, and then an As or P n
The n-type impurity in the polycrystalline silicon layer 46 is thermally diffused into the channel region 37 by ion-implanting the type impurity and heat-treating the n-type gate region 38.

Next, as shown in FIG.
Patterning is performed so as to remove the polycrystalline silicon layer 46 other than the JFET formation region, and contact holes 48-1 and 48-2 that penetrate the insulating layer 42 and reach the polycrystalline silicon layers 41-1 and 41-2. And contact holes 48-3, 48- reaching the polycrystalline silicon layer 41-3.
4 and a contact hole 48-5 which reaches the n ⁺ -type electrode lead-out region 51.

Next, these contact holes 48-1
~ 48-5 to cover Al (aluminum),
A metal wiring layer made of Al-Si or Al-Si-Cu is formed and patterned to form a metal wiring layer 49-
1 to 49-4 are formed. At this time, the metal wiring layer 49-1
Connects the polycrystalline silicon layer 41-1 (source of the JFET 10) and one end of the polycrystalline silicon layer 41-3 (resistive element 20) through the contact holes 48-1 and 48-4 and illustrates them. Patterning so as to connect to a signal source or a power source. The metal wiring layer 49-2 has contact holes 48-2 and 48-3.
The polycrystalline silicon layer 41-2 (drain of the JFET 10) and the polycrystalline silicon layer 41-3 (resistive element 20)
Is patterned so as to be connected to the other end portion thereof and to be connected to a ground or a power source (not shown).
As a result, the resistance element 20 is connected in parallel between the source and drain of the JFET 10. The metal wiring layer 49-3 is patterned so as to connect between the n ⁺ -type electrode lead-out region 51 and a power source (not shown) by the contact hole 48-5, and the metal wiring layer 49-4 is formed by the polycrystalline silicon layer 46. And a power supply (not shown) are connected. Then, a protective film (passivation film) or the like (not shown) is formed so as to cover the above structure.

From the above, the source region (p ⁺ diffusion region 3
6-1), the JFET 10 including the drain region (p ⁺ diffusion region 36-2) and the gate region 38, and the resistance element 20 including the first-layer polycrystalline silicon layer 41-3 are formed to form a p-channel JFET. A semiconductor device as a variable resistance element obtained by connecting a resistance element in parallel can be obtained.

Next, a semiconductor device according to another embodiment of the present invention will be described.

FIGS. 6A and 6B show the element structure of a semiconductor device according to another embodiment of the present invention.
Here, FIG. 7B shows the planar structure of the main layer, and FIG. 9A shows the sectional structure taken along the line AA ′ in FIG. In this figure, the same components as those of the above-described embodiment (FIG. 3) are designated by the same reference numerals and the description thereof will be omitted as appropriate.

The above embodiment (FIGS. 3 to 5) is a JF.
The resistance element 20 connected in parallel between the source and drain of the ET 10 is a polycrystalline silicon layer of the first layer (that is, source / drain extraction electrode (polycrystalline silicon layer 41-1,
41-2) Polycrystalline silicon layer 41 formed in the same step
-3), but in contrast to this,
In the present embodiment, the resistance element 20 is composed of a second-layer polycrystalline silicon layer (that is, a polycrystalline silicon layer formed for a gate extraction electrode).

That is, in the semiconductor device of the present embodiment, as shown in FIGS. 6A and 6B, the first polycrystalline silicon layer is the source / drain extraction electrode of the JFET 10. Crystal silicon layers 41-1 and 41
-2 is formed, on the other hand, as the second-layer polycrystalline silicon layer, in addition to the polycrystalline silicon layer 46-1 serving as the gate extraction electrode, the polycrystalline silicon layer 46-2 is formed on the insulating layer 42. The polycrystalline silicon layer 4 is formed.
6-2 is used as the resistance element 20.

The insulating layer 42 and the polycrystalline silicon layers 46-1 and 46-2 formed thereon are covered with the insulating layer 60. Then, between the polycrystalline silicon layer 41-1 which is the source extraction electrode and the metal wiring layer 49-1,
And the polycrystalline silicon layer 4 serving as the drain extraction electrode
Insulating layers 42, 6 are provided between 1-2 and the metal wiring layer 49-2.
0, a contact hole 148-1 formed through
Connected by 148-2, and the polycrystalline silicon layer 46-
2 and the metal wiring layers 49-2, 49-1 between the insulating layer 6
0, a contact hole 148-3 formed through
It is connected by 148-4. FIG. 6 (b)
As shown in FIG. 7, the n ⁺ type electrode lead-out region 51 and the metal wiring layer 49-3 are connected by a contact hole 148-5 formed through the insulating layers 42 and 60. Further, between the polycrystalline silicon layer 46-1 which is the gate extraction electrode and the metal wiring layer 49-4, a contact hole 148- formed through the insulating layer 60.
6. Other configurations are the same as those in FIG.

Next, a method of manufacturing the semiconductor device having the above-described structure will be described with reference to FIGS.

In this manufacturing method, the p-type silicon substrate 3 is used.
1. Formation of single crystal silicon semiconductor layer 32 on 1; element isolation regions 34-1, 34-2, p ⁺ regions 35-1, 35-2
And the step of forming the n ⁺ -type electrode lead-out region 51 are the same as those in the above embodiment.

In the present embodiment, after these steps, as shown in FIG. 7A, after the insulating layer 39 is selectively formed in the region except the JFET formation region, the entire surface is formed by, for example, the CVD method. A polycrystalline silicon layer containing a p-type impurity is formed and patterned to form a source (drain) extraction electrode of the JFET 10.
(41-2) is formed.

Next, as shown in FIG. 6B, after an insulating layer 42 made of a silicon oxide film or the like is formed on the entire surface,
The insulating layer 42 and the polycrystalline silicon layer 41-1 are formed in the central portion of the JFET formation region (region to be the channel region 37).
An opening 43 which penetrates (41-2) and reaches the single crystal silicon semiconductor layer 32 is formed. The opening 43 is formed by the same method as described in the above embodiment (FIG. 4B).

Next, as shown in FIG.
3, p-type impurities such as BF ₂ ⁺ or B ⁺ are ion-implanted in the vicinity of the surface of the single crystal silicon semiconductor layer 32. Ion implantation conditions at this time are the same as those in the above embodiment (see FIG.
It is the same as described in (a)). When the n-type impurity region 40 as the back gate is provided, P, A
An n-type impurity such as s or Sb is added to a deep portion (n ⁺ buried region 33 and channel region 3) of the single crystal silicon semiconductor layer 32.
(Region between 7) is ion-implanted.

Then, similarly as shown in FIG. 8A, heat treatment is performed to activate the ion-implanted p-type impurities to form the p-type channel region 37, and at the same time, the polycrystalline silicon layer 41- The p-type impurities in 1, 41-2 are thermally diffused into the single crystal silicon semiconductor layer 32 to form p ⁺ diffusion regions 36-1 and 36-2 serving as a source and a drain. Also, the n-type impurity region 40 that connects the n ⁺ buried region 33 and the channel region 37 by activating the n-type impurity ion-implanted for forming the back gate is formed.
Is formed.

Next, as shown in FIG. 5B, after forming the sidewall 44 on the inner side surface of the opening 43 in the same manner as described in the above embodiment (FIG. 5), As or P is formed. Second-layer polycrystalline silicon layer 4 containing n-type impurities such as
6 is formed on the entire surface or a polycrystalline silicon layer containing no impurities is formed, and then n-type impurities such as As or P are ion-implanted into the polycrystalline silicon layer, and this is heat-treated to produce n in the polycrystalline silicon layer 46. The type impurities are thermally diffused into the channel region 37 to form an n-type gate region 38.

Next, as shown in FIG. 9A, JFE
The polycrystalline silicon layer 46-1 to be the gate extraction electrode in the T formation region and the resistance element 2 on the insulating layer 42
The polycrystalline silicon layer 46 is patterned so that the polycrystalline silicon layer 46-2 which becomes 0 is left. At that time, it is possible to give an arbitrary resistance value to the polycrystalline silicon layer 46-2 by selecting the impurity concentration of the polycrystalline silicon layer 46-2, the aspect ratio of the pattern, and the like. Note that the impurity concentrations of the polycrystalline silicon layer 46-1 and the polycrystalline silicon layer 46-2 do not necessarily have to be the same, and may be different as necessary. However, in that case, the impurity introducing step has two steps. Then, as shown in FIG. 9B, an insulating layer made of a silicon oxide film is formed on the insulating layer 42 and the polycrystalline silicon layers 46-1 and 46-2 formed thereon by, for example, the CVD method. Form 60.

Next, as shown in FIGS. 6A and 6B, the contact hole 148-which penetrates the insulating layers 42 and 60 and reaches the polycrystalline silicon layers 41-1 and 41-2.
1, 148-2 and contact holes 148-3, 1 penetrating the insulating layer 60 and reaching the polycrystalline silicon layer 46-2.
48-4 and a contact hole 148-5 penetrating the insulating layers 42 and 60 to reach the n ⁺ -type electrode lead-out region 51.
And are formed.

Subsequently, as shown in FIGS. 6A and 6B, A is formed by covering the above contact holes.
1, a metal wiring layer made of Al-Si or Al-Si-Cu is formed and patterned to form a metal wiring layer 4
9-1 to 49-4 are formed. At this time, the metal wiring layer 4
9-1 connects the polycrystalline silicon layer 41-1 (source of the JFET 10) and one end of the polycrystalline silicon layer 46-2 (resistive element 20) through the contact holes 148-1 and 148-4. These are patterned so as to be connected to a signal source or a power source not shown, and the metal wiring layer 49-2 has a contact hole 148-.
2, 148-3, the polycrystalline silicon layer 41-2 (J
Drain of FET 10) and polycrystalline silicon layer 46-2
The (resistive element 20) is patterned so as to be connected to the other end thereof and to be connected to a ground or a power source (not shown). As a result, the resistance element 20 becomes a JFET.
10 sources and drains are connected in parallel. The metal wiring layer 49-3 is formed by the contact hole 148-5.
^A metal wiring layer 49-4 is formed by patterning so as to connect the ⁺ type electrode lead-out region 51 and a power source (not shown).
Is patterned so as to connect between the polycrystalline silicon layer 46 and a power source (not shown). Then, a protective film (passivation film) or the like (not shown) is formed so as to cover the above structure.

From the above, the source region (p ⁺ diffusion region 3
6-1), the JFET 10 including the drain region (p ⁺ diffusion region 36-2) and the gate region 38, and the resistance element 20 including the second-layer polycrystalline silicon layer 46-2 are formed to form a p-channel JFET. A semiconductor device as a variable resistance element obtained by connecting a resistance element in parallel can be obtained.

In the above two embodiments, the case where the resistance element 20 connected in parallel between the source and drain of the p-channel JFET is composed of a polycrystalline silicon resistance element containing p-type impurities has been described. The present invention is not limited to this, and a polycrystalline silicon resistance element containing an n-type impurity or a diffusion resistance obtained by diffusing an impurity in a single crystal can be used.

In the embodiment shown in FIG. 1, the case where the resistance element 20 is connected between the source and drain of one JFET 10 to form the variable resistance element has been described. For example, as shown in FIG. And two JFETs 10
It is also possible to configure the variable resistance element by connecting the sources and drains of the -1, JFETs 10-2 in parallel with each other and connecting the resistance element 20 in parallel between the sources and drains. In this case, JFET10-1, JFET10
If the channel resistance values between the source and the drain when R− ₂ is on are R ₁ and R ₂ , respectively, and the resistance value of the resistance element 20 is R ₃ , then four-step variable resistance values can be realized as follows. it can.

That is, first, JFET 10-1, JF
When both ET10-2 are turned on, R ₁ ,
Since R ₂ and R ₃ are connected in parallel, the combined resistance value R becomes a value represented by the following equation (4). R = (R ₁ × R ₂ × R ₃ ) / (R ₁ × R ₂ + R ₂ × R ₃ + R ₃ × R ₁ ) ... (4)

Further, the JFET 10-1 is turned on, JF
When the ET 10-2 is turned off, R ₁ and R ₃ are connected in parallel, and the combined resistance value R is a value represented by the following equation (5). R = (R ₁ × R ₃ ) / (R ₁ + R ₃ ) ... (5)

Further, the JFET 10-1 is turned off,
When 10-2 is turned on, R ₂ and R ₃ are connected in parallel, and the combined resistance value R is a value represented by the following equation (6). R = (R ₂ × R ₃ ) / (R ₂ + R ₃ ) ... (6)

Furthermore, JFET10-1, JFET10
When both -2 are in the off state, the combined resistance value R becomes a value represented by the following equation (7) because it is almost equal to the state of only R ₃ . R≈R ₃ (7)

Similarly, by connecting three JFETs and one resistance element in parallel, it is possible to realize a variable resistance element of 2 ³ = 8 stages from the combination of ON / OFF of each JFET. Therefore, in general, by connecting n JFETs and one resistance element in parallel, it is possible to realize a variable resistance element of 2 ⁿ stages.

The present invention has been described above with reference to the embodiments, but the present invention is not limited to the above embodiments, and various modifications can be made within the equivalent range. For example, in each of the above embodiments, the junction field effect transistor (JFET) has been described as an example, but the present invention is not limited to this, and another type of field effect transistor, for example, a MOS (Metal). It is also possible to use a -Oxide-Semiconductor) type or MES (Metal-Semiconductor) type. However, when the variable resistance element and the bipolar transistor of the present invention are mounted together on one semiconductor chip, many manufacturing steps are duplicated and the JFET is used because the number of manufacturing steps as a whole can be reduced. Is advantageous.

[0062]

As described above, according to the semiconductor device of the present invention, a resistance value higher than the channel resistance value between the source and drain when the field effect transistor is on is provided between the source and drain of the field effect transistor. Since the variable resistance element is configured by connecting the resistance elements that it has, when the field effect transistor is on, the combined resistance value due to the parallel connection of the resistance value of the resistance element and the channel resistance value of the field effect transistor is variable resistance. The resistance value of the element is a constant low resistance value, and when the field effect transistor is off, the resistance value of the resistance element is a resistance value of the variable resistance element and a constant high resistance value. That is, this semiconductor device exhibits a constant low resistance value or a constant high resistance value depending on the ON / OFF state of the field effect transistor, and has no dependence on the source-drain bias voltage. Therefore, in various fields of application, the distortion of the output signal waveform with respect to the input signal waveform is eliminated, and high-quality signal processing and the like can be performed.

Further, according to the method of manufacturing a semiconductor device of the present invention, a layer to be a resistance element is simultaneously formed in the step of forming the source / drain lead-out electrodes, and
According to another method for manufacturing a semiconductor device, the layer serving as the resistance element is formed at the same time in the step of forming the gate extraction electrode, so that the above steps can be performed without adding a new step or by adding a minimum number of steps. A variable resistance element having characteristics can be manufactured.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a circuit configuration of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a diagram showing characteristics as a variable resistance element of the semiconductor device shown in FIG.

3A and 3B are a cross-sectional view and a plan view showing an element structure of the semiconductor device of FIG.

FIG. 4 is a cross-sectional view showing a step in the method of manufacturing the semiconductor device of FIG.

FIG. 5 is a cross-sectional view illustrating a process following the process in FIG.

FIG. 6 is a cross-sectional view and a plan view showing an element structure of a semiconductor device according to another embodiment of the present invention.

FIG. 7 is a cross-sectional view showing a step in the method of manufacturing the semiconductor device of FIG.

8 is a cross-sectional view illustrating a process following the process in FIG.

FIG. 9 is a sectional view illustrating a step following FIG. 8;

FIG. 10 is a circuit diagram showing a circuit configuration of a semiconductor device according to still another embodiment of the present invention.

FIG. 11 is a diagram showing a general field effect transistor.

12 is a diagram showing characteristics of a conventional variable resistance element configured by using the field effect transistor of FIG.

[Explanation of symbols]

10, 10-1, 10-2 ... JFET, 20 ... Resistance element, 31 ... Silicon substrate, 32 ... Single crystal silicon semiconductor layer, 33 ... N ⁺ buried region, 34-1, 34-2 ... Element isolation region, 35 -1,35-2 ... p ⁺ region, 36-1
... p ⁺ diffusion region (source region), 36-2 ... p ⁺ diffusion region (drain region), 37 ... channel region, 38 ... gate region, 39, 42, 60 ... insulating layer, 40 ... n-type impurity region (back) Gate), 41-1 ... First-layer polycrystalline silicon layer (source extraction electrode), 41-2 ... First-layer polycrystalline silicon layer (drain extraction electrode), 41-3 ... First-layer polycrystalline silicon layer (resistor) Element), 46, 46-1 ... 2
Polycrystalline silicon layer (gate extraction electrode), 46-
2 ... Second layer polycrystalline silicon layer (resistive element), 48-1 to 48-1
48-5 ... Contact hole, 49-1 to 49-4 ... Metal wiring layer, 51 ... N ⁺ type electrode extraction region

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code Agency reference number FI Technical display location H01L 29/808

Claims (8)

[Claims] 1. A field effect transistor in which a channel resistance value between a source and a drain changes according to a bias voltage applied to a gate, and a channel resistance between the source and the drain when the field effect transistor is on. Has a higher resistance value than
A semiconductor device comprising: a resistance element connected between a source and a drain of the field effect transistor. 2. The semiconductor device according to claim 1, wherein the field effect transistor is a junction field effect transistor. 3. The semiconductor device according to claim 1, wherein the field effect transistor is a MOS field effect transistor or a MES field effect transistor. 4. The semiconductor device according to claim 1, wherein the resistance element is formed mainly of polycrystalline silicon. 5. A field effect transistor in which a channel resistance value between a source and a drain changes according to a bias voltage applied to a gate, and a channel resistance between the source and the drain when the field effect transistor is turned on. A method of manufacturing a semiconductor device having a resistance value higher than a value, comprising a resistance element connected between a source and a drain of the field effect transistor, wherein a layer serving as a takeout electrode for the source and the drain is provided. A method of manufacturing a semiconductor device, wherein the layer to be the resistance element is formed in the same step. 6. A field effect transistor in which a channel resistance value between a source and a drain changes according to a bias voltage applied to a gate, and a channel resistance between the source and the drain when the field effect transistor is turned on. A method of manufacturing a semiconductor device having a resistance value higher than a value, the resistance element being connected between a source and a drain of the field effect transistor, wherein a layer serving as an extraction electrode of the gate and the resistance are provided. A method of manufacturing a semiconductor device, which comprises forming a layer to be an element in the same step. 7. The method for manufacturing a semiconductor device according to claim 5, wherein the field effect transistor is a junction field effect transistor. 8. The method of manufacturing a semiconductor device according to claim 6, wherein the field effect transistor is a junction field effect transistor.