JPH09232285A - Plasma etching method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a plasma etching method which prevents a seam from being expanded and an etched-back surface from being roughened by a method wherein the temperature of a silicon material is controlled to room temperature or lower and the surface of the silicon material layer is etched back while a sulfur-based material layer is being deposited. SOLUTION: A substrate to be etched is set on a substrate stage at a substrate bias application-type ECR plasma etching apparatus. Then, a polycrystalline silicon layer 103 is etched back. In this etching-back process, free surfur which is generated in a plasma due to the dissociation of S2 F2 is deposited on the polycrystalline silicon layer 103 which is controlled to a low temperature, and a surfur-based material layer 104 is formed. Then, while a recessed part is buried so as to flatten the surface, an etching operation progresses. As a result, the polycrystalline silicon layer 103 whose surface is smooth is formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma etching method applied in the field of manufacturing semiconductor devices and the like. More specifically, it is used for etching back while smoothing the surface of a silicon material layer such as polycrystalline silicon. The present invention relates to a suitable plasma etching method.

[0002]

2. Description of the Related Art With the progress of higher integration and higher performance of semiconductor devices such as LSI, the area occupied by wiring portions on a semiconductor chip, that is, the proportion of wiring regions tends to increase. In order to avoid an increase in the semiconductor chip area due to this, interlayer connection by multilayer wiring and contact plugs is an essential process. Conventionally, as a method of forming electrodes and wirings, a method of forming a conductive material such as Al or an Al alloy by sputtering has been widely used.
However, in the situation where the multilayer wiring has progressed as described above, and as a result, the surface step of the semiconductor substrate and the aspect ratio of the connection hole are increasing remarkably, the method including the method using a collimator is also used. In the conventional method, poor connection and disconnection due to insufficient step coverage have become serious problems.

In view of such circumstances, a method of applying a CVD method excellent in step coverage to the formation of a conductive material is adopted. In forming the conductive material by these CVD methods, the most general method is to form a conductive material layer such as polycrystalline silicon or blanket tungsten on the entire surface of the substrate to be processed including the contact holes by the CVD method, and then etch back the entire surface. This is a method of leaving the inside of the connection hole. In this case, in addition to leaving the conductive material as a contact plug only in the connection hole, there is also a method in which the conductive material is left on the interlayer insulating film and further patterned to be used as a wiring material.

[0004]

In any of the methods, the problem of etching back the conductive material layer deposited by the CVD method is the expansion of the seam. This is a phenomenon in which etching locally progresses along the joint or joint of the growth of the conductive material layer that appears in the vicinity of the central portion of the connection hole, and an undesired groove is formed.
It has been considered that it cannot be prevented to some extent. When blanket tungsten is used as the conductive material, CV
The problem of seams has been considerably improved by means such as controlling the D condition to change the crystal orientation, but no significant improvement has been observed for polycrystalline silicon.

Further, in polycrystalline silicon, since crystal grains grow by a heat treatment in a post process after film formation, remarkable irregularities may occur on the surface. Therefore, the exposure accuracy of the resist at the time of patterning the wiring is deteriorated and the flatness of the interlayer insulating film is deteriorated. Further, when it is used as a capacitor electrode in a DRAM or the like, undesired irregularities are generated on the surface of the electrode, so that the capacitance value fluctuates and the reliability of the semiconductor device decreases.

These problems will be described in more detail with reference to FIGS. 7 and 8. FIG. 8 is a schematic sectional view of a stacked contact portion in the multilayer wiring structure. In this conventional example, a seam 116 enlarged by etching back is formed in the central portion of a contact plug 103a made of polycrystalline silicon formed by CVD and etching back.
Are formed. Therefore, in the barrier layer 106 formed by sputtering, the barrier layer lack 106a occurs at this portion. After this, Al-based metal wiring 10
When No. 7 is formed, the Al-based metal wiring 107 comes into contact with the contact plug 103a made of polycrystalline silicon to cause an alloying reaction, and in the worst case, the Al spike 117 is generated.

On the other hand, FIG. 8 is a schematic sectional view showing a part of the manufacturing process of the cylinder type capacitor electrode. In the figure, after forming a capacitor hole 118 in the upper insulating film 112, a polycrystalline silicon layer is formed on the entire surface by a CVD method, and an oxide film 114 is further formed on the entire surface by a CVD method and then etched back to form the center of the capacitor hole 118. Part of the capacitor electrode 113a by etching back the polycrystalline silicon layer.
Shows a state in which is formed. As shown in the figure, the surface of the capacitor electrode 113a has uneven unevenness, which changes the capacitance value of the capacitor.

The present invention proposes a plasma etching method which does not cause the expansion of seams and the roughening of the etched back surface in the etching back of the silicon material layer including the above-mentioned polycrystalline silicon, and the reliability is improved. It is an object of the present invention to provide an excellent semiconductor device.

[0009]

The plasma etching method of the present invention was devised to achieve the above-mentioned object, and is a plasma etching method for etching back a silicon material layer. It is characterized in that the temperature of the layer is controlled to room temperature or lower, and the sulfur-based material layer is etched back while being deposited on the surface of the silicon material layer. As a method of depositing the sulfur-based material layer, an etching gas containing a gas capable of releasing free sulfur into plasma is adopted under discharge dissociation conditions, or at least a part of the inner wall of the etching chamber is a wall containing sulfur. Either a plasma etching apparatus coated with a material and a method of sputtering the wall material containing sulfur can be adopted.

The silicon material layer targeted by the plasma etching method of the present invention is any one of single crystal silicon, polycrystalline silicon and amorphous silicon.
It may or may not contain impurities. Further, the sulfur-based material layer in the plasma etching method of the present invention,
It is any one of sulfur and polythiazil. Further, under the discharge dissociation conditions adopted in the present invention, a gas capable of releasing free sulfur into plasma is S ₂ F ₂ (m
p = −133 ° C., bp = 15 ° C.), SF ₂ (gas at room temperature), SF ₄ (mp = −121 ° C., bp = −38 ° C.),
S ₂ F ₁₀ (mp = −52.7 ° C., bp = 30 ° C.), S ₃
Cl ₂ (mp = −46 ° C.), S ₂ Cl ₂ (mp = −80
° C, bp = 137.1 ° C), SCl ₂ (mp = -122)
° C, bp = 59.6 ° C), S ₃ Br ₂ (mp = -46
C), S ₂ Br ₂ , SBr ₂ (both liquid at room temperature), X, etc.
At least any one of halogenated sulfur compounds having a / S ratio (X represents a halogen atom) of less than 6 and H ₂ S can be exemplified. Note that SF ₆ which is widely used as a sulfur fluoride-based gas has an F / S ratio of 6, and it is difficult to generate free sulfur that is generated in plasma under discharge dissociation conditions. Excludes gases that can release free sulfur into the plasma under discharge dissociation conditions as defined in the text.

Next, the operation will be described. The technical idea of the present invention is to etch back a silicon material layer,
By competing the deposition reaction of the sulfur-based material layer and filling the surface irregularities with the sulfur-based material layer and etching back while forming a flat surface, the final smoothing of the surface of the silicon material layer is achieved. To do. Sulfur or polythiazyl is a sublimable material, but it is deposited here when the temperature of the substrate to be etched is controlled to room temperature, that is, below the normal clean room temperature of 20 ° C. or lower. These sulfur-based materials are promptly removed by sputtering on the convex portions of the substrate to be etched and preferentially deposited on the concave portions, so that a smooth surface is obtained. In this state, a smooth silicon material layer surface is obtained by etching back under the condition of a selection ratio of about 1: 1. Elemental sulfur is deposited by using a gas capable of releasing free sulfur in the plasma described above, and if N-based gas such as N ₂ , NF ₃ , N ₂ H ₄ and its derivative is mixed with this, it is nitrided. Sulfur polymer (SN) _n or polythiazyl is deposited. When the sulfur-based material layer remains on the substrate to be etched after the etching back is finished, these substances are sublimated and removed by heating the substrate to be etched, and contamination or particle contamination does not occur. The sulfur-based material layer can also be removed by ashing. The sublimation temperature is about 90 ° C. or higher for sulfur in a reduced pressure atmosphere, and about 150 ° C. or higher for polythiazil.

The plasma etching apparatus used in the plasma etching method of the present invention is a conventional parallel plate type RI.
The E apparatus may be used, but in order to uniformly process a large-diameter substrate, it is desirable to adopt an apparatus capable of low-pressure operation and generation of high-density plasma. Further, in order to uniformly control the substrate to be etched below room temperature, it is necessary to adhere the substrate to be etched to a cooled substrate stage and perform etch back in a good heat conduction state. For this purpose, an electrostatic chuck, It is preferable to use a device having a monopolar electrostatic chuck, but a mechanical wafer clamp may be used.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Specific embodiments of the present invention will be described below with reference to the drawings. In the following drawings, the same components as those in FIGS. 7 and 8 referred to in the description of the conventional example are designated by the same reference numerals. In addition, the substrate stage of the plasma etching apparatus used in the following examples has a cooling means capable of controlling the substrate to be etched below room temperature, in which a coolant such as Fluorinert (trade name) or ethanol circulates, and the substrate can be heated. It has a built-in heater and, if necessary, an electrostatic chuck.

Embodiment 1 This embodiment is an example in which the present invention is applied to a step of forming a polycrystalline silicon wiring, which will be described with reference to FIG.

The substrate to be etched used in this embodiment is
As shown in FIG. 1A, a semiconductor substrate 101 made of silicon or the like is used.
An interlayer insulating film 102 made of SiO ₂ or the like is formed thereon to a thickness of 300 nm by atmospheric pressure CVD or the like, and a polycrystalline silicon layer 103 is formed thereon to a thickness of 300 nm by a low pressure CVD method, for example. As shown in the figure, the polycrystalline silicon layer 103 has heat treatment after deposition, so that irregularities are formed on its surface.

The substrate to be etched shown in FIG. 1A is set on the substrate stage of a substrate bias application type ECR plasma etching apparatus, and as an example, the polycrystalline silicon layer 103 is etched back under the following conditions. Cl ₂ 50 sccm S ₂ F ₂ 20 sccm Gas pressure 1.0 Pa Microwave power 1200 W (2.45 GHz) RF bias power 100 W (2 MHz) Etching substrate temperature −20 ° C. Etching amount 100 nm In this etch back process The free sulfur generated in the plasma due to the dissociation of S ₂ F ₂ is deposited on the polycrystalline silicon layer 103 controlled to a low temperature to form the sulfur-based material layer 104 as shown in FIG. 1B. Then, the etching progresses while filling the recesses and flattening the surface.

As a result, as shown in FIG. 1C, a polycrystalline silicon layer 1 having a smooth surface and a thickness of 200 nm is formed.
03 was formed. Thereafter, the substrate to be etched is heated to, for example, 100 ° C., whereby the sulfur-based material layer 104 remaining on the substrate to be etched is completely sublimated and removed. The sulfur-based material layer 104 may be removed by ashing. As a subsequent step, after forming a resist mask (not shown) on the smooth polycrystalline silicon layer 103, the polycrystalline silicon wiring is patterned using this as a mask. During resist exposure, there was no influence of irregular reflection or light scattering from the polycrystalline silicon layer 103, and highly accurate resist patterning was possible.

Embodiment 2 This embodiment is also an example in which the present invention is applied to the step of forming polycrystalline silicon wiring, which will be described with reference to FIG.

Since the substrate to be etched shown in FIG. 1A used in this embodiment is the same as that in the previous embodiment, duplicated description will be omitted. This substrate to be etched was set on the substrate stage of a substrate bias application type ECR plasma etching apparatus, and as an example, the polycrystalline silicon layer 1 was formed under the following conditions.
03 etch back. Cl ₂ 50 sccm S ₂ F ₂ 20 sccm H ₂ 30 sccm Gas pressure 1.0 Pa Microwave power 1200 W (2.45 GHz) RF bias power 100 W (2 MHz) Etching substrate temperature 10 ° C. Etching amount 100 nm This etch In the back step, the addition of H ₂ promotes the generation of free sulfur in the plasma due to the dissociation of S ₂ F ₂ , and the temperature of the substrate to be etched is higher by about 30 ° C. as compared with Example 1. As shown in FIG. 1 (b), the sulfur-based material layer 104 is formed by depositing on the polycrystalline silicon layer 103, and the recesses are filled in to flatten the surface to perform etching.

As a result, as shown in FIG. 1C, the polycrystalline silicon layer 1 having a smooth surface and a thickness of 200 nm is formed.
03 was formed. Since the subsequent steps are the same as those in the first embodiment, the duplicate description will be omitted. According to the present embodiment,
More practical etchback is possible at process temperatures close to room temperature.

Third Embodiment This embodiment is also an example in which the present invention is applied to the step of forming a polycrystalline silicon wiring, which will be described with reference to FIG.

Since the substrate to be etched shown in FIG. 1 (a) used in this embodiment is the same as that in the previous embodiment, duplicate description will be omitted. This substrate to be etched was set on the substrate stage of a substrate bias application type ECR plasma etching apparatus, and as an example, the polycrystalline silicon layer 1 was formed under the following conditions.
03 etch back. Cl ₂ 50 sccm S ₂ F ₂ 20 sccm N ₂ 30 sccm Gas pressure 1.0 Pa Microwave power 1200 W (2.45 GHz) RF bias power 100 W (2 MHz) Etching substrate temperature 10 ° C. Etching amount 100 nm This etch In the back step, the sulfur generated in the plasma due to the dissociation of S ₂ F ₂ due to the addition of N ₂ immediately becomes thiazyl (SN). This polymerizes easily in the gas phase to form polythiazyl (SN) _n , which is shown in FIG.
As shown in (b), the sulfur-based material layer 104 is formed by depositing on the polycrystalline silicon layer 103, the recesses are filled in, and the surface is flattened to perform etching.

As a result, as shown in FIG. 1C, the polycrystalline silicon layer 1 having a smooth surface and a thickness of 200 nm is formed.
03 was formed. After that, by heating the substrate to be etched to 170 ° C., for example, the sulfur-based material layer 104 made of polythiazyl remaining on the substrate to be etched is completely sublimated and removed. The sulfur-based material layer 104 may be removed by ashing. The subsequent steps are the same as those in the first embodiment.
Since it is the same as the above, duplicate description will be omitted. According to this example, by using the deposition of polythiazyl having a high sublimation temperature as the planarizing material layer, more practical etchback can be performed at a process temperature close to room temperature.

Embodiment 4 This embodiment is an example in which the present invention is applied to the formation of a contact plug using polycrystalline silicon, which will be described with reference to FIGS. 2 and 3. The substrate to be etched used in this embodiment is, as shown in FIG. 2A, an interlayer insulating film 10 made of SiO ₂ or the like on a semiconductor substrate 101 made of silicon or the like.
2 is formed to a thickness of 1100 nm by atmospheric pressure CVD or the like, a connection hole 105 having a diameter of 0.3 μm is formed therein, and a polycrystalline silicon layer 103 is further formed on the entire surface to a thickness of 500 nm by a low pressure CVD method. It was formed. In the polycrystalline silicon layer 103, a seam 116 is formed at the center of the connection hole 105 by a seam of growth as shown in the figure.

The substrate to be etched shown in FIG.
The polycrystalline silicon layer 103 is set on the substrate stage of a CR type plasma etching apparatus, and as an example, the polycrystalline silicon layer 103 is etched back under the following conditions. The MCR type plasma etching apparatus will be described later. S ₂ Cl ₂ 50 sccm Ar 20 sccm Gas pressure 1.0 Pa Sidewall electrode power supply power 1000 W (13.56 MHz) RF bias power 20 W (450 kHz) Etching substrate temperature −20 ° C. Overetching 5% In this etchback process Is the free sulfur generated in the plasma due to the dissociation of S ₂ Cl ₂ , as shown in FIG.
The polycrystalline silicon layer 103 controlled to a low temperature as shown in FIG.
The sulfur-based material layer 104 is formed by depositing it on the upper surface, and the recesses such as seams are filled in to flatten the surface and etching proceeds.

As a result, as shown in FIG. 3 (c), the contact plug 103a having a smooth surface was formed without the seam expanding unlike the conventional example. Thereafter, the substrate to be etched is heated to, for example, 100 ° C., whereby the sulfur-based material layer 104 remaining on the substrate to be etched is completely sublimated and removed. Sulfur-based material layer 10
The removal of 4 may be performed by ashing.

In the subsequent step, as shown in FIG. 3D, a barrier layer 106 made of Ti / TiN, an Al type metal layer 107 and an antireflection layer 108 made of TiN are formed by sputtering and then patterned to form an upper layer. After forming the wiring and forming the upper interlayer insulating film 122, the connection hole 115 is opened on the contact plug 103a to obtain a stacked contact structure. In this embodiment, since a contact plug having a good shape with no seam expansion was obtained, it is possible to obtain a highly reliable semiconductor device free from defects such as Al spikes.

Example 5 In this example, an example in which the present invention is applied to the formation of a capacitor using polycrystalline silicon as an electrode will be described with reference to FIG. The substrate to be etched used in this example is shown in FIG.
As shown in (a), after the contact plug 103a made of polycrystalline silicon is formed in the connection hole by opening in the interlayer insulating film 102 by the same process as in the fourth embodiment, S
The insulating film 112 made of io ₂ is 600 n by the atmospheric pressure CVD method.
After depositing a capacitor hole 118, a polycrystalline silicon layer 113 is deposited on the entire surface by low pressure CVD to a thickness of 50 nm, and the oxide film 1 is formed in the central portion of the capacitor hole 118.
14 is left by etching back. Oxide film 1
Reference numeral 14 is a mask for protecting the surface of the polycrystalline silicon layer 113 in the capacitor hole 118 from etching back in a later step.

The substrate to be etched was etched back to the interface of the insulating film 112 by using the helicon wave plasma etching apparatus under the following conditions as an example. Cl ₂ 50 sccm S ₂ Br ₂ 30 sccm N ₂ 30 sccm Gas pressure 1.0 Pa Helicon wave power source power 1500 W (13.56 MHz) RF bias power 250 W (400 kHz) Etching substrate temperature −20 ° C. Over etching 20% In this etch back step, as shown in FIG. 4B, the sulfur-based material layer 104 made of polythiazil is deposited on the surface of the polycrystalline silicon layer 113 having an uneven surface, and the etching progresses while filling the unevenness of the surface.

As a result, a capacitor electrode 113a having a smooth surface was formed as shown in FIG. 4 (c). Thereafter, the substrate to be etched was heated to 150 ° C. or higher or subjected to an ashing treatment, whereby the sulfur-based material layer remaining on the surface of the substrate to be etched was completely removed. In the next step, although not shown, the oxide film 114 and the insulating film 11 are omitted.
2 is removed by wet etching with diluted hydrofluoric acid or the like to obtain a ring-shaped capacitor electrode 113a. According to the present embodiment, it is possible to form a highly reliable polycrystalline silicon capacitor electrode without capacitance fluctuation due to the effect of smoothing etch back.

Example 6 In Examples 6 to 10 shown below, a plasma etching apparatus in which at least a part of the inner wall of the etching chamber is covered with a wall material containing sulfur, and the wall material containing sulfur is sputtered. This is an example of etching back while depositing a sulfur-based material layer on the substrate to be etched.

The plasma etching apparatus shown in FIG. 5 employed in this embodiment has a basic structure of a substrate bias application type E.
It is a CR plasma etching device. That is, the substrate to be etched 1 is held in close contact with the substrate stage 2 having the cooling means and the heating means by the clamp 3. An RF bias power source 4 is connected to the substrate stage 2. Clamp 3
May be replaced with an electrostatic chuck. On the other hand, the microwave generated by the magnetron 5 is introduced into the bell jar 7 made of a dielectric material such as quartz or alumina via the microwave waveguide 6, and interacts with the magnetic field of 0.0875T by the solenoid coil 8. To generate ECR plasma. The feature of the present plasma etching apparatus is the wall material 9 containing sulfur provided on the inner wall of the chamber and the shutter 10 for controlling the exposed surface area of the wall material 9 containing sulfur. Wall material 9 containing the sulfur was adopted as a SiS ₂ and Ar plasma spraying. The surface of the clamp 3 may be coated with a material containing sulfur. According to this plasma etching apparatus,
When the shutter opening is 100%, that is, when the wall material 9 containing sulfur is almost exposed, the wall material 9 containing sulfur is sputtered by the plasma and the sulfur-based material is supplied into the plasma. If the shutter opening is 0%, all the wall material 9 containing sulfur is shielded from the plasma, and a normal substrate bias application type ECR plasma etching apparatus is obtained. By setting the shutter opening between 0% and 100%, it is possible to arbitrarily control the supply amount of the sulfur-based material layer into the plasma. In FIG. 5, details of the device such as the driving means of the shutter 10 and the gas introduction hole are omitted.

The plasma etching method according to the present embodiment is an example in which the present invention is applied to the step of forming polycrystalline silicon wiring, which will be described again with reference to FIG.

Since the substrate to be etched shown in FIG. 1A used in this embodiment is the same as that in the first embodiment, duplicate description will be omitted. This substrate to be etched is set on the substrate stage of the substrate bias application type ECR plasma etching apparatus shown in FIG. 5, and as an example, the polycrystalline silicon layer 103 is etched back under the following conditions. SF ₆ 20 sccm Ar 100 sccm Gas pressure 1.0 Pa Microwave power 1200 W (2.45 GHz) RF bias power 100 W (2 MHz) Etching substrate temperature −30 ° C. Etching amount 100 nm Shutter opening 100% This etch back In the process, the wall material 1 containing sulfur
9 is exposed to plasma and is sputtered, and a sulfur-based material is supplied into the plasma. When the surface of the clamp 3 is also coated with the sulfur-based material, the sulfur-based material is also supplied from here. These sulfur-based materials are deposited on the polycrystalline silicon layer 103 controlled at a low temperature to form the sulfur-based material layer 104, and the recesses are filled in to flatten the surface to perform etching. Needless to say, SF ₆ is an etchant supply source, not a sulfur-based material supply source.

As a result, as shown in FIG. 1C, the polycrystalline silicon layer 1 having a smooth surface and a thickness of 200 nm is formed.
03 was formed. Thereafter, the substrate to be etched is heated to, for example, 100 ° C., whereby the sulfur-based material layer 104 remaining on the substrate to be etched is completely sublimated and removed. The sulfur-based material layer 104 may be removed by ashing. As a subsequent step, after forming a resist mask (not shown) on the smooth polycrystalline silicon layer 103, the polycrystalline silicon wiring is patterned using this as a mask. During resist exposure, there was no influence of irregular reflection or light scattering from the polycrystalline silicon layer 103, and highly accurate patterning was possible.

Embodiment 7 This embodiment is an example in which polycrystalline silicon wiring is formed by controlling the shutter opening with the same substrate bias application type ECR plasma etching apparatus as in the previous embodiment. Since the substrate to be etched shown in FIG. 1A used in this embodiment is the same as that in the first embodiment, duplicate description will be omitted. This substrate to be etched is a substrate bias application type EC shown in FIG.
The polycrystalline silicon layer 103 is set on the substrate stage of the R plasma etching apparatus, and as an example, the polycrystalline silicon layer 103 is etched back under the following conditions. Cl ₂ 20 sccm Gas pressure 1.0 Pa Microwave power 1200 W (2.45 GHz) RF bias power 100 W (2 MHz) Etching substrate temperature −20 ° C. Etching amount 100 nm Shutter opening 80% In this etch back process , Wall material containing sulfur 1
9 is exposed to plasma and is sputtered, and a sulfur-based material is supplied into the plasma. When the surface of the clamp 3 is also coated with the sulfur-based material, the sulfur-based material is supplied into the plasma also from here. These sulfur-based materials are deposited on the polycrystalline silicon layer 103 controlled at a low temperature to form a sulfur-based material layer 104 mainly composed of sulfur, and the recesses are filled in to flatten the surface to perform etching. In particular, in this embodiment, since the etching back is performed with Cl ₂ gas alone, the etching due to the radical component is suppressed. As a result, smoothing etch-back can be performed under the condition that the shutter opening is reduced and the substrate temperature to be etched is increased, that is, the deposition of the sulfur-based material layer 104 is small as compared with the sixth embodiment.

As a result, as shown in FIG. 1C, the polycrystalline silicon layer 1 having a smooth surface and a thickness of 200 nm is formed.
03 was formed. Thereafter, the substrate to be etched is heated to, for example, 100 ° C., whereby the sulfur-based material layer 104 remaining on the substrate to be etched is completely sublimated and removed. The sulfur-based material layer 104 may be removed by ashing. As a subsequent step, after forming a resist mask (not shown) on the smooth polycrystalline silicon layer 103, the polycrystalline silicon wiring is patterned using this as a mask. During resist exposure, there was no influence of irregular reflection or light scattering from the polycrystalline silicon layer 103, and highly accurate patterning was possible.

Embodiment 8 This embodiment is an example in which the present invention is applied to the formation of contact plugs using polycrystalline silicon. First, the MCR (Magnetically Confin) adopted in this embodiment is used.
An outline of the ed reactor) plasma etching apparatus will be described with reference to FIG. As shown in FIG. 6, the plasma etching apparatus used in this embodiment is basically a normal MCR plasma etching apparatus. That is, the substrate to be etched 1 is held in close contact with the substrate stage 2 having the cooling means and the heating means by the clamp 3. An RF bias power source 4 is connected to the substrate stage 2. The clamp 3 may be replaced with an electrostatic chuck. The chamber side wall is an annular side wall electrode 11, to which a side wall electrode power supply 12 is connected. The chamber top plate serves as a counter electrode 12 having a ground potential. Side wall electrode 11 and counter electrode 12
A multi-pole magnet for confining the plasma is provided in contact with the outside of the chamber, but the illustration is omitted together with the gas introduction hole and the like. The feature of the present plasma etching apparatus is the wall material 9 containing sulfur provided on the inner wall of the chamber and the shutter 10 for controlling the exposed surface area of the wall material 9 containing sulfur. Particularly, in the device of the present embodiment, the wall material 9 containing sulfur is formed on the surface of the side wall electrode 11. Wall material 9 containing the sulfur was adopted as a SiS ₂ and Ar plasma spraying. The surface of the clamp 3 may be coated with these sulfur-based material layers. According to the present plasma etching apparatus, when the shutter opening is 100%, that is, when the wall material 9 containing sulfur is almost completely exposed, the wall material 9 containing sulfur is sputtered by the plasma and the sulfur-based material is supplied into the plasma. If the shutter opening is 0%, all the wall material 9 containing sulfur is shielded from the plasma, and a normal MCR plasma etching apparatus is obtained. By setting the shutter opening between 0% and 100%, it is possible to arbitrarily control the supply amount of the sulfur-based material layer into the plasma. In FIG. 6, details of the device such as the driving means of the shutter 10, the gas introduction hole, and the vacuum pump are omitted.

The plasma etching method according to this embodiment is an example in which the present invention is applied to the step of forming a contact plug made of polycrystalline silicon, which will be described again with reference to FIGS. 2 and 3.

The substrate to be etched shown in FIG. 2 (a) used in this embodiment is the same as that in the previous embodiment 4, and the duplicated description will be omitted. This substrate to be etched is set on the substrate stage of the MCR plasma etching apparatus shown in FIG. 6 and, as an example, the polycrystalline silicon layer 103 is etched back under the following conditions. SF ₆ 30 sccm Ar 100 sccm Gas pressure 1.0 Pa sidewall electrode power: 1000 W (13.56MHz) RF bias power 40 W (450 kHz) to be etched substrate temperature -20 ° C. overetching 5% shutter opening 100% this etch In the back process, the wall material 1 containing sulfur
9 is exposed to plasma and is sputtered, and a sulfur-based material is supplied into the plasma. When the surface of the clamp 3 is also coated with the sulfur-based material, the sulfur-based material is also supplied from here. These sulfur-based materials are deposited on the polycrystalline silicon layer 103 whose temperature is controlled to a low temperature to form a sulfur-based material layer 104 mainly containing sulfur, as shown in FIG.
As shown in FIG. 5, the seam 116 is embedded to planarize the surface and the etching proceeds.

As a result, as shown in FIG. 3C, the contact plug 103a having a smooth surface was formed without the seam expanding unlike the conventional example. Thereafter, the substrate to be etched is heated to, for example, 100 ° C., whereby the sulfur-based material layer 104 remaining on the substrate to be etched is completely sublimated and removed. Sulfur-based material layer 10
The removal of 4 may be performed by ashing.

As a subsequent step, as shown in FIG. 3D, a barrier layer 106 made of Ti / TiN, an Al type metal layer 107 and an antireflection layer 108 made of TiN are formed by sputtering and then patterned to form an upper layer. After forming the wiring and forming the upper interlayer insulating film 122, the connection hole 115 is opened on the contact plug 103a to obtain a stacked contact structure. In this embodiment, since a contact plug having a good shape with no seam expansion was obtained, it is possible to obtain a highly reliable semiconductor device free from defects such as Al spikes.

Embodiment 9 This embodiment is an example in which the present invention is applied to the contact plug forming process using polycrystalline silicon by adopting the MCR plasma etching apparatus as in the case of the previous embodiment 8. 2 and FIG. 3 will be described. The plasma etching apparatus shown in FIG. 6 employed in this example has the same basic configuration as the apparatus described in Example 8 above, but in this Example, the wall material 9 containing sulfur was deposited by plasma CVD. Adopted polythiazil. The other device configuration is the same as that of the device of the eighth embodiment.

The substrate to be etched shown in FIG. 2 (a) used in this embodiment is the same as that described in the fourth embodiment, and the duplicated description will be omitted. This substrate to be etched is set on the substrate stage of the MCR type plasma etching apparatus, and the polycrystalline silicon layer 1 is set under the following conditions as an example.
03 etch back. Cl ₂ 50 sccm Gas pressure 1.0 Pa Side wall power supply power 1500 W (13.56 MHz) RF bias power 250 W (450 kHz) Etching substrate temperature −10 ° C. Shutter opening 100% In this etch back step, plasma was applied. Free polythiazyl which is released into the plasma by sputtering the exposed sulfur-containing wall material 9 is deposited on the polycrystalline silicon layer 103 controlled to a low temperature as shown in FIG. The layer 104 is formed, the recesses such as seams are filled in, and the surface is flattened to perform etching.

As a result, as shown in FIG. 3 (c), the contact plug 103a having a smooth surface was formed without the seam expanding unlike the conventional example. Thereafter, the substrate to be etched is heated to 170 ° C., for example, so that the sulfur-based material layer 104 remaining on the substrate to be etched is completely sublimated and removed. Sulfur-based material layer 10
The removal of 4 may be performed by ashing.

As a subsequent step, as shown in FIG. 3D, a barrier layer 106 made of Ti / TiN, an Al type metal layer 107 and an antireflection layer 108 made of TiN are formed by sputtering and then patterned to form an upper layer. After forming the wiring and forming the upper interlayer insulating film 122, the connection hole 115 is opened on the contact plug 103a to obtain a stacked contact structure. In this embodiment, since a contact plug having a good shape with no seam expansion was obtained, it is possible to obtain a highly reliable semiconductor device free from defects such as Al spikes.

Example 10 In this example, an example in which the present invention is applied to a capacitor forming process using polycrystalline silicon for electrodes will be described with reference to FIGS. 6 and 4. The plasma etching apparatus shown in FIG. 6 used in this embodiment is the same as that described in the previous embodiment 8, and the duplicated description will be omitted. Further, since the substrate to be etched shown in FIG. 4A used in this embodiment is the same as that described in the previous embodiment 5, the duplicated description will be omitted.

This substrate to be etched was etched under the following conditions as an example, and the polycrystalline silicon layer 113 was etched back to the interface of the interlayer insulating film 112. Cl ₂ 30 sccm Ar 100 sccm Gas pressure 1.0 Pa Side wall power supply power 1000 W (13.56 MHz) RF bias power 20 W (450 kHz) Etching substrate temperature −20 ° C. Overetching 5% Shutter opening 100% This etch In the back step, the wall material 9 containing sulfur exposed to the plasma is sputtered and the free sulfur-based material layer released into the plasma is a polycrystal whose temperature is controlled as shown in FIG. 2B. The sulfur-based material layer 104 mainly composed of sulfur is formed by depositing on the silicon layer 103, and the recesses on the surface are filled in and planarized to perform etching.

As a result, as shown in FIG. 4C, the capacitor electrode 113a having a smooth surface was formed without leaving an uneven surface unlike the conventional example. After that, by heating the substrate to be etched to 120 ° C., for example,
The sulfur-based material layer 104 remaining on the substrate to be etched is completely sublimated and removed. The sulfur-based material layer 104 may be removed by ashing. In the next step, although not shown, the oxide film 114 and the insulating film 112 are removed by wet etching with diluted hydrofluoric acid or the like to obtain a ring-shaped capacitor electrode 113a. According to the present embodiment, it is possible to form a highly reliable polycrystalline silicon capacitor electrode without capacitance fluctuation due to the effect of smoothing etch back.

Although the present invention has been described above with reference to ten examples, the present invention is not limited to these examples.

For example, although the polycrystalline silicon layer is illustrated as the silicon material layer in the embodiments, it may be the etching back of the single crystal silicon layer or the amorphous silicon layer. In addition, S ₂ F ₂ , S ₂ Cl ₂ and S ₂ Br ₂ were adopted as typical gases that can release free sulfur into plasma under discharge dissociation conditions. However, as mentioned above, the X / S ratio is less than 6. Various halogenated sulfur compounds can be used. The H ₂ S gas does not generate an etchant by itself, so it is necessary to use it in combination with another halogen-based gas.

As the etching apparatus, a substrate bias application type ECR plasma etching apparatus, an MCR plasma etching apparatus and a helicon wave plasma etching apparatus have been exemplified, but an inductive coupling type plasma etching apparatus and
More general parallel plate type RIE device and magnetron R
It may be an IE device.

Further, it goes without saying that the etching conditions, the structure of the substrate to be etched, etc. can be changed appropriately within the scope of the technical idea of the present invention.

[0054]

As is apparent from the above description, according to the plasma etching method of the present invention, when etching back a silicon material layer such as polycrystalline silicon, the surface on which irregularities due to crystal grains or seams are formed is removed. The silicon material layer having a smooth surface can be finally obtained by etching back while smoothing by depositing the sulfur-based material layer.

Therefore, various problems that are directly related to the deterioration of the reliability of the semiconductor device, such as deterioration of patterning accuracy of fine wiring, occurrence of Al spike due to expansion of contact plug seam, fluctuation of capacitor capacitance value, etc., are avoided. It becomes possible to do.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view illustrating a plasma etching process of a polycrystalline silicon wiring to which the present invention is applied in the order of the processes.

2A to 2D are schematic cross-sectional views illustrating the first half of the step of forming a contact plug using polycrystalline silicon to which the present invention is applied, in the order of the steps.

FIG. 3 is a schematic cross-sectional view illustrating the latter half of the contact plug formation step using polycrystalline silicon to which the present invention is applied, in the order of the steps.

FIG. 4 is a schematic cross-sectional view illustrating a step of forming a capacitor electrode using polycrystalline silicon according to the present invention in the order of steps.

FIG. 5 is a schematic sectional view showing a substrate bias application type ECR plasma etching apparatus adopted in the plasma etching method of the present invention.

FIG. 6 is an M employed in the plasma etching method of the present invention.
It is a schematic sectional drawing which shows a CR plasma etching apparatus.

FIG. 7 is a schematic cross-sectional view showing a problem of the conventional technique.

FIG. 8 is a schematic cross-sectional view showing another problem of the conventional technique.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Substrate to be etched, 2 ... Substrate stage, 3 ... Clamp, 4 ... RF bias power supply, 5 ... Magnetron, 6 ... Microwave waveguide, 7 ... Berge, 8 ... Solenoid coil, 9 ... Wall material containing sulfur, Reference numeral 10 ... Shutter, 11 ... Side wall electrode, 12 ... Side wall electrode power supply, 13 ... Counter electrode 101 ... Semiconductor substrate, 102 ... Interlayer insulating film, 103 ... Polycrystalline silicon layer, 103a contact plug, 104 ...
Sulfur-based material layer, 105 ... Connection hole, 106 ... Barrier layer,
106a Missing barrier layer, 107 ... Al-based metal layer, 10
8 ... Antireflection layer, 112 ... Insulating film, 113 ... Polycrystalline silicon layer, 113a ... Capacitor electrode, 114 ... Oxide film,
115 ... Connection hole, 116 ... Seam, 117 ... Al spike, 118 ... Capacitor hole, 122 ... Upper interlayer insulating film

Claims (6)

[Claims] 1. A plasma etching method for etching back a silicon material layer, wherein the temperature of the silicon material layer is controlled to room temperature or lower, and a sulfur-based material layer is deposited on the surface of the silicon material layer. A plasma etching method characterized by etching back. 2. The plasma according to claim 1, wherein the sulfur-based material layer is deposited by adopting an etching gas containing a gas capable of releasing free sulfur into the plasma under discharge dissociation conditions. Etching method. 3. At least one of the inner walls of the etching chamber
2. The plasma etching method according to claim 1, wherein a plasma etching apparatus whose portion is covered with a wall material containing sulfur is employed, and the wall material containing sulfur is sputtered to deposit the sulfur-based material layer. . 4. The silicon material layer is one of single crystal silicon, polycrystalline silicon and amorphous silicon.
The plasma etching method according to claim 1, wherein the plasma etching method is a seed. 5. The plasma etching method according to claim 1, wherein the sulfur-based material layer is one of sulfur and polythiazyl. 6. Gases capable of releasing free sulfur into plasma under discharge dissociation conditions are S ₂ F ₂ , SF ₂ , SF ₄ , S ₂ F ₁₀ , S ₃ Cl ₂ , and S.
₂ Cl ₂ , SCl ₂ , S ₃ Br ₂ , S ₂ Br ₂ , SBr
_{3. The} method for forming a multilayer wiring according to claim 2, wherein the method is at least one of ₂ and H ₂ S.