JPH09181171A - Multilayered wiring forming method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent plug loss due to loading effect when a contact plug is formed in a connection hole by etching back. SOLUTION: When a high melting point metal layer 5 is etched back, a contact plug surface is dropped out from the surface of an interlayer insulating film 2, and plug loss is generated. While an etching stopper layer 12 is formed on the contact plug in this stage, the interlayer insulating film 2 is selectively etched back by the thickness corresponding to the plug loss, and the plug loss is resolved. In the case of a substrate chucking system by a single pole system electrostatic chuck, an elimination step of residual charge and the etching back of the interlayer insulating layer 2 may be simultaneously processed. Hence step coverage of an upper wiring is improved by flattening the contact plug, and multilayered wiring structure of high reliability can be realized. In the case of simultaneous processing, throughput of manufacuturing process is improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a multilayer wiring applied in the field of manufacturing semiconductor devices and the like. More specifically, it is possible to improve flatness in a multilayer wiring structure in which electrical connection is made by a contact plug. A possible multilayer wiring forming method.

[0002]

2. Description of the Related Art With the progress of higher integration and higher performance of semiconductor devices such as LSI, the ratio of the area occupied by wiring portions on a semiconductor chip tends to increase. In order to avoid an increase in the semiconductor chip area due to this, interlayer connection by multilayer wiring and contact plugs is an essential process. Conventionally, as a method of forming electrodes and wiring, forming Al or Al alloy by sputtering has been widely performed. However, in the situation where the multilayer wiring has progressed as described above, and as a result, the surface step of the semiconductor substrate and the aspect ratio of the connection hole are increasing remarkably, the method including the method using a collimator is also used. In the conventional method, poor connection and disconnection due to insufficient step coverage have become serious problems.

Therefore, in recent years, various selective CVD methods have been proposed in which a refractory metal layer of W, Mo, Ta or the like or a metal of Al, Al alloy, Cu or the like is selectively grown and embedded in the connection hole. In this selective CVD, a source gas such as a metal halide, a metal carbonyl, or an organometallic compound is reduced by a lower layer wiring material exposed at the bottom of a contact hole, and a constituent metal is selectively deposited in the contact hole. . However, in the selective CVD, the selectivity gradually deteriorates as the number of batches increases, and the constituent metal tends to be deposited on an undesired portion such as on the interlayer insulating film. In addition, there is an unsolved problem such as poor controllability of etchback removal of an overgrown portion called a nail head on a contact hole, and it is the current situation that it has not reached a practical level.

In view of the above situation, the blanket CVD electrode / electrode is being reviewed in place of the selective CVD.
This is a wiring forming method. The blanket CVD is named because it deposits on the entire surface of the underlayer with no selectivity regardless of the chemical properties of the growth underlayer. As an example, a typical example is a process of covering the entire surface of an interlayer insulating film in which a connection hole is opened and forming a refractory metal layer such as W so as to fill the connection hole. In addition, W by blanket CVD
A general commentary article regarding the contact hole embedding is published, for example, on page 220 of the November 1990 issue of Semiconductor World Magazine (published by Press Journal).

[0005]

By the way, in order to use a contact plug material layer such as polycrystalline silicon or a refractory metal by blanket CVD in the contact hole to flatten it and use it as a so-called contact plug, Needless to say, it is necessary to remove unnecessary contact plug material layers deposited on the other interlayer insulating films by etching back. In this etch-back process, from the viewpoint of uniformity of processing within the substrate to be etched, it is usual to perform over-etching of, for example, about 5 to 10%. However, due to variations in the thickness of the contact plug material layer, non-uniformity of plasma density in the etching apparatus, etc., there is a portion where the underlying interlayer insulating film and barrier metal are exposed at a relatively early stage during the etch back process. is there. At this exposed portion, as a result of the reduction of the exposed area of the reaction partner, that is, the contact plug material layer and the like, the concentration of the etching species is relatively increased as compared with the other portions. For this reason, in this exposed portion, the etching rate is locally increased, and the surface of the contact plug which is once embedded in the continuous hole and flattened is largely corroded, so-called plug loss often occurs. As described above, the phenomenon that the etching rate varies as a result of the unevenness of the pattern density of the object to be etched on the same substrate to be etched is generally called a loading effect, which is a major problem in the contact plug formation process due to etchback. It is a point. It is expected that the problem of loading effect will become more and more apparent in the future where the diameter of semiconductor substrates becomes larger and high-speed single-wafer etching equipment using high-density plasma etching equipment is becoming the mainstream. It

The problem caused by the loading effect will be described in more detail with reference to FIG. In the figure, a contact hole 3 is opened in the interlayer insulating film 2 on the semiconductor substrate 1, and a contact plug made of a polycrystalline silicon layer 6 is formed therein by etching back. Especially in FIG.
As a subsequent step, a wiring layer including a barrier layer 7, an Al-based metal layer 8 and an antireflection layer 9 is formed, and an upper layer connection hole 11 is formed on the upper layer interlayer insulating film 10 using a resist mask (not shown). The state which is opening is shown.
The upper layer connection hole 11 has a so-called Stacked Contact structure formed immediately above the connection hole 3,
It is intended to miniaturize the semiconductor device by devising a layout space in the multilayer wiring.

In FIG. 5, as a result of the loading effect at the time of etching back the polycrystalline silicon layer 6, the surface of the contact plug formed by the polycrystalline silicon layer 6 is the interlayer insulating film 2.
There is a plug loss from the surface of the. It can be seen that two problems occur due to this plug loss. One is that the Al-based metal layer 8 and the antireflection layer 9 are depressed corresponding to the plug loss, and as a result, a dent portion is generated.
Diffuse reflection occurs at the time of exposure of the resist mask for opening the upper layer connecting hole 11 to lower the lithography accuracy, and the time required for overetching to completely open the upper layer connecting hole 11 increases. As a result, in the step of opening the upper layer connection hole, selective etching with the antireflection layer 9 becomes impossible, and the exposed portion of the antireflection layer 9 is shaved or the resist mask has a insufficient film thickness. 2
The second problem is step breakage due to insufficient step coverage during sputtering of the barrier layer 7. This is shown in FIG. 5 as a missing barrier layer 13. This makes Al
The system metal layer 8 is in direct contact with the contact plug made of the polycrystalline silicon layer 6, and due to thermal history in the subsequent process, Al
When the spike 14 is generated, in the worst case, the semiconductor substrate 1
It is expected that the impurity diffusion layer 1a will be penetrated.

The present invention aims to solve the above-mentioned problems of the prior art. That is, an object of the present invention is to provide a method for forming a multilayer wiring, which has a step of forming a contact plug by an etch-back method that does not cause plug loss at a level that reduces the reliability of the multilayer wiring. Another object of the present invention is to provide a method for manufacturing a semiconductor device in which throughput is not lowered in the transport process of the substrate to be etched after completion of the etch back when the substrate to be etched is held by an electrostatic chuck in such an etch back method. Is to provide.

[0009]

The method for forming a multilayer wiring according to the present invention was devised to achieve the above-mentioned object. In the first invention (Claim 1), the conductive material layer is formed on the conductive material layer. A step of opening a contact hole facing the conductive material layer in the interlayer insulating film, a step of filling the inside of the contact hole, a step of forming a contact plug material layer on the entire surface of the interlayer insulating film, and a step of etching back the contact plug material layer. In the method for forming a multilayer wiring having a step of forming a contact plug in a connection hole, a step of etching back the interlayer insulating film is provided after the etch back step of leaving the contact plug material layer only in the connection hole. To do.

In the second invention (claim 6), a step of opening a connection hole facing the conductive material layer in the interlayer insulating film on the conductive material layer, filling the inside of the connection hole, and further on the interlayer insulating film. In a multi-layer wiring forming method including a step of forming a contact plug material layer on the entire surface and a step of etching back the contact plug material layer to form a contact plug in a connection hole, a substrate to be etched is held by a unipolar electrostatic chuck. At the same time, it has a step of etching back the interlayer insulating film following the etch back step of leaving the contact plug material layer only in the contact hole, and the residual charge on the substrate to be etched induced by the monopolar electrostatic chuck. It has a step of removing.

In any of the inventions, in the step of etching back the interlayer insulating film, it is desirable to etch back while forming the etching stopper layer on the contact plug.

In any of the inventions, in the step of etching back the interlayer insulating film, the substrate to be etched is controlled at room temperature or lower, and sulfur fluoride that can generate free sulfur in plasma under discharge dissociation conditions is used. It is desirable to use an etching gas containing a system gas. Examples of such sulfur fluoride-based gas include S ₂ F ₂ , SF ₂ , SF
_At least one of ₄ and S ₂ F ₁₀ can be mentioned. Further, it is desirable to have a step of heat-treating the substrate to be etched subsequent to the step of etching back the interlayer insulating film using these sulfur fluoride-based gas.

Next, the operation of the present invention will be described. The gist of the present invention is that after the contact plug material layer etch back step, the interlayer insulating film itself is etched back by an amount commensurate with the depth of the plug loss generated by the etch back, and finally the plug loss is eliminated. In etching back the interlayer insulating film, if etching back is performed while forming an etching stopper layer on the already completed contact plug, a sufficient selection ratio with the contact plug material layer can be obtained, and the contact plug is further etched. Never.

For etching back an interlayer insulating film made of a silicon oxide-based material layer or the like, an F / S ratio such as S ₂ F ₂ , SF ₂ , SF ₄ and S ₂ F ₁₀ (a fluorine atom and a sulfur atom in one molecule) is used. When a fluorinated sulfur-based gas having a ratio of less than 6 is used, free sulfur generated by these compounds in plasma under discharge dissociation conditions is deposited on a substrate to be etched controlled to room temperature or lower. . Of these, sulfur does not remain on the interlayer insulating film made of a silicon oxide-based material layer or the like that releases oxygen by etching, but remains only on the contact plug, and functions as an etching stopper layer. The etching mechanism of the silicon oxide based material layer by the sulfur fluoride based gas is as disclosed by the applicant of the present application in Japanese Patent Application Laid-Open No. 4-84427.

[0015] These sulfur fluoride-based gas, N _2, NF
If N-based gas such as ₃ , N ₂ H ₄ and its derivative is further added, thiazyl (SN) molecules are generated in the plasma, and this compound is further polymerized by plasma to form (SN) _n, that is, polythiazyl. . Polythiazil, like sulfur, is deposited on the substrate to be etched and remains only on the contact plug to form an etching stopper layer.

Since a sulfur-based material such as sulfur or polythiazyl is a sublimable material, it is deposited on the substrate to be etched only when the substrate to be etched is controlled to a room temperature which is a normal clean room temperature or lower. On the contrary, the sulfur-based material layer once deposited is also sublimated and removed by heating the substrate to be etched after the etching back is completed, and there is no risk of leaving contamination contamination or particle contamination. The sublimation temperature is about 90 ° C. or higher for sulfur and about 150 ° C. or higher for polythiazyl in vacuum. It can also be removed by ashing treatment in an oxidizing atmosphere.

Since SF ₆ which is widely used as a sulfur fluoride gas has an F / S ratio of 6, it is difficult to generate free sulfur generated in plasma under discharge dissociation conditions. , Excluded from the sulfur fluoride-based gas used in the present invention.

In order to uniformly control the substrate to be etched below room temperature, it is necessary to bring the substrate to be etched into close contact with the cooled substrate stage and perform etch back in a good heat conduction state. For this purpose, it is desirable to use an electrostatic chuck, especially a monopolar electrostatic chuck. If a monopolar electrostatic chuck is used, residual charges remain on the substrate to be etched even after the etching back is completed, which hinders the separation of the substrate to be etched from the substrate stage. Therefore, a step of removing residual charges is required. For this purpose, as disclosed by the inventor of the present application in Japanese Patent Application Laid-Open No. 7-115085, plasma processing accompanied by a certain level of ion incident intensity is effective.
In the second invention of the present application, attention is paid to the fact that the step of removing residual charges and the etching back of the interlayer insulating film can be shared by the plasma treatment using the same sulfur fluoride gas,
It contributes to the improvement of throughput.

In the present invention, the thickness of the interlayer insulating film is reduced by the plug loss when the etch back process of the interlayer insulating film is performed. If set, there will be no problem in the performance of the completed semiconductor device such as withstand voltage.

The plasma etching apparatus for carrying out the present invention may be a conventional parallel plate type RIE apparatus, but from the viewpoint of uniform processing of a large-diameter substrate, a low operating pressure and high density plasma etching apparatus is used. Is desirable. As such an apparatus, a substrate bias application type ECR (Electron Cyclotron Res) is used.
once) plasma etching device, ICP (In
(Ductively Coupled Plasma)
Etching device, TCP (Transformer C)
open plasma etching device, helicon wave plasma (helicon wave plasma)
a) An etching device and the like can be exemplified. These plasma etching apparatuses are 1 × 10 ¹¹ / cm ³ or more and 1 × 10 ¹⁴ / cm ³ or more.
Since high-density and uniform plasma of less than about cm ³ can be generated, there is an advantage that high-speed etching can be performed.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Specific embodiments of the present invention will be described below with reference to the drawings. In the following drawings, the same components as those in FIG. 8 referred to in the description of the conventional example are designated by the same reference numerals. Further, the substrate stage of the plasma etching apparatus used in the following examples, a coolant such as Fluorinert (trade name) or ethanol circulates, and has a cooling means capable of controlling the substrate to be etched below room temperature,
It has a built-in heater that can heat the substrate.

Example 1 In this example, a W layer formed by blanket CVD as a contact plug material layer was etched back, and a substrate bias application type E having a means for cooling a substrate to be etched was used.
This is an example in which a contact plug is formed by using a CR plasma etching apparatus, which will be described with reference to FIGS. 1 (a) to 1 (c) and FIGS. 2 (d) to 2 (e).

The substrate to be etched used in this embodiment is
As shown in FIG. 1A, Si is formed on a semiconductor substrate 1 such as Si on which an impurity diffusion layer 1a is formed in advance as a conductive material layer.
An interlayer insulating film 2 of O ₂ or the like is formed by atmospheric pressure CVD or the like, a connection hole 3 facing the impurity diffusion layer 1a is opened therein, a contact layer / barrier metal layer 4 is conformally formed, and a refractory metal layer 5 is formed. Is formed on the entire surface. The thickness of the interlayer insulating film 2 is, for example, 1100 nm, and the opening diameter of the connection hole 3 is 0.30 μ.
m. The adhesion layer / barrier metal layer 4 is a Ti layer of 20n.
The m and TiN layers are formed in this order by collimated sputtering to have a thickness of 30 nm. Further, the refractory metal layer 5 made of W is formed by blanket CVD so that the contact hole 3 is buried and the adhesion layer / barrier metal layer 4 on the interlayer insulating film 2 is also covered to form a substantially flat surface.
This blanket CVD was formed under the following conditions as an example. First, after nucleating W for 20 seconds under the conditions of WF ₆ 25 sccm SiH ₄ 10 sccm gas pressure 1.1 × 10 ⁴ Pa substrate temperature 475 ° C., WF ₆ 60 sccm H ₂ 360 sccm gas pressure 1. Deposition is performed by switching to a condition of 1 × 10 ⁴ Pa and a substrate temperature of 475 ° C. The refractory metal layer 5 on the adhesion layer / barrier metal layer 4 has a thickness of, for example, 500 n.
m.

Next, the etch back step, which is a characteristic part of the present application, is entered. The substrate to be etched shown in FIG. 1A is set on the substrate stage of a substrate bias application type ECR plasma etching apparatus, and as an example, the refractory metal layer 5 is etched back under the following conditions. The etch-back of the refractory metal layer 5 is performed by the adhesion layer / barrier metal layer 4 on the interlayer insulating film 2.
Stops when exposed. The end point of this etch back was determined based on the elapsed etching time by etching the sample on which the refractory metal layer was formed in advance under the same etching conditions and measuring the etching rate. Etching back condition of refractory metal layer SF ₆ 20 sccm Ar 50 sccm Gas pressure 1.0 Pa Microwave power 900 W (2.45 GHz) RF bias power 100 W (2 MHz) Etching substrate temperature 20 ° C. Overetching 0% In the etching process, high-speed etching proceeds in such a manner that radical reactions due to F ^* , which is generated in large quantity in plasma due to dissociation of SF ₆ , are assisted by ions such as Ar ⁺ and SF _x ⁺ .

Next, the adhesion layer / barrier metal layer 4 on the interlayer insulating film 2 is etched back under the following conditions. Adhesion layer / barrier metal layer Etchback conditions Cl ₂ 40 sccm Ar 40 sccm Gas pressure 1.0 Pa Microwave power 900 W (2.45 GHz) RF bias power 150 W (2 MHz) Etching substrate temperature 20 ° C. Overetching 20% The adhesion layer / barrier metal layer 4 is etched by the interlayer insulating film 2
1), the residue of the adhesion layer / barrier metal layer 4 was not found on the exposed interlayer insulating film 2 as shown in FIG. 1B. As a result, the high melting point metal layer 5 and the adhesion layer / barrier metal layer 4 were buried evenly in the connection hole 3, but a plug loss of about 200 nm occurred, and the high melting point metal layer 5 and the adhesion layer / barrier metal layer 4 were generated. The surface of the slab fell from the surface of the interlayer insulating film 2. Therefore, when the upper layer wiring is formed in this state, problems may occur due to deterioration of step coverage.

Therefore, the etching conditions are switched in the same substrate bias application type ECR plasma etching apparatus, and the interlayer insulating film 2 is etched back under the following etching back conditions using a sulfur fluoride based gas. Interlayer insulating film etch back conditions S ₂ F ₂ 30 sccm Gas pressure 0.3 Pa Microwave power 1200 W (2.45 GHz) RF bias power 250 W (2 MHz) Etching substrate temperature −30 ° C. In this etch back step, An etching stopper layer 12 made of sulfur is formed on the exposed surface of the contact plug made of the refractory metal layer 5 and the adhesion layer / barrier metal layer 4 in the contact hole 3 to protect the contact plug surface from ion incidence. As a result, the interlayer insulating film 2 made of SiO ₂ is etched back while maintaining the selectivity.
As shown in (c), the contact plug and the interlayer insulating film 2 could be planarized on the same plane.

Next, the substrate to be etched is heated to, for example, 120 ° C. in a vacuum atmosphere, and the etching stopper layer 12 made of sulfur is removed by sublimation to obtain the state shown in FIG. 2 (d).
The above is the main part of the present embodiment.

When the Stacked Contact structure is continuously adopted, as shown in FIG. 2 (e), TiN is used.
A barrier layer 7 made of Al, etc., an Al-based metal layer 8 and an antireflection layer 9 made of TiN are sequentially formed by sputtering and then patterned to form a wiring layer. Further, an upper interlayer insulating film 10 is formed, and lithography and etching are performed using the same mask as when forming the connection hole 3 to form the upper connection hole 1
Open 1. In this embodiment, since the shape of the contact plug is ideal without plug loss, there is no deterioration in step coverage during sputtering of the Al-based metal layer in the next step, and excessive over-etching occurs when the upper layer connection hole is opened. It is possible to form a highly reliable multi-layered wiring structure without the need for applying it.

Example 2 This example is similar to the previous example 1 in that the contact plug material layer made of a W layer formed by blanket CVD is etched back, the substrate to be etched is cooled, and a monopolar electrostatic chuck is provided. This is an example in which a contact bias is formed by using a substrate bias application type ECR plasma etching apparatus. This will be described again with reference to FIGS. 1A to 1C and 2D to 2E.

Since the substrate to be etched shown in FIG. 1A used in this embodiment is the same as the substrate to be etched used in the first embodiment, duplicate description will be omitted.

Next, the substrate to be etched is adhered and held on a cooled substrate stage of a substrate bias applying type ECR plasma etching apparatus by a monopolar electrostatic chuck, and as an example, the high melting point metal layer 5 is etched back under the following conditions. Perform. The refractory metal layer 5 is etched back by the interlayer insulating film 2.
The process stops when the upper adhesion layer / barrier metal layer 4 is exposed. The end point of this etch back was determined based on the elapsed etching time by etching the sample on which the refractory metal layer was formed in advance under the same etching conditions and measuring the etching rate. Etching back condition of refractory metal layer SF ₆ 20 sccm Ar 50 sccm Gas pressure 1.0 Pa Microwave power 900 W (2.45 GHz) RF bias power 150 W (2 MHz) Etching substrate temperature −30 ° C. Overetching 0% This etching process is the same as in Example 1, but
The radical reaction is suppressed by cooling the substrate to be etched, and the etchback in which the reaction by ion assist is stronger and the anisotropy is more advanced.

Next, the adhesion layer / barrier metal layer 4 on the interlayer insulating film 2 is etched back under the following conditions. Adhesion layer / barrier metal layer Etchback conditions Cl ₂ 40 sccm Ar 40 sccm Gas pressure 1.0 Pa Microwave power 900 W (2.45 GHz) RF bias power 200 W (2 MHz) Etching substrate temperature −30 ° C. Overetching 20 % The adhesion layer / barrier metal layer 4 is etched by the interlayer insulating film 2
1), the residue of the adhesion layer / barrier metal layer 4 was not found on the exposed interlayer insulating film 2 as shown in FIG. 1B. As a result, the high melting point metal layer 5 and the adhesion layer / barrier metal layer 4 were buried evenly in the connection hole 3, but a plug loss of about 200 nm occurred, and the high melting point metal layer 5 and the adhesion layer / barrier metal layer 4 were generated. The surface of the slab fell from the surface of the interlayer insulating film 2.

Therefore, the etching conditions are switched in the same substrate bias application type ECR plasma etching apparatus, and the interlayer insulating film 2 is etched back under the following etching back conditions. This etch back condition also serves as a step of removing residual charges on the substrate to be etched. Interlayer insulating film etchback and residual charge removal conditions S ₂ F ₂ 20 sccm Ar 50 sccm Gas pressure 0.3 Pa Microwave power 1200 W (2.45 GHz) RF bias power 250 W (2 MHz) Etching substrate temperature −30 ° C. Time 20 sec In this step, the etching stopper layer 12 made of sulfur is formed on the exposed surface of the contact plug made of the refractory metal layer 5 and the adhesion layer / barrier metal layer 4 in the connection hole 3.
Are formed to protect the contact plug surface from ion incidence. As a result, the interlayer insulating film 2 made of SiO ₂ was etched back while maintaining the selection ratio, and the contact plug and the interlayer insulating film 2 could be planarized on the same plane as shown in FIG. 1C. . At the same time, the residual charges of the substrate to be etched are removed, and the substrate to be etched is removed from the substrate stage without any trouble.

Next, the substrate to be etched is heated to 120 ° C. in a vacuum atmosphere, and the etching stopper layer 12 made of sulfur is removed by sublimation to obtain the state of FIG. 2 (d).
The above is the main part of the present embodiment.

Subsequently, as shown in FIG. 2 (e), a Stacked Contact structure may be formed as in the previous embodiment. According to this embodiment, an ideal contact plug shape with no plug loss can be obtained, and the etching back of the inter-layer insulating film and the charge removal step can be performed simultaneously, so that a multilayer wiring structure with high throughput can be formed.

Embodiment 3 In this embodiment, contact back is performed by etching back the contact plug material layer formed of polycrystalline silicon with a substrate bias application type ICP (inductively coupled plasma) etching device having a cooling means for the substrate to be etched. This is an example of forming a plug, which will be described with reference to FIGS. 3 (a) to 3 (c) and FIGS. 4 (d) to 4 (e).

The substrate to be etched employed in this embodiment is:
As shown in FIG. 3A, an interlayer insulating film 2 of SiO ₂ or the like is formed by atmospheric pressure CVD or the like on a semiconductor substrate 1 of Si or the like on which an impurity diffusion layer 1a has been formed in advance to face the impurity diffusion layer 1a. The contact hole 3 is opened, and a contact plug material layer made of a polycrystalline silicon layer 6 containing impurities is further formed by low pressure CVD. The thickness of the interlayer insulating film 2 is, for example, 1
100 nm, the opening diameter of the contact hole 3 is 0.30 μm, and the polycrystalline silicon layer 6 is 500 nm on the interlayer insulating film 2.

Next, the etch back step, which is a characteristic part of this embodiment, is entered. The substrate to be etched shown in FIG.
The polycrystalline silicon layer 6 was set on the substrate stage of a substrate bias application type ICP etching device, and the polycrystalline silicon layer 6 was etched back under the following conditions as an example. The upper electrode (ground potential) of the substrate bias application type ICP etching apparatus used in this embodiment has a surface of the electrode formed of silicon and a heating means such as a heater. Etchback conditions for polycrystalline silicon layer Cl ₂ 20 sccm Ar 50 sccm Gas pressure 1.0 Pa ICP power supply power 1500 W (2 MHz) RF bias power 500 W (1.8 MHz) Etching substrate temperature 20 ° C. Upper electrode temperature 200 ° C. Over-etching 20% In this etching process, the radical reaction due to Cl ^* generated in the plasma due to the dissociation of Cl ₂ is
High-speed etching progresses in the form of being assisted by ions of ⁺ , Ar ^+, etc., no residue of the polycrystalline silicon layer 6 is observed on the interlayer insulating film 2, and the polycrystalline silicon layer is formed only in the connection hole 3. A contact plug of 6 was formed. Also, excess radicals are captured by the heated upper electrode,
Undesired isotropic etching reactions are effectively prevented. However, as shown in FIG.
Plug loss occurred. Therefore, when the upper layer wiring is formed in this state, problems may occur due to deterioration of step coverage.

Therefore, the etching conditions are switched in the same substrate bias application type ICP etching apparatus, and the interlayer insulating film 2 is etched back by the amount corresponding to the plug loss under the following etching back conditions. Interlayer insulating film etch back conditions S ₂ F ₂ 50 sccm Gas pressure 0.3 Pa ICP power supply power 1500 W (2 MHz) RF bias power 500 W (1.8 MHz) Etching substrate temperature −30 ° C. Upper electrode temperature 200 ° C. Main etching In the back step, the etching stopper layer 12 made of sulfur is formed on the exposed surface of the contact plug made of the polycrystalline silicon layer 6 in the contact hole 3 to protect the contact plug surface from ion incidence. As a result, the interlayer insulating film 2 made of SiO ₂ was etched back while maintaining the selection ratio, and the contact plug and the interlayer insulating film 2 could be planarized on the same plane as shown in FIG. 3C.

Next, the substrate to be etched is heated to, for example, 120 ° C. in a vacuum atmosphere, and the etching stopper layer 12 made of sulfur is removed by sublimation to obtain the state of FIG. 4 (d).
The above is the main part of the present embodiment.

When the Stacked Contact structure is subsequently adopted, as an example, the barrier layer 7 made of TiN or the like, the Al type metal layer 8 made of Al-2% Cu and the antireflection layer 9 made of TiN are sequentially formed by sputtering. Post-patterning is performed to form a wiring layer. Further, an upper interlayer insulating film 10 is formed, and lithography and etching are performed using the same mask as that for forming the connection hole 3 to open the upper connection hole 11. This state is shown in FIG. In this embodiment, since the contact plug has an ideal contact plug shape with no plug loss, there is no deterioration in step coverage during sputtering of the Al-based metal layer or the like in the next step. Further, since the surface of the wiring layer has good flatness, overetching at the time of opening the upper layer connection hole is sufficient in a short time, and a highly reliable multilayer wiring structure can be formed.

Example 4 In this example, the etch back of the contact plug material layer also made of polycrystalline silicon was performed by using a substrate bias application type helicon wave plasma having a cooling means for the substrate to be etched and a monopolar electrostatic chuck means. This is an example in which a contact plug is formed by using an etching device, and this is also shown in FIGS. 3 (a) to 3 (c) and FIGS.
This will be described with reference to FIG.

The substrate to be etched shown in FIG. 3A used in this embodiment is the same as that described in the third embodiment, and therefore the duplicated description will be omitted. This substrate to be etched is held by an electrostatic chuck on a cooled substrate stage of a substrate bias application type helicon wave plasma etching device,
As an example, the polycrystalline silicon layer 6 was etched back under the following conditions. Etchback conditions for polycrystalline silicon layer Cl ₂ 20 sccm Ar 50 sccm Gas pressure 1.0 Pa Helicon wave power source power 1500 W (13.56 MHz) RF bias power 250 W (400 kHz) Etching substrate temperature −30 ° C. Overetching 20 % In this etching step, the radical reaction due to Cl ^* generated in the plasma due to the dissociation of Cl ₂ is
High-speed etching progresses in the form of being assisted by ions of ⁺ , Ar ^+, etc., no residue of the polycrystalline silicon layer 6 is observed on the interlayer insulating film 2, and the polycrystalline silicon layer is formed only in the connection hole 3. A contact plug of 6 was formed. However, as shown in FIG. 3B, a plug loss of about 150 nm occurred. Therefore, when the upper layer wiring is formed in this state, problems may occur due to deterioration of step coverage. The substrate to be etched is
Electrostatic chuck Even when the power supply is turned off, the electrostatic chuck is still firmly electrostatically adsorbed on the substrate stage.

Therefore, the etching conditions are switched in the same substrate bias application type helicon wave plasma etching apparatus, the interlayer insulating film 2 is etched back by the amount corresponding to the plug loss under the following etch back conditions, and the substrate to be etched is destaticized. Give. Interlayer insulating film etch back and static elimination processing conditions S ₂ F ₂ 20 sccm N ₂ 20 sccm Ar 80 sccm Gas pressure 1.0 Pa Helicon wave power source power 1000 W (13.56 MHz) RF bias power 100 W (400 kHz) Etched substrate Temperature −30 ° C. Time 20 sec In this etching back and static elimination treatment step, the etching stopper layer 12 made of polythiazyl is formed on the exposed surface of the contact plug made of the polycrystalline silicon layer 6 in the contact hole 3, and the contact plug surface is formed. Protects against ion injection. As a result, the interlayer insulating film 2 made of SiO ₂ was etched back while maintaining the selection ratio, and as shown in FIG. 3C, the contact plug and the interlayer insulating film 2 could be planarized on the same plane. Further, the residual charges of the substrate to be etched were also removed at the same time, and the substrate to be etched could be separated from the substrate stage without any trouble.

Next, the substrate to be etched is heated to, for example, 170 ° C. in a vacuum atmosphere, and the etching stopper layer 12 made of polythiazyl is removed by sublimation to obtain the state of FIG. 4 (d). The above is the main part of the present embodiment.

When the Stacked Contact structure is subsequently adopted, the same post-process as in the third embodiment is performed to complete the multilayer wiring structure shown in FIG. In this embodiment, since the contact plug has an ideal shape without plug loss, the step coverage during sputtering of the Al-based metal layer in the next step is not deteriorated and a highly reliable multilayer wiring structure can be formed. Is. Further, since the static elimination step required when using the monopolar electrostatic chuck is shared with the etching back of the interlayer insulating film, a manufacturing process with high throughput becomes possible.

Although the present invention has been described with reference to the four examples, the present invention is not limited to these examples.

For example, in the embodiments, as the conductive material layer,
The process of forming the contact plug by embedding the refractory metal layer or the polycrystalline silicon layer in the connection hole opened on the impurity diffusion layer of the semiconductor substrate has been described as an example. In addition to this, polycrystalline silicon, polycide, or the like may be used as the conductive material layer, and the conductive material layer may be applied to a process of embedding in a via hole formed in an interlayer insulating film on a lower wiring formed of these materials. See also Stacked Con
It may be a general contact structure other than the tact structure. Further, when applied not only to the contact plug but also to embedded wiring or the like in which wiring is formed in the groove formed in the interlayer insulating film, it contributes to planarization of the multilayer wiring here as well.

Although W is exemplified as the refractory metal layer 5, M
Other refractory metals such as o and Ta may be used. The adhesion layer / barrier metal layer 4 is exemplified by Ti / TiN.
ON, TiW, TiSi _x, etc., may be appropriately selected various materials depending on the material of the base and the refractory metal layer. Alternatively, as the contact plug material layer, Al-based metal, Cu-based metal, or the like may be used.

As the etching apparatus, a substrate bias application type ECR plasma etching apparatus, an ICP etching apparatus and a helicon wave plasma etching apparatus are exemplified, but a more general parallel plate type RIE apparatus or a magnetron RIE apparatus may be used. .

Further, it goes without saying that the etching conditions, etching gas, structure of the substrate to be etched, etc. can be appropriately changed within the scope of the technical idea of the present invention.

[0052]

As is apparent from the above description, according to the present invention, the plug loss caused by the loading effect at the time of etching back the contact plug material layer can be reduced or eliminated, and the highly integrated semiconductor device which uses a lot of multilayer wiring. The flatness at is improved. Therefore, the step coverage of the upper layer wiring formed on the interlayer insulating film is improved, and the disconnection of the wiring step can be prevented. Further, there is no irregular reflection of exposure light at the time of lithography of the resist mask for patterning the upper layer wiring, and accurate processing can be performed.

When an etching apparatus having a means for holding a substrate to be etched by a single-pole type electrostatic chuck is used, flattening by etching back can be achieved by simultaneous processing with a step of removing residual charges on the substrate to be etched, An extremely high throughput manufacturing process is possible. Due to the effects described above, interlayer connection of multilayer wiring based on a fine design rule can be performed with high reliability, and the method for forming a multilayer wiring of the present invention greatly contributes to the manufacturing process of semiconductor devices and the like.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view illustrating the first half of the steps of Examples 1 and 2 to which the present invention is applied in the order of the steps, (a)
Shows a state in which an adhesion layer / barrier metal layer and a refractory metal layer are formed on the entire surface of a semiconductor substrate having a connection hole, and (b) shows a contact plug formed by etching back the refractory metal layer and the adhesion layer / barrier metal layer. In the state where the plug loss occurs, (c) shows a state in which the interlayer insulating film is etched back while forming the etching stopper layer on the contact plug.

FIG. 2 is a schematic cross-sectional view illustrating the latter half of the steps of Examples 1 and 2 to which the present invention is applied, in the order of the steps, (d)
Is a state where the etching stopper layer is removed, (e) is St
This is a state in which a multilayer wiring having an acked contact structure is formed.

FIG. 3 is a schematic cross-sectional view illustrating the first half of the steps of Examples 3 and 4 to which the present invention is applied, in the order of the steps;
Is a state in which a polycrystalline silicon layer is formed on the entire surface of a semiconductor substrate having a connection hole, (b) is a state in which a polycrystalline silicon layer is etched back to form a contact plug, and plug loss occurs, and (c) is a contact plug. The interlayer insulating film is in a state of being etched back while the etching stopper layer is formed thereon.

FIG. 4 is a schematic cross-sectional view illustrating the latter half of the steps of Examples 3 and 4 to which the present invention is applied in the order of the steps, (d)
Is a state where the etching stopper layer is removed, (e) is St
This is a state in which a multilayer wiring having an acked contact structure is formed.

FIG. 5 is a schematic cross-sectional view illustrating a problem in a conventional method of forming a multilayer wiring.

[Explanation of symbols]

 1 Semiconductor Substrate 1a Impurity Diffusion Layer 2 Interlayer Insulation Film 3 Connection Hole 4 Adhesion Layer and Barrier Metal Layer 5 Refractory Metal Layer 6 Polycrystalline Silicon Layer 7 Barrier Layer 8 Al-Based Metal Layer 9 Antireflection Layer 10 Upper Layer Interlayer Insulation Film 11 Upper Layer Connection hole 12 Etching stopper layer 13 Missing barrier layer 14 Al spike

Claims (10)

[Claims] 1. A step of forming a connection hole facing the conductive material layer in an interlayer insulating film on the conductive material layer, filling the connection hole, and further forming a contact plug material layer on the entire surface of the interlayer insulating film. Step, in the multilayer wiring forming method having a step of etching back the contact plug material layer to form a contact plug in the connection hole, following the etchback step of leaving the contact plug material layer only in the connection hole, A method of forming a multi-layer wiring, comprising a step of etching back the interlayer insulating film. 2. The method for forming a multilayer wiring according to claim 1, wherein in the step of etching back the interlayer insulating film, etching back is performed while forming an etching stopper layer on the contact plug. 3. In the step of etching back the interlayer insulating film, the substrate to be etched is controlled to a room temperature or lower, and etching containing a sulfur fluoride-based gas capable of generating free sulfur in plasma under discharge dissociation conditions. The method for forming a multilayer wiring according to claim 1, wherein a gas is used. 4. The sulfur fluoride-based gas is at least any one of S ₂ F ₂ , SF ₂ , SF ₄ and S ₂ F _10.
A method for forming a multilayer wiring as described. 5. The method for forming a multilayer wiring according to claim 3, further comprising a step of heat-treating the substrate to be etched after the step of etching back the interlayer insulating film. 6. A step of opening a connection hole facing the conductive material layer in an interlayer insulating film on the conductive material layer, filling the inside of the connection hole, and further forming a contact plug material layer on the entire surface of the interlayer insulating film. A step of etching back the contact plug material layer to form a contact plug in the connection hole, wherein the substrate to be etched is held by a unipolar electrostatic chuck, Following the etchback step of leaving the layer only in the connection hole, there is a step of etching back the interlayer insulating film, and removing the residual charges on the substrate to be etched induced by the monopolar electrostatic chuck. A method for forming a multi-layer wiring, characterized by comprising steps. 7. The method for forming a multilayer wiring according to claim 6, wherein in the step of etching back the interlayer insulating film, etching back is performed while forming an etching stopper layer on the contact plug. 8. In the step of etching back the interlayer insulating film, the substrate to be etched is controlled to a room temperature or lower, and etching containing a sulfur fluoride-based gas capable of generating free sulfur in plasma under discharge dissociation conditions. 7. The method for forming a multilayer wiring according to claim 6, wherein gas is used. 9. The sulfur fluoride-based gas is at least any one of S ₂ F ₂ , SF ₂ , SF ₄ and S ₂ F _10.
A method for forming a multilayer wiring as described. 10. The method for forming a multilayer wiring according to claim 8, further comprising a step of heating the substrate to be etched, following the step of etching back the interlayer insulating film.