JP2001085331A - Sequential sputter and reactive precleaning of via-hole and contact - Google Patents

Abstract

PROBLEM TO BE SOLVED: To generally obtain a method for improving fill and electrical performance of metals deposited on patterned dielectric layers. SOLUTION: A method includes a process, in which a patterned dielectric layer is cleaned in a processing chamber with a first plasma, consisting essentially of argon (212), a process in which the patterned dielectric layer is cleaned in a processing chamber with a second plasma consisting essentially of hydrogen and helium (215), a process in which a barrier layer is deposited on the patterned dielectric layer, after exposing the dielectric layer to the first plasma and the second plasma (220) and a process, in which a metal is deposited on the barrier layer. Furthermore, the sequential plasma treatments can be conducted in a variety of plasma processing chambers of an integrated processing sequence, including pre-clean chambers, PVD chambers, etching chambers and other plasma processing chambers.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

FIELD OF THE INVENTION The present invention relates generally to the deposition of a film on a substrate. More particularly, the present invention relates to etching and cleaning of a dielectric layer prior to metal deposition.

[0002]

BACKGROUND OF THE INVENTION In integrated circuits, feature sizes are becoming smaller, multilayer metallization is becoming more common, and the importance of low dielectric constant films is increasing. Low-k films, especially for intermetal dielectric (IMD) layers, reduce the RC time delay of coated connection metallization, prevent crosstalk between metallizations, and reduce device power consumption. desirable.

[0003] Sub-half micron multilayer metallization is the next generation of very large scale integrated circuits ("VLSI").
Is one of the key technologies. Multi-layer connections at the heart of this technology require planarization of high aspect ratio features such as plugs and other interlayer connections. The reliable formation of these interlayer connections is critical to the success of VLSI and the constant effort to improve circuit density and quality on individual substrates and dies.

[0004] Conventional chemical vapor deposition (CVD) and physical vapor deposition (PVD) techniques deposit conductive material into contact holes, vias, trenches, or other features formed on a substrate. Used for One problem with conventional processes is that contact holes or other patterns often have a high aspect ratio, ie, a ratio of hole height to their width or diameter that is greater than one. The aspect ratio of the hole is
Technological advances increase as more closely spaced features are obtained.

[0005] The presence of natural oxides and other contaminants in small features typically results in non-uniform distribution of the deposited metal in the features, as natural oxides and other contaminants promote uneven distribution of the deposited metal. Causes voids. Exposure of the exposed film layer / substrate to oxygen results in the formation of this natural oxide. Exposure to oxygen can occur when the substrate is moved in air at atmospheric conditions between processing chambers, or when a small amount of oxygen remaining in the vacuum chamber contacts the wafer / film layer.
Or when the layer is contaminated by etching.
Other contaminants in the features include sputter material from the oxide overetch, residual photoresist from the stripping process, residual hydrocarbon or fluorocarbon polymers from the preceding oxide etch step, Alternatively, it is a redeposited substance derived from a pre-cleaning sputter etching process. Natural oxides and other contaminants form regions on the substrate that hinder film formation by forming regions where film growth is hindered. Before the growth restricted area is filled with the deposited metal, the enhanced growth area will swallow and seal the microfeatures.

Also, the presence of natural oxides and other contaminants increases via / contact resistance and reduces the electromigration resistance of small features.
Contaminants can diffuse into the dielectric layer, sublayer, or deposited metal and can alter the performance of devices containing small features. Contamination occurs at the interface between the deposited metal and the underlying conductive or semi-conductive features.
Although it may be limited to a thin boundary region within the feature, this thin boundary region is the pivot of the micro-feature. Acceptable level values of contaminants in a feature decrease with decreasing feature width.

[0007] Pre-cleaning of features using a sputter etch process is effective in reducing contaminants in large features or small and large features having an aspect ratio of less than about 4: 1. However, sputter etch processes, physical shock, sputter deposition and the Si / SiO ₂ onto the feature sidewalls, Suppata deposition of metal sublayer, such as aluminum or copper onto the feature sidewalls, damage to the silicon layer by . For larger features, the sputter etch process typically reduces the amount of contaminants in the features to acceptable levels. For smaller features with larger aspect ratios, the sputter etch process was not very effective at removing intra-feature contaminants and reduced the performance of the formed device.

[0008] Precleaning by a sputter etch process is not particularly suitable for features having exposed copper. Copper readily diffuses into and penetrates the dielectric, including the sidewalls of vias formed in the dielectric, destroying or degrading the integrity of the dielectric. This diffusion is true for TEOS, thermal oxides, and dielectric materials with some low K constants. Therefore, when copper pre-cleaning is applied, a new pre-cleaning process is required.

FIG. 1 shows a substrate 10 including holes 11 formed in an electrically insulating layer or dielectric layer 12 thereon, such as, for example, a layer of silicon dioxide or silicon nitride. Contaminants on the sidewalls 14 of the holes promote uneven deposition of the metal-containing layer, making it difficult to deposit a uniform metal-containing layer in the high aspect ratio hole 11. The metal-containing layer eventually aggregates across the width of the hole before the hole is completely filled, thereby forming voids and discontinuities in the hole. Thereafter, the high mobility of the metal atoms surrounding the voids causes the atoms to diffuse and minimize the void surface area forming circular voids as shown in FIG. These voids and discontinuities result in poor and unreliable electrical contacts.

[0010] Pre-cleaning is primarily a sputter-etch type process in which contaminants are sputtered from the substrate. It is preferably carried out using a mixture of an inert gas, typically argon, and a reactive gas, typically hydrogen. A mixture of argon and hydrogen is used to remove both reactive and non-reactive contaminants, modify the shape of contact holes, vias, trenches and other patterns to improve subsequent metal deposition processes it can. Increasing the argon content in the pre-cleaning mixture gas results in a corresponding increase in the pre-cleaning process etch rate and a corresponding decrease in the pre-cleaning process etch uniformity. In order to effectively remove reactive compounds or contaminants such as copper oxides and hydrocarbons, the gas mixture must contain hydrogen. By pre-cleaning the patterned substrate with a mixed gas of argon and some amount of hydrogen, the etching rate is lower and the etching non-uniformity is increased as compared with the pre-cleaning using argon.

A pre-cleaning process having both a high concentration of reactive gas and an improved etch rate would substantially enhance the removal of contaminants by the addition of reactive gas. .

No. 5,660,68 by Zhao et al.
No. 2 illustrates an attempt to combine reactive cleaning with etching of a patterned dielectric layer using a plasma containing hydrogen and argon. Argon etches the deposit from the openings and hydrogen reacts with the residual deposit to form gaseous by-products. While the combination of etching and cleaning improves subsequent metal deposition, the combined plasma treatment does not prevent void formation in subsequent metal layers. Accordingly, there remains a need for a method of improving metal layer deposition on patterned dielectric layers, especially on openings such as vias and trenches having an aspect ratio greater than about 1.0.

[0013]

SUMMARY OF THE INVENTION The present invention generally provides a method for improving the filling and electrical performance of a metal deposited on a patterned dielectric layer. Openings, such as vias and trenches, in the patterned dielectric layer are etched to facilitate filling and then cleaned to reduce metal oxide in the openings. In one aspect, the invention is directed to cleaning a patterned dielectric layer in a processing chamber with a first plasma comprising primarily argon, and in a processing chamber with a second plasma comprising hydrogen and helium as essential. Cleaning of the patterned dielectric layer. After etching and cleaning, the openings are filled with a metal that can be deposited on the barrier / liner layer. Preferably, both cleaning processes are performed in the same chamber.

The present invention also provides a process for cleaning a patterned dielectric layer in a processing chamber using a first plasma comprising argon as essential, wherein the first plasma comprises a first plasma. By supplying RF plasma power to an induction coil surrounding the processing chamber and to a substrate support member supporting the substrate.
Generated by applying a bias. The patterned dielectric layer is cleaned in process by a second plasma, essentially composed of hydrogen and helium, where the second plasma provides RF plasma power to an induction coil surrounding the processing chamber. Is increased, and R to the substrate supporting member supporting the substrate is increased.
Generated by reducing the F bias supply.

Further, after exposing the dielectric layer to the first plasma and the second plasma, a barrier / liner layer is deposited on the patterned dielectric layer, and then a metal layer is deposited on the barrier layer. Is also good. Furthermore, sequential plasma processing can be performed in various plasma processing chambers of an integrated process sequence, including a pre-cleaning chamber, a physical vapor deposition chamber, an etching chamber, and other plasma processing chambers.

[0016]

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a suitable method for pre-cleaning vias, contacts, and other features that are etched into a dielectric layer, such as a silicon dioxide layer. The dielectric layer is made of Ge, S
Etched in a dry or wet etch chamber to expose conductor or semi-conductive sublayers, such as i, Al, Cu, or TiN sublayers. The etching exposes the sub-layer, which allows the features to be filled with a conductor or semi-conductive material, the material comprising:
A connection is made with a metal interlayer connection layer subsequently deposited on the dielectric layer. Etching features in a dielectric typically leaves contaminants that must be removed to improve feature filling and to increase the integrity and reliability of the final device formed. It is.

After etching the dielectric layer, the features are:
It may contain damaged silicon or metal residues resulting from overetching of the dielectric layer. The feature may also include residual photoresist on its surface from one or both of the photoresist stripping and ashing processes, or residual hydrocarbons from a dielectric etching step, or fluorocarbon polymers. There is. The feature surface may also contain redeposited material generated by the sputter etch preclean process. These contaminants can interfere with the selectivity of the metallization by migrating into the dielectric layer or promoting uneven distribution of the deposited metal. Also, the presence of contaminants substantially reduces the width of the features and, consequently, creates narrower areas within the metal forming vias, contact interconnects, or other conductive features, thereby reducing the resistance of the deposited metal. May increase.

Submicron features that have been cleaned and filled according to the present invention are formed by conventional techniques for depositing a dielectric material on the surface of a semiconductor substrate. Any dielectric material now known or later discovered can be used and is within the scope of the present invention, including low dielectric materials such as organic polymers and aerogels. The dielectric layer can include one or more different layers, and can be deposited on any suitable sub-layer that facilitates deposition. Preferred deposition promoting sublayers include a conductive metal such as Al, Cu, and a barrier surface such as TiN, Ta, TaN.

[0019] Once deposited, the dielectric layer can be formed using conventional techniques.
Etched by vias, contacts, and trains
H or other sub-micron features.
Features typically have high aspect ratios with steep sidewalls
Will have a ratio. Etching of dielectric layer is plasma
Any dielectric etching process, including etching
May be realized. For etching silicon dioxide
The unique technique of C_TwoF ₆,SCIENCE FICTION₆, And NF_ThreeCompound like
Things are included. However, patterning is known in the art.
Can be realized on any layer using any of the methods
Good.

[0020]

FIG. 2 is a schematic diagram of a cluster tool system having a multi-substrate processing chamber. The cluster tool system 100 includes vacuum load lock chambers 105, 110 mounted on a first stage transfer chamber 115. Load lock chamber 1
05, 110 maintain the vacuum conditions in the first stage transfer chamber 115 while substrates enter and exit the system 100. The first robot 120 includes one or more substrate processing chambers 125 and 1 attached to the load lock chambers 105 and 110 and the first stage transfer chamber 115.
The substrate is transferred to and from the substrate 30. Processing chambers 125 and 1
30 is provided for performing a number of substrate processing operations such as chemical vapor deposition (CVD) or physical vapor deposition (PVD), etching, pre-cleaning, degassing, orientation, and other substrate processes. Can be. In addition, the first robot 120 may transfer the substrate to one or more transfer chambers 13 disposed between the first stage transfer chamber 115 and the second stage transfer chamber 140.
Have 5 go in and out. The transfer chamber 135 includes a first stage transfer chamber 115 and a second stage transfer chamber 14.
It is used to maintain an ultra-high vacuum state in the second stage transfer chamber 140 while a substrate transfer between 0 is possible. The second robot 145 transfers a substrate between the transfer chamber 135 and the plurality of substrate processing chambers 150, 155, 160, and 165.

Similar to the processing chambers 125, 130 described above, additional processing chambers 150, 165 can be provided to perform various substrate processing operations. For example, the processing chamber 150 is a CVD chamber provided for depositing a silicon oxide film, and the processing chamber 155
Is an etching chamber provided for etching the opening for the interlayer contact feature;
0 is a PVD chamber provided for reactive sputter deposition of one or both of tantalum, tantalum nitride barrier films, and a process chamber 165 is provided for PVD provided for sputter deposition of a conductor film such as copper. Chamber. Arranging the processing chambers in sequence is beneficial for the practice of the present invention. Multiple cluster tool systems are required to perform all the processes required to complete the interconnects in the manufacture of integrated circuits or chips.

In operation, substrates are transferred to vacuum load lock chambers 105, 110 by a conveyor belt or robotic system (not shown) operating under the control of a microprocessor or computer program executed by a computer (not shown). Is done. Robot 1
20 and 145 operate under the control of a computer program to transfer substrates between the various processing chambers of the cluster tool system 100.

The above cluster tool system is mainly for explanation. Electron cyclotron resonance (EC
R) Other plasma processing equipment, such as plasma processing equipment, inductively coupled RF high density plasma processing equipment, etc., may be used as part of the cluster tool system. Furthermore, the method for forming a silicon oxide layer and a barrier layer of the present invention is not limited to a specific apparatus or a specific plasma excitation method.

FIG. 3 is a flowchart showing the argon pre-cleaning step and the hydrogen plasma pre-cleaning step of the present invention along with other process sequence steps occurring before and after the hydrogen plasma pre-cleaning step. The steps shown in FIG. 3 can be performed in response to instructions of a computer program executed by a microprocessor or a computer controller for the cluster tool system 100.

First, a dielectric layer is deposited on a substrate (step 200). Deposition of a dielectric layer such as a silicon oxide film can be achieved through various known methods. The dielectric layer is preferably deposited using, for example, a CVD process performed in the CVD chamber 150 shown in FIG. However, as will be appreciated by those skilled in the art, for the formation of active devices and other structures, the substrate is typically subjected to a number of processing steps prior to deposition of the dielectric layer.

Second, the dielectric layer is planarized in preparation for depositing an overlying layer (step 205). The planarization process can include chemical mechanical polishing (CMP), etching, or other similar processes. Openings for interlayer connection features, such as contacts, vias, etc., are etched into the dielectric layer (step 210). The sputter etching process can be performed in a typical etching chamber, such as the etching chamber 155 shown in the cluster tool system 100 of FIG. Typically, the thickness of the dielectric layer is between about 0.5 microns and about 3.0 microns, and the interconnect structure has sub-quarter micron openings and an aspect ratio (width greater than 1: 1). Ratio to height). Step 205, 210
Produces a patterned substrate with interconnect features that are metallized or filled with multiple layers of material.

Third, an argon plasma cleaning (step 212) according to the present invention is performed on the patterned substrate to remove deposits from previous process steps. In an argon plasma step, the deposit is sputtered by the argon plasma and removed from the opening. The argon sputtering process
While it can be performed in various chambers, it is preferable to perform in a pre-cleaning chamber. Fourth, a hydrogen plasma pre-cleaning step according to the present invention is performed on the patterned substrate. The substrate is pre-cleaned using a hydrogen plasma (step 215) to reduce copper oxide to copper and to clean and stabilize the structure of the dielectric layer. Although the pre-cleaning step can be performed in any typical plasma processing chamber, it is preferred that the pre-cleaning step be performed in the pre-cleaning chamber. The steps of argon plasma etching and hydrogen plasma pre-cleaning according to the present invention will be described in more detail with respect to the pre-cleaning chamber shown in FIG.

Next, a diffusion barrier layer, preferably tantalum nitride, is deposited to prevent diffusion of silicon into the overlying metal layer (step 220). The diffusion barrier layer also improves film adhesion between different films such as a metal film and a silicon oxide film. The tantalum nitride layer is preferably deposited using a PVD chamber provided for known reactive sputtering. The thickness of the diffusion barrier layer is about 50
Preferably, it is between Angstroms and about 200 Angstroms.

FIG. 4 is a cross-sectional view of a typical PVD chamber useful for depositing a barrier layer. PVD chamber 310
Generally includes a chamber enclosure 312, a substrate support member 314, a target 316, a shield 318, a clamp ring 320, a gas inlet 322, and a gas exhaust port 32.
4, including a magnet assembly 326, an RF plasma power source 328, and an RF bias source 334.
During processing, the substrate 330 is placed on the substrate support member 314 and processing gas is passed through the gas inlet 322 located between the end of the target and the top of the shield, the target 316,
The substrate 330 is introduced into the processing area 332 defined by the shield 318. An RF bias source 334 supplies an RF bias to the substrate support member 314, while an RF bias source
The plasma power source 328 supplies RF power to the target during processing to excite and maintain the plasma of the processing gas in the processing region 332. Shield 318 is typically grounded during processing. During deposition, ions in the plasma bombard the target, sputtering material from the surface of the target. The sputtered material reacts with ions in the plasma to form a desired film on the substrate surface. For the deposition of barrier films such as tantalum / tantalum nitride, it is common for the process gas to include argon and nitrogen, where argon is the primary gas source for plasma ions bombarding the target 316. In operation, nitrogen reacts primarily with atoms (tantalum) sputtered from target 316 to form a tantalum / tantalum nitride film deposited on substrate 330. After deposition of the barrier film, the substrate is typically annealed at a temperature between about 300 and about 500 degrees to improve the material properties of the deposited film.

Finally, a metal layer, such as copper, is deposited on the diffusion barrier layer and an interlayer contact feature (step 22).
5) The formation is completed. The thickness of the metal layer is about 6,000
Desirably, between 0 Angstroms and about 10,000 Angstroms. Copper deposition can be performed in a known typical PVD chamber or a typical CVD chamber. The above process would be repeated for a multi-layer integrated circuit structure.

According to the present invention, the patterned dielectric layer is pre-cleaned using an argon plasma and then a hydrogen plasma prior to the deposition of the tantalum nitride barrier layer. The pre-cleaning process can be performed in various processing chambers including a PVD chamber, a CVD chamber, an etching chamber, and a pre-cleaning chamber. The pre-cleaning process is preferably performed using a pre-cleaning chamber prior to depositing the tantalum nitride barrier layer. Although the invention is described using a pre-cleaning chamber, the invention applies to various processing chambers.

FIG. 5 is a cross-sectional view of a typical pre-cleaning chamber that is advantageous for the present invention. An example of a pre-cleaning chamber useful in the present invention is Pre-Clean II Chamb
er and provided by Applied Materials, Inc. of Santa Clara, California. In general, the pre-cleaning chamber 510 has a substrate support member 512 located within a processing chamber enclosure 514 below the quartz dome. Substrate support member 512 typically includes a central pedestal plate 518 disposed within recess 520 on insulating plate 522, where substrate support member 512 is typically made of quartz, ceramic, or the like. ing. During processing, substrate 524 is mounted on central pedestal plate 518 and secured thereon by locating pins 532. Preferably, the RF coil 526 is located outside the quartz dome 516 to bombard and maintain the process gas in the chamber
Connected to power source 524. Generally, an RF matching network 530 is provided for matching between the RF power source 524 and the RF coil 526.
The substrate support member 512 is typically connected to an RF bias source 528 that provides a bias to the substrate support member 512. The RF power source 524 includes a coil 526
Provides RF power up to about 500 W at 2 MHz,
Bias source 528 is applied to substrate support member 512.
It is preferred to provide up to about 500 W of RF bias at 56 MHz.

According to the present invention, the patterned or etched substrate may be pre-cleaned using an argon plasma and then a hydrogen plasma in a pre-cleaning chamber prior to deposition of the barrier layer. preferable. After the dielectric layer has been planarized and the openings for the interconnect features have been formed, the substrate is preferably transferred to a pre-cleaning chamber. Pattern etching of the substrate is performed prior to transfer of the substrate to a processing platform or system having a pre-cleaning chamber.
Processing may occur in other processing platforms or systems. Once the substrate is loaded for processing in the pre-cleaning chamber, a processing gas containing primarily argon, i.e., more than about 50% argon by number of atoms, is applied to the processing region, preferably at a pressure of about 0.8 mtorr. be introduced.
The argon gas plasma is excited in the processing area and exposes the substrate to an argon sputter cleaning environment. The argon plasma provides between about 50 W and about 500 W of RF power from the RF power source 524 to the RF coil 526;
Preferably, an RF bias between about 50 W and about 500 W is applied from the RF bias source 528 to the substrate support member 512 for generation. The argon plasma is held for about 10 to about 300 seconds to provide sufficient cleaning time for deposits that are not easily removed with a reactive hydrogen plasma. The argon plasma is preferably generated by about 300 W of RF power applied to the coil and about 300 W of RF bias applied to the substrate support, and is preferably held for about 60 seconds.

Following the argon plasma, the chamber pressure is increased to about 80 mTorr, and a processing gas, consisting essentially of hydrogen and helium, containing between 5% and 100% hydrogen by number of atoms is introduced into the processing region. The process gas preferably contains about 5% hydrogen and about 95% helium. The hydrogen / helium gas plasma is bombarded in the processing region to expose the substrate to a reactive hydrogen plasma environment. The hydrogen plasma is supplied from the RF power source 524 at about 50 W and about 5 W.
It is generated by applying a power between 00 W to the RF coil 526 and an RF bias between about 5 W and about 300 W from the RF bias source 528 to the substrate support member 512. The hydrogen plasma is held for a time between about 10 seconds and about 300 seconds to reduce copper oxide to copper and clean the substrate. The hydrogen plasma is preferably generated by applying an RF power of about 450 W to the coil and an RF bias of about 10 W to the substrate support member, preferably about 60 W.
Hold for seconds. Once the pre-cleaning process is over, the pre-cleaning chamber is evacuated to evacuate process gases and reaction by-products from the pre-cleaning process. Thereafter, a barrier layer is deposited on the cleaned substrate, and the remaining processes outlined in FIG. 3 are performed.

While the above description is directed to preferred embodiments of the invention, other and further embodiments of the invention will be devised without departing from the basic scope of the invention. The scope of the present invention is defined by the appended claims.

[Brief description of the drawings]

BRIEF DESCRIPTION OF THE DRAWINGS For a better understanding of how the above-described features, advantages and objects of the invention are achieved,
The present invention will be described in more detail with reference to its embodiments shown in the accompanying drawings. However, the accompanying drawings merely illustrate exemplary embodiments of the present invention, and
It should be noted that this should not be considered as limiting the scope of the invention. This is because the present invention allows for other equally effective embodiments.

FIG. 1 is a schematic, partial cross-sectional view of a patterned substrate showing irregularly-oriented, fine-grained particle deposition in contact holes in a substrate having voids, discontinuities, and uneven surfaces. Show layers.

FIG. 2 is a schematic diagram of a cluster tool system having a multiple substrate processing chamber.

FIG. 3 illustrates another process sequence step that occurs before and after the argon and hydrogen plasma steps.
It is a flowchart which shows the sequential step of argon plasma cleaning and hydrogen plasma cleaning of this invention.

FIG. 4 is a cross-sectional view of an exemplary PVD chamber useful for depositing a barrier layer.

FIG. 5 is a cross-sectional view of a typical pre-cleaning chamber useful in the present invention.

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Bernie M. Cohen United States of America, California, Santa Clara, Marietta Drive 2931 (72) Inventor Suraj Bengarajan United States of America, California, Sunnyvale, Astor Avenue 1035 Apartment Number 1160 (72) Inventor of Shanbin Lee United States of America, California, San Jose, Villa Center Way 648 (72) Inventor Kenny King-Thai Nguyen Cameron Hills Drive 43793, Fremont, California, United States of America 43793 (72) Inventor @ Jandin United States of America, California, San Jose, W. Riverside Way 1020

Claims (20)

[Claims] 1. A method for improving metal deposition on a patterned dielectric layer, the method comprising: a) cleaning the patterned dielectric layer in a processing chamber with a first plasma comprising primarily argon. And b) cleaning the patterned dielectric layer in the processing chamber with a second plasma essentially comprising hydrogen and helium. 2. The method of claim 1, wherein said processing chamber is a pre-cleaning chamber. 3. The method of claim 1, wherein the first plasma is configured with argon as essential. 4. The method of claim 1, wherein the second plasma is comprised of about 5% to about 100% hydrogen and about 0% to about 95% helium. the method of. 5. The method of claim 1, further comprising: after exposing the dielectric layer to the first plasma and the second plasma, depositing a metal on the patterned dielectric layer. 6. A method for improving metal deposition on a patterned dielectric layer on a substrate, comprising: a) the patterned dielectric in a processing chamber by a first plasma comprising primarily argon. Cleaning gymnastics, wherein the first plasma is generated by applying RF power to a coil surrounding the processing chamber to apply an RF bias to a substrate support member supporting the substrate; b. Cleaning the patterned dielectric layer in the processing chamber with a second plasma essentially comprising hydrogen and helium, the second plasma applying RF power to the coil surrounding the processing chamber; RF to the substrate support member that supplies and supports the substrate
And c) exposing the dielectric layer to the first plasma and the second plasma, and then depositing a metal on the patterned dielectric layer. . 7. The method of claim 6, wherein said processing chamber is a pre-cleaning chamber. 8. The method of claim 6, wherein the first plasma is configured with argon as essential. 9. The method of claim 6, wherein the second plasma is comprised essentially of about 5% atomic hydrogen and about 95% helium atomic. 10. The method of claim 6, further comprising depositing a barrier layer on the patterned dielectric layer prior to depositing the metal. 11. The method of claim 6, wherein an RF bias applied to the substrate support member to generate the second plasma is smaller than an RF bias applied to the substrate support member to generate the first plasma. The described method. 12. The first plasma is generated with about 300 W of RF power applied to the coil and about 300 W of RF bias applied to the substrate support member.
The second plasma is applied to the induction coil at about 4
7. The method of claim 6, wherein the method is generated with 50 W of RF power and about 10 W of RF bias applied to the substrate support member. 13. The method of claim 6, wherein an etching plasma is maintained in said processing chamber for about 60 seconds. 14. A method for improving metal deposition on a patterned dielectric layer on a substrate, the method comprising: a) the patterning in the processing chamber by a first plasma comprising argon. Cleaning the applied dielectric layer, wherein the first plasma is generated by applying RF power to a coil surrounding a processing chamber and applying an RF bias to a substrate support member supporting the substrate. B) cleaning the patterned dielectric layer in the processing chamber with a second plasma essentially comprising hydrogen and helium, wherein the second plasma comprises the coil surrounding the processing chamber; Supply of the RF bias to the substrate support member that supports the substrate by increasing the supply of the RF power to the substrate. C) depositing a barrier layer on said patterned dielectric layer after exposing said dielectric layer to said first plasma and said second plasma; and d. E.) Depositing a metal on said barrier layer. 15. The method of claim 14, wherein said processing chamber is a pre-cleaning chamber. 16. The method according to claim 16, wherein the second plasma has an atomic number of about 5%.
From about 100% hydrogen and from about 0% to about 95% atomic number
15. The method of claim 14, wherein the helium is essential. 17. The method according to claim 17, wherein the second plasma has an atomic number of about 5%.
15. The method of claim 14, wherein the hydrogen and hydrogen of about 95% helium are essential. 18. The method of claim 1, wherein the first plasma is generated with about 300 W of RF power applied to the coil and about 300 W of RF bias applied to the substrate support member, and the second plasma is applied to the coil. About 450W
RF power and about 10 W applied to the substrate support member
15. The method of claim 14, wherein the method is generated with an RF bias. 19. The method of claim 14, wherein an etching plasma is maintained in said processing chamber for about 60 seconds. 20. The method of claim 1, wherein the first plasma is about 0.8 mTorr.
The method of claim 14, wherein the second plasma is generated at a pressure in the processing chamber of about 80 mTorr.