KR100779337B1 - Method of making semiconductor devices - Google Patents

Method of making semiconductor devices Download PDF

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KR100779337B1
KR100779337B1 KR1020060080493A KR20060080493A KR100779337B1 KR 100779337 B1 KR100779337 B1 KR 100779337B1 KR 1020060080493 A KR1020060080493 A KR 1020060080493A KR 20060080493 A KR20060080493 A KR 20060080493A KR 100779337 B1 KR100779337 B1 KR 100779337B1
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South Korea
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diffusion barrier
plasma treatment
groove
reactive
sputtering
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KR1020060080493A
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Korean (ko)
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신종훈
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동부일렉트로닉스 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76855—After-treatment introducing at least one additional element into the layer
    • H01L21/76856—After-treatment introducing at least one additional element into the layer by treatment in plasmas or gaseous environments, e.g. nitriding a refractory metal liner
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32131—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by physical means only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric

Abstract

A method for manufacturing a semiconductor device is provided to enhance the accuracy of the semiconductor device by lowering resistivity of a diffusion barrier and reducing surface roughness of the diffusion barrier. An insulating layer is formed on a lower process substrate. A groove is formed on the insulating layer. A via-hole is formed at a part of the groove region. A diffusion barrier is formed on a surface of the lower process substrate including the via-hole and the groove. The diffusion barrier is sputter-etched by performing a reactive RF sputtering process. A process condition of the reactive RF sputtering includes RF power of an RF generator of 60W to 80W within a process chamber, He and H2 as plasma discharge gas, a plasma-processing time of 25 to 35 seconds, and internal chamber pressure of 9mtorr.

Description

반도체 장치 형성 방법{METHOD OF MAKING SEMICONDUCTOR DEVICES}Method of forming semiconductor device {METHOD OF MAKING SEMICONDUCTOR DEVICES}

도 1a 내지 1c는 반도체 소자 제조과정 중의 소자의 단면도이다.1A to 1C are cross-sectional views of devices during a semiconductor device manufacturing process.

도 2는 플라즈마 처리를 한 후의 확산방지막과 플라즈마 처리가 적용되지 않고 증착한 확산방지막의 표면저항변화에 대한 비교이다.2 is a comparison of the surface resistance change of the diffusion barrier film after the plasma treatment and the diffusion barrier film deposited without the plasma treatment.

도 3은 플라즈마 처리를 한 후의 확산방지막과 플라즈마 처리가 적용되지 않은 확산방지막의 표면거칠기에 대한 비교이다. 3 is a comparison of the surface roughness of the diffusion barrier film after the plasma treatment and the diffusion barrier film not applied to the plasma treatment.

본 발명은 반도체 제조 방법에 관한 것으로 보다 상세하게는, 듀얼 다마신(Dual Damascen) 배선 형성 기법에서 플라즈마 처리(Plasma Treatment)를 이용하여 확산방지막(Diffusion Barrier)의 비저항을 낮추는 반도체 배선 형성 기법에 관한 것이다.The present invention relates to a semiconductor manufacturing method, and more particularly, to a semiconductor wiring forming technique for lowering the specific resistance of a diffusion barrier using plasma treatment in a dual damascen wiring forming technique. will be.

반도체 제조 방법 중 구리 이중 다마신 배선 형성 기법에서 실리콘 산화막 등 절연막이 형성된 있는 반도체 소자에 비아홀(via hole) 혹은 컨택홀(contact hole) 이나 그루브를 형성한 후 확산방지막(Diffusion Barrier)을 증착한다. 이때, 상기 확산방지막은 확산방지막 위에 형성될 구리로 인한 구리 이온의 확산 방지 목 적으로 증착된다. 상기 확산방지막은 대체로 비저항이 높다. 따라서 접속부 저항이 높아지는 문제와 소자 내에 기생 커패시터 등의 영향으로 인한 알씨 딜레이(RC Delay)가 발생 된다. 상기 알씨 딜레이의 영향으로 반도체 소자의 응답속도가 늦어지거나 왜곡되는 문제가 있다.  In the method of forming a copper double damascene wire in a semiconductor manufacturing method, a via hole, a contact hole, or a groove is formed in a semiconductor device in which an insulating film such as a silicon oxide film is formed, and then a diffusion barrier is deposited. At this time, the diffusion barrier is deposited for the purpose of preventing the diffusion of copper ions due to the copper to be formed on the diffusion barrier. The diffusion barrier is generally high in resistivity. As a result, an increase in connection resistance and an RC delay are generated due to parasitic capacitors and the like. There is a problem that the response speed of the semiconductor device is slowed or distorted due to the delay of the RF delay.

본 발명은 이중 다마신공정 중 확산방지막의 비저항이 올라가 응답속도가 늦어지는 문제를 해결하기 위한 것으로, 플라즈마 처리를 이용하여 확산방지막의 비저항을 낮추는 반도체 장치 형성 방법을 제공하는 것을 목적으로 한다. An object of the present invention is to solve the problem that the specific resistance of the diffusion barrier film is increased during the dual damascene process, thereby slowing the response speed, and an object of the present invention is to provide a method of forming a semiconductor device which lowers the specific resistance of the diffusion barrier film using a plasma treatment.

상기 목적을 달성하기 위한 본 발명은 반도체 장치 형성 방법에 관한 것으로 기판에 절연층을 형성하는 단계; 절연층에 그루부(Groove) 및 그루브 영역 일부에 형성되는 비아홀을 형성하는 단계; 비아홀 및 그루부가 형성된 기판 표면에 확산방지막을 형성하는 단계; 상기 확산 방지막을 반응성 고주파 스퍼터링(Reactive RF Sputtering)에 의해 스퍼터 에칭하는 단계를 구비하여 이루어지는 것을 특징으로 한다.The present invention for achieving the above object relates to a method for forming a semiconductor device comprising the steps of: forming an insulating layer on a substrate; Forming a via hole formed in the groove and a part of the groove area in the insulating layer; Forming a diffusion barrier on a surface of the substrate on which the via hole and the groove are formed; And sputter etching the diffusion barrier layer by reactive RF sputtering.

또한, 상기 플라즈마 처리에는 물리적 기상증착(Physical Vapor Deposition; 이하 'PVD'라 칭함)이 응용된 스퍼터 에칭이 사용될 수 있다. In addition, the plasma treatment may be a sputter etching applied to the physical vapor deposition (hereinafter referred to as 'PVD').

또한, 상기 PVD기법은 반응성 고주파 스퍼터링(Reactive RF Sputtering)이고 플라즈마 처리를 위한 상기 고주파 스퍼터링 장비의 챔버(Chamber) 내에 조건들은, 고주파발생기의 고주파(RF)전력이 60W 내지 80W, 플라즈마 방전가스가 He 및 H2이 구비되고, 플라즈마 처리 시간이 25초 내지 35초, 압력이 9mtorr 내지 11mtorr이 될 수 있다. 이때, 상기 플라즈마 방전가스인 He 및 H2의 비율은 9:1이 될 수 있다.In addition, the PVD technique is reactive RF sputtering, and conditions within the chamber of the high frequency sputtering apparatus for plasma treatment include: high frequency (RF) power of the high frequency generator is 60W to 80W, and plasma discharge gas is He And H 2 is provided, the plasma treatment time may be 25 seconds to 35 seconds, the pressure may be 9 mtorr to 11 mtorr. In this case, the ratio of the plasma discharge gas He and H 2 may be 9: 1.

본 발명의 플라즈마 처리 후 확산방지막의 표면 거칠기는 2Å 내지 5Å 이 될 수 있다.After the plasma treatment of the present invention, the surface roughness of the diffusion barrier layer may be 2 kPa to 5 kPa.

이하, 첨부된 도면을 참조하여 본 발명에 따른 일 실시예를 통해 보다 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in more detail through an embodiment according to the present invention.

먼저 도 1a에서와 같이 반도체 기판에 이미 구리로 형성된 하부 도전 패턴(110)의 상면에 이온이동 방지를 위한 일종의 절연막, 가령 실리콘 질화막인 하부확산방지막(120)을 적층한다. 그리고, 하부확산방지막(120)에 층간 절연을 위한 절연판(130)을 적층한다. 그런다음, 절연판(130) 상면에 식각 과정중 식각의 제어를 위한 식각정지막(140)을 적층한다. 그런다음, 식각정지막(140) 상면에 두번째 다마신 공정의 배선과의 절연을 위한 절연막(150)을 적층한다. 상기 하부확산방지막(120), 절연판(130)과 식각정지막(140) 및 절연막(150)을 포함하는 것을 절연 층(190)이라 하겠다. First, as shown in FIG. 1A, a kind of insulating film for preventing ion migration, for example, a lower diffusion barrier 120, which is a silicon nitride layer, is stacked on an upper surface of a lower conductive pattern 110 formed of copper on a semiconductor substrate. In addition, an insulating plate 130 for interlayer insulation is laminated on the lower diffusion barrier layer 120. Then, the etch stop layer 140 for controlling the etching during the etching process is laminated on the insulating plate 130. Thereafter, an insulating film 150 for insulating the wiring of the second damascene process is stacked on the etch stop layer 140. The insulating layer 190 includes the lower diffusion barrier layer 120, the insulating plate 130, the etch stop layer 140, and the insulating layer 150.

상기 절연층(190)에 그루브 형성용 식각 공정과 비아홀 또는 컨택홀 공정을 실행하면 도 1b와 같이 공정기판에 그루부(160) 및 비아홀이 형성된 반도체 장치가 구비된다. 그런다음, 도 1c와 같이 상기 그루부(160) 주변에 일종의 도체막인 확산방지막(170) 증착 과정을 거친다. 증착 과정이나 증착 후에, 상기 확산방지막(170)에 플라즈마 처리를 거치게 된다. 상기 확산방지막(170)의 물질은 질화탄탈륨 또는 질화티타늄이 될 수 있다. 상기 플라즈마 처리에 사용되는 기법은 PVD기법 중에서 반응성 고주파 스퍼터링(Reactive RF Sputtering)기법이 될 수 있다. 반응성 고주파 스퍼터링 기법을 위한 장비는 챔버(Chamber) 내에서 방전가스인 수소와 헬륨을 구비한다. 타켓(Target)으로는 확산방지막을 포함하는 반도체 기판이 챔버 내에 구비되고 고주파와 방전가스가 플라즈마를 일으켜 확산방지막을 스퍼터링하면서 플라즈마 처리가 이루어질수 있게 된다. When the groove forming etching process and the via hole or contact hole process are performed on the insulating layer 190, as shown in FIG. 1B, the semiconductor device having the groove 160 and the via hole formed on the process substrate is provided. Then, as shown in FIG. 1C, the diffusion barrier layer 170, which is a kind of conductive layer, is deposited around the groove portion 160. After the deposition process or deposition, the diffusion barrier 170 is subjected to a plasma treatment. The material of the diffusion barrier 170 may be tantalum nitride or titanium nitride. The technique used for the plasma treatment may be a reactive RF sputtering technique among PVD techniques. Equipment for the reactive high frequency sputtering technique includes hydrogen and helium as the discharge gases in the chamber. As a target, a semiconductor substrate including a diffusion barrier layer is provided in a chamber, and a high frequency and discharge gas generate plasma to sputter the diffusion barrier layer so that plasma treatment may be performed.

이때, 도 2는 상기 플라즈마 처리를 한 확산방지막(210)과 플라즈마 처리가 적용되지 않은 확산방지막(220)의 증착과정에서 고주파 전력을 가변했을때 확산방지막의 표면저항변화를 비교한 것이다. 반응성 고주파 스퍼터링(Reactive RF Sputtering)을 하기 위한 플라즈마 처리 조건들은 고주파 전력을 20W 에서 100W 까지 가변하며, 방전가스로 He과 H2의 비율이 9:1, 처리시간이 30초, 압력이 10mtorr일때, 확산방지막의 저항변화를 기록한 선도이다. 도 2의 고주파전력이 60W 내지 80W 구간을 보면, 플라즈마 처리가 적용된 선도(210)가 플라즈마 처리가 적용되지 않은 선도(220)보다 고주파 전력에 관계없이 비저항이 낮아지는 것을 볼 수 있는데 이와 같은 이유는 플라즈마 처리 과정동안 확산방지막의 질소 함유량이 작아지기 때문이다. 상기와 같은 과정으로 플라즈마 처리를 통해 비저항을 낮추어 알씨 딜레이(RC Delay)를 줄일 수 있다.In this case, FIG. 2 compares the surface resistance change of the diffusion barrier film when the high frequency power is varied during the deposition process of the diffusion barrier film 210 subjected to the plasma treatment and the diffusion barrier film 220 to which the plasma treatment is not applied. Plasma treatment conditions for reactive RF sputtering vary the high frequency power from 20W to 100W, when the ratio of He and H 2 as discharge gas is 9: 1, the processing time is 30 seconds, and the pressure is 10 mtorr. This is a diagram recording the resistance change of the diffusion barrier. When the high frequency power of FIG. 2 is in the range of 60W to 80W, it can be seen that the resistivity lowered regardless of the high frequency power is higher than the diagram 210 to which the plasma treatment is not applied. This is because the nitrogen content of the diffusion barrier film is reduced during the plasma treatment process. In the same process as described above, a specific resistance may be lowered through plasma treatment to reduce an RC delay.

도 3은 상기 플라즈마 처리를 한 확산방지막(310)과 플라즈마 처리가 적용되지 않은 확산방지막(320)의 플라즈마 처리과정에서 고주파 전력을 가변했을때 표면거칠기의 비교표이다. 반응성 고주파 스퍼터링(Reactive RF Sputtering)을 하기위한 플라즈마 처리 조건들은 도 2의 조건과 같다. 도 3을 참조하면 플라즈마 처리가 적용된 선도(310)는 고주파 전력의 변화에 관계없이 일정한 평탄도를 유지하는 것을 볼 수 있다. 이와같은 이유는 플라즈마 처리 하는 동안 강력한 활성종들(radicals)과 이온들의 충격으로 표면거칠기가 감소 하는 것이다. 반면에 플라즈마 처리가 적용되지 않은 선도(320)는 표면의 평탄도가 고르지 않은 것을 볼수 있다. 이때, 플라즈마 처리된 확산방지막 선도(310)를 보면 표면거칠기는 2Å 내지 5Å내에 있게 된다.3 is a comparison table of surface roughness when the high frequency power is varied during the plasma processing of the diffusion barrier 310 treated with the plasma and the diffusion barrier 320 not subjected to the plasma treatment. Plasma treatment conditions for reactive RF sputtering are the same as those of FIG. 2. Referring to FIG. 3, it can be seen that the diagram 310 to which the plasma treatment is applied maintains a flatness regardless of a change in high frequency power. The reason for this is that the surface roughness is reduced by the impact of strong radicals and ions during plasma treatment. On the other hand, the diagram 320 without plasma treatment may be seen that the surface flatness is uneven. At this time, the surface roughness of the plasma treatment diffusion barrier film 310 is within 2 ~ 5Å.

다음으로 확산방지막의 표면에 금속을 형성 한다. 상기 금속은 주로 구리가 된다. 그런다음, 화학적 기계적 연마(CMP)를 실시하여 그루브 및 비아홀에 생성된 금속층을 남기고, 절연층 위쪽의 금속층을 제거하게 된다.Next, a metal is formed on the surface of the diffusion barrier. The metal is mainly copper. Then, chemical mechanical polishing (CMP) is performed to leave the metal layer formed in the grooves and via holes, and to remove the metal layer over the insulating layer.

본 발명은 상술한 특정의 실시예나 도면에 기재된 내용에 그 기술적 사상이 한정되지 아니하며, 청구범위에서 청구하는 본 발명의 요지를 벗어남이 없이 당해 발명이 속하는 기술분야에서 통상의 지식을 가진 자라면 누구든지 다양한 변형의 실시가 가능한 것은 물론이고, 그와 같은 변경은 본 발명의 청구범위 내에 있게 된다.The present invention is not limited to the technical spirit of the specific embodiments or drawings described above, and those skilled in the art without departing from the gist of the invention claimed in the claims Various modifications are possible, of course, and such changes are within the scope of the claims of the present invention.

본 발명의 효과로는 플라즈마 처리를 사용하여 확산방지막의 비저항을 낮추고 확산방지막의 표면거칠기를 완화하여 반도체 소자의 정밀도를 향상시키는 데 그 효과가 있다.The effect of the present invention is to lower the specific resistance of the diffusion barrier film and to reduce the surface roughness of the diffusion barrier film by using plasma treatment to improve the precision of the semiconductor device.

Claims (5)

삭제delete 하부 공정 기판에 절연층을 형성하는 단계;Forming an insulating layer on the lower process substrate; 상기 절연층에 그루부 및 그루브 영역 일부에 형성되는 비아홀을 형성하는 단계;Forming a via hole formed in the insulating layer and a part of the groove portion and the groove region; 상기 비아홀 및 그루부가 형성된 기판 표면에 확산방지막을 형성하는 단계; 및Forming a diffusion barrier on a surface of the substrate on which the via hole and the groove are formed; And 상기 확산 방지막을 반응성 고주파 스퍼터링(Reactive RF Sputtering)에 의해 스퍼터 에칭하는 단계를 포함하여 구성되는 것을 특징으로 하는 반도체 장치 형성 방법.And sputter etching the diffusion barrier layer by reactive RF sputtering. 제 2 항에 있어서, The method of claim 2, 상기 반응성 고주파 스퍼터링(Reactive RF Sputtering)의 공정 조건은 공정 챔버 내에 고주파발생기의 고주파(RF)전력이 60W 내지 80W, 플라즈마 방전가스로 He 및 H2이 구비되고, 플라즈마 처리 시간이 25초 내지 35초, 챔버(CHanmber)내의 압력이 9mtorr 내지 11mtorr인것을 특징으로 하는 반도체 장치 형성 방법.The process conditions of the reactive RF sputtering is a high frequency (RF) power of the high frequency generator in the process chamber 60W to 80W, He and H 2 as the plasma discharge gas is provided, the plasma treatment time is 25 to 35 seconds And the pressure in the chamber is 9 mtorr to 11 mtorr. 제 3 항에 있어서,The method of claim 3, wherein 상기 플라즈마 방전가스의 He 및 H2d의 비율은 9:1을 특징으로 하는 반도체 장치 형성 방법.And the ratio of He and H 2d of the plasma discharge gas is 9: 1. 제 4 항에 있어서,The method of claim 4, wherein 상기 플라즈마 처리 후 상기 확산방지막의 표면 거칠기는 2Å 내지 5Å 를 특징으로하는 반도체 장치 형성 방법.The surface roughness of the diffusion barrier film after the plasma treatment, characterized in that 2Å to 5Å.
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001085331A (en) 1999-05-11 2001-03-30 Applied Materials Inc Sequential sputter and reactive precleaning of via-hole and contact
US6423637B2 (en) 2000-06-29 2002-07-23 Hyundai Electronics Industries Co., Ltd. Method of manufacturing copper wiring in a semiconductor device
JP2003309170A (en) 2002-02-14 2003-10-31 Nec Electronics Corp Semiconductor device and manufacturing method therefor
KR20050007700A (en) * 2003-07-11 2005-01-21 동부아남반도체 주식회사 Semiconductor device and formation method of metal line in the semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001085331A (en) 1999-05-11 2001-03-30 Applied Materials Inc Sequential sputter and reactive precleaning of via-hole and contact
US6423637B2 (en) 2000-06-29 2002-07-23 Hyundai Electronics Industries Co., Ltd. Method of manufacturing copper wiring in a semiconductor device
JP2003309170A (en) 2002-02-14 2003-10-31 Nec Electronics Corp Semiconductor device and manufacturing method therefor
KR20050007700A (en) * 2003-07-11 2005-01-21 동부아남반도체 주식회사 Semiconductor device and formation method of metal line in the semiconductor device

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