JPH09212532A - Semiconductor integrated circuit layout method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To secure the relative accuracy of a device necessary for the characteristic of a circuit. SOLUTION: The maximum unit of cell arrangement, namely the maximum number of cells which can be arranged horizontally, within a given arranging area is obtained (101) and transistor data is divided in matching with the size of the arranging area (102). Then, elements are arranged under the restriction of arranging necessary cells to be in one horizontal line concerning one element, the restriction of arranging balance elements by gathering to be one element and the restriction of arranging at a distance longer than an adjacent cell string without fail though dealing with divided ones respectively to be one element concerning a divided element (103). In addition whether or not arrangement is completed is judged (104), the restrictions are gradually released for rearrangement (105 to 110) and the arranging area is increased (111) sucessively.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit layout method using a computer, and more particularly to a layout method in a master slice type semiconductor device.

[0002]

2. Description of the Related Art In recent years, in the field of semiconductor integrated circuits, there has been a remarkable reduction in the number of products of various types, and there is a demand for shortening the development and manufacturing period. Therefore, transistors, capacitors,
Prepare up to the element formation process such as resistance in advance,
After that, a so-called master slice method is adopted in which only the necessary wiring is performed to realize a semiconductor integrated circuit. Further, in order to shorten the development period, it is general to use a computer for the layout of the layout and wiring of the semiconductor integrated circuit.

A layout method of a master slice type semiconductor device using a conventional computer will be described below with reference to FIGS. 2 and 8.

In FIG. 2, 11 to 15 are transistors. Each of the transistors 11 to 15 has the following coordinates on the drawing.

Transistor 11: (x ₁₁ , y ₁₁ ) Transistor 12: (x ₁₂ , y ₁₂ ) Transistor 13: (x ₁₃ , y ₁₃ ) Transistor 14: (x ₁₄ , y ₁₄ ) Transistor 15: (x ₁₅ , y ₁₅ ) Here, the relationship between the position values of these coordinates is as follows.

X ₁₁ <x ₁₄ <x ₁₂ <x ₁₃ <x ₁₅ y ₁₄ = y ₁₅ <y ₁₁ = y ₁₂ <y ₁₃ The transistors 11 to 15 are elements (cells) corresponding to the transistors on the master slice. It is realized as an element by connecting a plurality of transistors in parallel, and the number required for each connection is two for the transistors 11, two for the transistors 12, six for the transistors 13, and two for the transistors 14. , The same 15 will be two.

FIG. 8 is a diagram showing a layout result of a conventional master slice type semiconductor device.

In FIG. 8, 21 to 44 are cells on the master slice. The elements on the circuit diagram allocated and allocated on the master slice are assigned the same reference numerals, and on the master slice, if they are composed of a combination of a plurality of elements, the circuit A symbol to that effect is added after the symbol in the figure. For example, since 6 cells are required for the element 13 on the master slice, the combination 13-1, 13-2, 1 of the transistor 13 on the master slice is shown in FIG.
It is described as 3-3, 13-4, 13-5, 13-6.

In the conventional layout method, the initial arrangement position is determined based on the relative position on the circuit diagram, and when an overlap occurs, the elements are moved and replaced, and the empty cells in the arrangement area. Repeat the arrangement so that At this time, in order to obtain the circuit characteristics, the cells must be arranged in a row in a row for one element, and elements that require further relative accuracy should be arranged in a row in a row as in the case of the one element. I had to do it.

The arrangement area is a cell 21 on the master slice.
, The transistor 13 has the largest y-coordinate on the circuit diagram.
The initial placement position is determined to be one of 1, 1, 25, 29, or 33. Similarly, the initial position of the transistor 13 is determined to be the cell 29 from the relative positional relationship of the x coordinates.

The transistor 13 requires six cells, and since it is one element, the six cells must be arranged in one horizontal row. However, in the current placement area, only four cells can be placed side by side on the master slice. Therefore, cells 37 to 44 are newly added as arrangement areas on the master slice so that 6 cells can be arranged in one row. by this,
The transistor 13 is arranged in the cells 21, 25, 29, 33, 37 and 41 on the master slice.
Other transistors 11, 12 and transistor 1
4 and 15 are processed in the same manner, but since each is a balance element that requires relative accuracy,
Must be arranged in a horizontal row. As a result of such processing, the placement result shown in FIG. 8 is obtained.

[0012]

However, when such a conventional semiconductor integrated circuit layout method is used, the necessary relative accuracy and the like can be retained due to the characteristics of the circuit, but the layout is wasteful. , Fig. 8
Also in, the cells 24 existing on the master slice,
28, 32, 36, 38, 39, 40, 42, 43, 44 are not used.

The present invention is intended to solve the problems in the conventional method as described above, and it is possible to maintain the required relative accuracy and the like in view of the characteristics of the circuit while performing an efficient layout. An object is to provide a semiconductor integrated circuit layout method.

[0014]

In order to solve the above-mentioned problems, the semiconductor integrated circuit layout method of the present invention uses the maximum unit of cell arrangement within a given arrangement area, that is, the maximum number of cells that can be arranged side by side. , The step of dividing the transistor data according to the size of the arrangement area, the constraint of arranging the necessary cells in one horizontal row for one element, and the balance element as one element collectively. Regarding the handling and placement constraints and the divided elements, each divided element is treated as one element, but the constraint is to place them at least in adjacent cell columns, and to place them under these constraints. A step of determining whether or not is completed, a step of gradually releasing the constraint and re-arranging, and a step of increasing the arrangement area,
It is characterized by performing sequential processing using a computer.

As a result, the layout shape suitable for the layout area can be determined, and the restrictions on the layout are released one by one, so that the layout restrictions for maintaining the circuit characteristics are set within the layout area. You can protect to the maximum. In other words, it is possible to maintain the required relative accuracy and the like in terms of the characteristics of the circuit while performing an efficient layout.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a semiconductor integrated circuit layout method according to the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing a processing flow in one embodiment of the present invention. In FIG. 1, 101 is a step of obtaining the maximum number of cells that can be arranged side by side, which is the maximum unit of cell arrangement, 102 is a step of dividing the elements to be arranged based on the maximum number of cells, and 103 is a fixed constraint. While arranging the cells, 104 is a step of judging whether the arrangement is successful, 105 is a step of releasing restrictions on the arrangement of elements (balance elements) requiring relative accuracy, 10
6 is a step of arranging in the same manner as step 103, 107 is a step of deciding whether or not the arrangement is successful similarly to step 104, 10
8 is a step of releasing restrictions on arrangement so that individual elements can be divided into arrangement cell units, 109 is a step of performing arrangement similar to step 103, and 110 is a step of determining whether or not arrangement is successful similarly to step 104. , 111 is a step of increasing the arrangement area.

FIG. 2 is a circuit diagram for explaining this embodiment. In FIG. 2, 11 to 15 are transistors.

FIG. 3 is a diagram showing the placement result in step 103, and 21 to 32 are cells on the master slice.

The elements corresponding to the elements on the circuit diagram allocated and arranged on the master slice are designated by the same reference numerals,
Further, on the master slice, when it is composed of a combination of a plurality of elements, the corresponding reference numeral is added after the reference numeral on the circuit diagram. For example, for the element 11, four cells are required on the master slice, and therefore, they are described as combinations 13-1, 13-2, 13-3, and 13-4 on the master slice in FIG. ing.

FIG. 4 is a diagram showing the placement result in step 106. The reference numerals in FIG. 4 correspond to those in FIG. 3 and are given the same reference numerals.

FIG. 5 is a diagram showing the placement result in step 109. Reference numerals in FIG. 5 are the same as those in FIG.

FIG. 6 is a diagram showing another example of the placement result in step 106. In FIG. 6, reference numerals 21 to 32 are cells on the master slice, and other elements are denoted by the same reference numerals as those in FIG.

FIG. 7 is a diagram showing another example of the placement result in step 109. The reference numerals in FIG. 7 correspond to those in FIG. 6 and are given the same reference numerals.

First, the present embodiment will be described with reference to FIGS. In FIG. 2, transistors 11 and 1
It is assumed that 2, 13, 14, and 15 require combinations of 2, 2, 4, 2, and 2 cells on the master slice, respectively.

In step 101, the maximum unit of cell arrangement, that is, the maximum number of cells that can be arranged side by side (M)
Get. This is obtained by checking the data in the area to be placed.

The area to be arranged in FIG. 3 is the area from cells 21 to 32 on the master slice. The maximum number of cells (M) that can be arranged side by side in this area is three.

In step 102, the elements to be arranged are divided based on the maximum number (M) of cells.

Transistors 11, 12, 14, 1 of FIG.
No. 5 requires two cells each, which is less than the maximum number of cells (M) of three, so that no particular processing is performed on these transistors 11, 12, 14, 15.

However, the transistor 13 requires four cells. If the number of cells required for each element exceeds the maximum number of cells, division processing is performed. The cells required for the element are divided by the maximum number of cells, and the quotient (Q) and the remainder (R) are obtained. Then, the elements are divided into Q elements that require M cells on the master slice and one element that requires R cells on the master slice. The transistor 13 is divided into one element that requires three cells on the master slice and one element that requires one cell on the master slice.

The placement is performed in step 103. Step 1
The restrictions on the arrangement in 03 are the following items. (A) In one element, necessary cells are arranged in a row in a horizontal row. (B) The balancing elements are collectively treated and arranged as one element. (C) Regarding the divided elements, each of the divided elements is treated as one element, but they cannot be arranged apart from each other by more than adjacent cell rows.

FIG. 3 shows the placement result in step 103. The initial position arrangement is determined based on the relative position on the circuit diagram. When the overlap occurs, the elements are moved and replaced under the above-mentioned restrictions on the arrangement, and the arrangement is repeated so that the number of empty cells in the arrangement region is minimized. The transistor 13 has the largest arrangement y on the circuit diagram.
Since it has the coordinates, the initial arrangement position is determined in any of the cells 21, 25 and 22. Similarly, the initial position of the transistor 13 is determined to be the cell 29 based on the relative positional relationship of the x coordinates.

Since the transistor 13 is divided into the data of three cells and the data of one cell in the step 102, first, three data are arranged. Three cells are required next to the constraint (a), and 13-1 is set to the cell 21 to 1
3-2 is arranged in the cell 25, and 13-3 is arranged in the cell 29. Further, due to the constraint (c), since 13-4 can be arranged only in the adjacent cell column, the cells 22 and 2 can be arranged.
It can only be placed in either 6, 30 or 30. Here, assuming that left-justification is arranged in principle, 13-4
Are placed in the cell 22. Next, the transistors 11 and 12 are arranged. Since this element requires relative accuracy due to its characteristics,
Designated as a balancing element. Therefore, it must be treated as one element due to the constraint (b).
That is, four cells are required in the horizontal direction. If the placement is determined in the same manner as the transistor 13, the placement cannot be performed because the placement area is exceeded as shown in FIG. The same applies to the transistors 14 and 15.

In step 104, the condition of FIG. 3 is checked and it is found that the placement is not possible within the placement area.
Since the arrangement is not completed, the process proceeds to step 105.

In step 105, the restrictions on the arrangement of the balance elements are released. That is, the constraint (b) in step 103 is removed, and the element can be divided. However, because of the effect of the constraint (c), it is inevitable that the adjacent cell rows cannot be arranged apart from each other.

In step 106, the transistors 11, 12 and the transistor 14, which have exceeded the arrangement region,
Placement is performed centering on 15 according to the same procedure as in step 103 under the new placement constraint. FIG. 4 shows the arrangement result. In FIG. 4, no matter how the transistor 15 moves, it cannot be arranged unless it exceeds the arrangement region.

In step 107, the state shown in FIG. 4 is checked and it is found that the placement cannot be performed within the placement area. Since the arrangement is not completed, the process proceeds to step 108.

In step 108, the restriction on the arrangement of one element is released. That is, the constraint (a) is removed, and
It can be divided into cells. However, since the constraint (c) is still in effect, it is inevitable that the adjacent cell rows cannot be arranged apart from each other.

In step 109, the transistor 15 which has exceeded the placement region is placed by the same procedure as in step 103 under the new constraint. FIG. 5 shows the arrangement result.

In step 110, the state shown in FIG. 5 is checked and it is determined that the arrangement is completed. Next, another example of the embodiment will be described with reference to FIGS. 6 and 7. In FIG. 2, transistors 11, 12, 13, 14, and 15 are 2, 2, 6, and 2 on the master slice, respectively.
It is assumed that a combination of 1 and 2 cells is required. The arrangement result FIG. 6 can be obtained by sequentially performing the steps 101 to 110 as in the first embodiment.

In step 110, the state of FIG. 6 is checked and it is found that the placement is impossible. Since the arrangement is not completed, the process proceeds to step 111.

In step 111, the arrangement area is increased. Since it was found in step 110 that the arrangement cannot be performed, the arrangement cannot be performed as it is no matter how many times the processing is repeated.
Therefore, the arrangement area will be expanded. The cells 33, 34, 35, and 36 on the master slice are registered as cells that can be newly arranged, and the processes from step 101 to step 110 are sequentially performed. FIG. 7 shows the result.

Here, FIG. 8 which is the arrangement result by the conventional method and FIG. 7 which is the arrangement result of the second embodiment of the present invention.
Try to compare. Since the element such as the transistor 13 that requires six cells on the master slice is divided in advance according to the size of the arrangement region, the element on the master slice can be used without waste. Further, the transistors 11 and 12 and the transistors 14 and 15, which require relative accuracy, that is, the balance elements, can be efficiently arranged in a shape in which a sufficient distance between cells is maintained to maintain the accuracy. Further, even in a standard cell type semiconductor integrated circuit in which these layout results are registered and reused, since the layout shape as a whole is close to a rectangle, there is little waste and it is very easy to use.

[0044]

According to the present invention, the transistor data is divided in accordance with the size of the arrangement area, and the constraint that the necessary cells are arranged in one horizontal row for one element and the balance element is collectively set as one element. Regarding the constraint that it is handled as an element and the divided element, each divided element is treated as one element, but it cannot be placed apart from each other by more than adjacent cell rows. If the processing cannot be done and the placement cannot be done, the constraints are released in sequence, and when the placement area is insufficient,
By gradually increasing the required area and repeating the placement, it is possible to achieve a compact placement within the specified placement area, and to improve the relative accuracy of the circuit characteristics due to the placement distance between the elements or cells increasing. A semiconductor integrated circuit layout method capable of suppressing deterioration to a minimum can be provided.

[Brief description of drawings]

FIG. 1 is a process flow chart for explaining an embodiment of a semiconductor integrated circuit layout method according to the present invention.

FIG. 2 is a circuit diagram for explaining an embodiment of the present invention.

FIG. 3 is a diagram showing an arrangement result in step 103 in the processing flow shown in FIG.

FIG. 4 is a diagram showing an arrangement result in step 106 in the processing flow shown in FIG.

5 is a diagram showing a placement result in step 109 in the processing flow shown in FIG.

FIG. 6 is a diagram showing another example of the placement result in step 106 in the processing flow shown in FIG. 1.

FIG. 7 is a diagram showing another example of the placement result in step 109 in the processing flow shown in FIG.

FIG. 8 is a diagram showing an arrangement result by a conventional method.

[Explanation of symbols]

11-15 Transistors 11-1, 11-2 Combination on the master slice of the transistor 11 12-1, 12-2 Combination on the master slice of the transistor 12 13-1 to 13-6 Combination on the master slice of the transistor 13 14 -1, 14-2 Combination on the master slice of the transistor 14 15-1, 15-2 Combination on the master slice of the transistor 15 21 to 44 Cell on the master slice

Claims (4)

[Claims] 1. A step of performing placement under one or more constraints, a step of determining whether the placement is complete,
As a result of the determination, if the placement is not completed, the constraint is sequentially released, and if the placement is not completed even if all the constraints are released, the placement area is increased. And a semiconductor integrated circuit layout method comprising: 2. The number of cells required for one device is 1
The constraint of arranging them side by side in a row, the constraint of treating balanced elements as a single element and placing them, and the divided element is treated as one element for each divided element. 2. The semiconductor integrated circuit layout method according to claim 1, which has a constraint that they cannot be arranged apart from each other. 3. A step of dividing an element according to a size of a given placement area, a step of placing the element under one or more restrictions, and a step of determining whether or not the placement is completed. If, as a result of the determination, the placement is not completed, the step of sequentially releasing the restrictions is performed. If the placement is not completed even if all the restrictions are released, the placement area is increased. A method for laying out a semiconductor integrated circuit, comprising: 4. A required cell for one element is a horizontal line.
The constraint of arranging them side by side in a row, the constraint of treating balanced elements as a single element and placing them, and the divided element is treated as one element for each divided element. 4. The structure according to claim 3, which has a constraint that they cannot be arranged apart from each other.
A semiconductor integrated circuit layout method according to claim 1.