JP2671759B2 - Automatic layout method of semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for automatically laying out a semiconductor integrated circuit, and more particularly to a method for arranging logic cells suitable for layout design of a semiconductor integrated circuit having a high cell usage rate.

[0002]

2. Description of the Related Art In the layout process of a logic cell in the layout design of a semiconductor integrated circuit, the logic cell is moved or replaced in a layout target area by some method so as to satisfy an evaluation function indicating a layout constraint condition. . In the initial layout design method, the layout is executed while eliminating the overlap between the logic cells, and when the overlap of the logic cells is inevitable, the layout is restarted from the beginning, so that the layout design took a long time.

As an improvement of this, during the initial placement of logic cells and the movement and exchange of logic cells, overlapping of logic cells is allowed, and the degree of freedom of movement and exchange of logic cells is increased to reduce the placement processing time. Techniques have been adopted that reduce the number of local solutions (a state in which all logic cells cannot be arranged and are repeatedly moved and replaced). This improved layout method will be described with reference to FIG.

Here, as shown in FIG.
Consider a case where the six logic cells A to F shown in FIG. 4B are arranged on the chip 1 having the layout target cells 1a. The result of the initial placement is shown in FIG. As shown in the figure, as a result of the initial placement, overlap occurs between the logic cell A and the logic cell B and between the logic cell B and the logic cell F. Therefore, in FIG.
The logic cell A is moved and rearranged as shown in FIG. As a result of the rearrangement, a new overlap occurs between the logic cell A and the logic cell D. After that, the movement and the rearrangement are repeated until there is no overlap, that is, until the evaluation function is satisfied.

Even with the improved layout method described above, FIG.
There is a high possibility of falling into a local solution state in which the states shown in (c) to (d) are repeated. Therefore, in order to further shorten the placement processing time and prevent local solutions, the layout target area is divided into a plurality of areas, and when the logic cell is moved or exchanged between the areas, the area division is performed according to the progress of the placement processing. A method has been proposed in which the size is made fine and, at the same time, the overlapping condition of the logic cells is made stricter as the placement process progresses (JP-A-2-226744).

[0006]

In the above-mentioned conventional example,
Since all of them were moved and replaced regardless of the size and shape of the logic cell, for example, when executing a move or a replacement for a logic cell of a multi-cell configuration that has a large used area, In some cases, new logic cells overlap each other, and it takes a long time to place the logic cells, or the cell placement cannot be decided due to a local solution state. Therefore, an object of the present invention is to include a large logic cell or an odd-shaped logic cell, and even if the cell usage rate is high, it is possible to complete the layout in a short time without inducing a local solution. It is to provide an automatic layout method.

[0007]

An automatic layout method for a semiconductor integrated circuit according to the present invention classifies logic cells into a logic cell group according to at least one of the size and the shape before performing a layout process. An arrangement processing order is determined for the classified logic cell group, and the arrangement processing of the logic cells included in the logic cell group is performed in the ordered order.

[0008]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a flow chart showing a processing procedure of an embodiment of the present invention, and FIG. 2 is an explanatory view showing a concrete arrangement state of logic cells. As a specific example for this embodiment, a case will be described in which logic cells are classified into two according to their areas and the placement processing is performed in two stages.

First, conditions are set for classifying logic cells (step S1). Here, it is assumed that the logic cells A to F shown in FIG. 2A are arranged on a chip, and whether or not the logic cell area is 4 unit cells or more is set as a setting condition. Next, the logic cell area condition determined as the logic cell classification process is compared with the area of each logic cell (step S2). Here, as shown in FIG. 2B, the cells are classified into two, that is, a logic cell (group) having an area set to 4 unit cells or more and a logic cell (group) having an area less than 4 unit cells. .

Next, the arrangement processing order condition of the two logic cell groups classified according to the area of this logic cell is determined (step S3). Here, by arranging the logic cell group having a large logic cell area first, the logic cell having a large logic cell area is prevented from being moved or exchanged in the latter half of the arrangement process, thereby preventing the occurrence of a local solution. That is,
It is assumed that the logic cells belonging to the group are the targets of the first placement process and the logic cells belonging to the group are the targets of the second placement process. Then, the logic cell group is ordered according to the determined placement order condition (step S4). Here, the first processing order is assigned to the logical cell group of the group, and the second processing order is assigned to the logical cell group of the group.

Next, the placement processing is performed according to the determined placement processing order (steps S5 and S6). here,
As described above, the placement process of the logic cell group of the group having the large logic cell area is performed to determine the placement position [(c) of FIG. 2]. Then, the placement process of the logic cell group included in the group is performed to determine the placement position [(d) in FIG. 2]. Finally, it is determined whether the final arrangement condition is satisfied (step S7). If this arrangement condition is not satisfied, the condition for classifying the logic cells and the arrangement processing order of the logic cell group are changed, and the same processing is performed. Table 1 is a table for comparing the number of combinations of placement search between the case where the logic cells are divided into two groups as shown in FIG. 2 and the placement process is performed in two stages, and the processing method of the conventional example.

[0012]

[Table 1]

In this way, the number of wiring search combinations is drastically reduced to, for example, 1/104, so that the time required for automatic placement can be shortened by this embodiment. In addition, by arranging the logic cells having the larger size first, it is possible to prevent the logic cells from overlapping when they are moved or replaced. FIG. 3 shows the progress of processing when a layout design is performed using this embodiment, as compared with the case where the layout is designed in the conventional example. This data shows that the layout target cell is 2.5
The number of k cells and the number of logical cells is 822, and the cell usage rate is 86.5%. As can be seen from FIG. 3, in the conventional example, the placement position of the logic cell cannot be determined in the latter half of the placement process, and the local solution state is entered. On the other hand, in the case of the present embodiment, it is possible to completely determine the arrangement position of the logic cell without falling into the local solution state.

Although the preferred embodiment has been described above, the present invention is not limited to the above embodiment, and various modifications can be made within the scope of the present invention. For example, the grouping of the logic cells to be arranged is not according to the size but according to the outer shape (depending on whether the cell is a special shape cell like the logic cell A or a normal shape cell like the logic cell C). ), Or grouping according to size and outer shape. Further, as compared with the embodiment shown in FIG. 1, the condition setting for determining the arrangement processing order of step S3 and the determination of the arrangement processing order of the logic cell group of step S4 are performed before the classification of the logic cells of step S2. You can make changes. In the embodiment,
The placement process was performed in two steps, but the process steps can be further subdivided into three steps, four steps, and so on.

[0015]

As described above, the automatic layout method for a semiconductor integrated circuit according to the present invention classifies logic cells into logic cell groups according to their size and shape before performing layout processing and classifies them. Since the placement processing order is determined for the logic cell group and the placement processing of the logic cells included in the logic cell group is performed in the ordered order, according to the present invention, there is no overlap in the movement or replacement during the placement processing. The logic cells that are likely to occur can be arranged first. Therefore, for example, by arranging multi-cell logical cells having a large cell area at the beginning of the arranging process, it is possible to avoid overlapping of the cells, which is likely to occur due to movement or replacement of these logical cells. Therefore, it is possible to prevent the occurrence of the local solution state, which was difficult to avoid in the conventional example.

[Brief description of the drawings]

FIG. 1 is a flowchart showing a processing procedure according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram of a logic cell placement process for explaining a specific embodiment of an embodiment of the present invention.

FIG. 3 is a graph showing the progress of arrangement processing for explaining the effect of one embodiment of the present invention.

FIG. 4 is a logic cell layout diagram for explaining a layout processing method of a conventional example.

[Explanation of symbols]

1 Chip on which logic cells are arranged 1a Layout target cells provided in advance on the chip A to F Logic cells to be arranged

Claims (6)

(57) [Claims] 1. An automatic layout method of a semiconductor integrated circuit for arranging logic cells in a layout area, wherein the logic cells are classified into a plurality of groups according to at least one of size and shape thereof. The process steps, the ordering process step of ordering the classified logic cell groups, and the logic cell placement process step of placing the logic cells on the chip for each group according to the ordered order are performed in this order. A method for automatically laying out a characteristic semiconductor integrated circuit. 2. The semiconductor integrated circuit according to claim 1, wherein the plurality of groups follow the size of the logic cell, and a group including a logic cell having a larger group order is given a faster order. Automatic layout method. 3. The plurality of groups are a group including a special-shaped logic cell and a group including a general-shaped logic cell, and the group is ordered such that the group including the special-shaped logic cell is ordered earlier. 3. The automatic layout method for a semiconductor integrated circuit according to claim 1. 4. An automatic layout method of a semiconductor integrated circuit for arranging logic cells in a layout area, wherein ordering is performed on a plurality of groups into which logic cells are classified according to at least one of size and shape. A processing step, a classification processing step of classifying the logic cells into a plurality of groups according to at least one of size and shape thereof , and arranging the logic cells on a chip for each group according to an ordered order. A method for automatically laying out a semiconductor integrated circuit, comprising: performing a logic cell placement process and performing the process in this order. 5. The semiconductor integrated circuit according to claim 4, wherein the plurality of groups follow the size of logic cells, and a group including a logic cell having a larger group order is assigned a faster order. Automatic layout method. 6. The plurality of groups are a group including a special-shaped logic cell and a group including a general-shaped logic cell, and the group is ordered such that the group including the special-shaped logic cell is given an early order. The automatic layout method for a semiconductor integrated circuit according to claim 4, characterized in that: