JP2965259B2 - Arrangement method of semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial application field) The present invention relates to a method for arranging a semiconductor integrated circuit of a standard cell system or a gate array system, and in particular, arranges circuit blocks using a computer. The present invention relates to an arrangement method determined by an automatic arrangement process.

(Prior Art) A semiconductor integrated circuit device obtains a desired circuit operation by arranging a rectangular circuit block having a logical function and a storage function in a chip and wiring between input and output terminals of each circuit. is there.

FIG. 3 shows a schematic configuration of a semiconductor integrated circuit chip using a general standard cell system. The chip is divided into a plurality of circuit block rows 12, which are element areas, a wiring area 13 between each circuit block row, and an input / output circuit area 14 provided in the periphery. Two or three layers of metal wiring are used for wiring, and different layers are respectively allocated in the horizontal direction and the vertical direction.

In such a semiconductor integrated circuit device, when determining a layout by automatic layout processing using a computer,
It is an object to minimize the area of the integrated circuit and the length of each wiring. As an automatic placement method for this purpose, two circuit blocks on a chip are selected, it is determined whether or not the replacement of these circuit blocks improves the overall placement state, and the replacement of the cells is sequentially converged. There is a method of determining the arrangement position of all the cells by repeating the above steps.

However, this method has a problem that the final arrangement state depends on the initial arrangement state, the improvement converges before reaching the best arrangement state, and the local arrangement is likely to fall into a local minimum solution. .

This problem will be described more specifically with reference to FIG.
FIG. 4 (a) shows five circuit blocks 10 ₁ , 10 ₂ , 10 ₃ , 10 ₄ , 10
_{This is} the initial state arrangement of the chip composed of No. ₅ . These circuit blocks 10 are connected by wiring 11. If the length of the wiring connecting the two circuit blocks is 1, the total wiring length is 8. For the purpose of further shortening the wiring length, for example, as shown in FIG. 4 (b), two circuit blocks 10 ₃ and 10 ₄ are exchanged and moved. In this case, the total wiring length is 11, which is longer than the initial state. Therefore, the exchange movement of the circuit block is not adopted. Next, after returning the wiring of the circuit block to the initial state,
Even if another two circuit blocks are exchanged and moved in a similar manner, the total wiring length is not reduced. In practice, however, an arrangement as shown in FIG. 4 (c) is possible, which is the best arrangement state and the total wiring length is 5. That is, the circuit arrangement depends on the initial state, and the improvement converges before reaching the best arrangement state, falls into a local minimum solution, and the best arrangement state cannot be obtained globally. was there.

(Problems to be Solved by the Invention) As described above, in the conventional automatic arrangement method, the improvement of the arrangement state proceeds depending on whether or not local improvement is possible. There is a problem in that the improvement converges before reaching the best arrangement state, and the local arrangement tends to fall into a local minimum solution, so that the best arrangement state cannot be obtained from a global perspective.

[Configuration of the invention]

(Means for Solving the Problems) The present invention has been made in view of the above circumstances, and when arranging circuit blocks on a semiconductor substrate by an automatic arrangement process, the circuit blocks are exchanged and moved. The arrangement state is determined using a specific reference, and if the circuit arrangement state has not been improved, the exchange movement of the circuit block is continuously performed within a predetermined number of times, and if the circuit arrangement state has been improved, It is another object of the present invention to provide a method of arranging a semiconductor integrated circuit, characterized by registering the improved circuit arrangement state.

(Operation) As described above, according to the present invention, the circuit block is exchanged and moved from the initial state, and the circuit arrangement state is determined. Exchange movement can be performed.
Therefore, it is possible to escape from the local minimum solution and converge to an optimal circuit arrangement state by performing the continuous exchange movement of the circuit blocks a plurality of times.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows a processing procedure of the present arrangement method. After the start, first, an initial arrangement state is determined in the chip area (S1). Next, the number of times the circuit blocks are exchanged and moved continuously is set (S2). Next, the current arrangement state is evaluated (S3), and the number of times of replacement movement of the circuit block is compared with a set value (S4). If less than the set value, the process proceeds to step S5 and subsequent steps. Next, the circuit blocks are exchanged and moved, a new arrangement state is generated, and the state is evaluated (S5, S6,
S7). Next, it is determined whether or not the generated new arrangement state has been improved from the old arrangement state. If the new arrangement state has been improved, the registration of the new arrangement state and the number of circuit block replacement movements up to the present are reset (S10, S11). Next, when it is determined that the placement improvement cannot be obtained, the number of times of continuous replacement and movement of the circuit block is increased by one (S9), and the replacement and transfer of a plurality of cells are repeated to obtain further improvement. Such a new arrangement state is generated.

FIG. 2 is a layout diagram processed using the present layout method. Figure 2 (a) five circuit blocks 1 _1, 1 _2, 1 _3, 1 _4, 1 ₅
(S1). These circuit blocks 1 are connected by wiring 2. Next, the number of times the circuit blocks are exchanged and moved continuously is set. In this case, for example, the set value is set to 2 (S2).
Next, the current arrangement state is evaluated. As an evaluation method, for example, the total wiring length is adopted as a reference. If the length of the wiring connecting the two circuit blocks 1 is 1, the total wiring length is 8 (S3). Next, FIG. 2, as shown in (b) 2 single circuit block 1 _3, 1 ₄ select to exchange mobile (S5, S6). Next, this new arrangement state is evaluated. The total wiring length is 11 (S
7). Next, it is determined whether the new arrangement state has been improved from the old arrangement state. In this case, the total wiring length of the old layout is 8,
The total wiring length of the new arrangement is 11, and the circuit arrangement state is poor (S8). After returning the conventional circuit block 1 ₃ ends the process at this stage, 1 ₄ of the arrangement in the initial state, has been performed switched mobile relative to another of the two circuit blocks 1. In the present invention, even when the new arrangement state becomes worse than the old arrangement state, if the number of times of performing the exchange movement is equal to or less than the set value, the processing is continued. That is, in the present embodiment, since the set value is 2 and the current number of exchange movements is 1, the processing is continued (S
9). That is, the arrangement of FIG. 2 (b), the selected switched mobile circuit block 1 _2, 1 ₅ as shown in FIG. 2 (c) performing (S5, Sb). Next, this new arrangement state is evaluated.
The total arrangement length is 5 (S7). Next, it is determined whether the new arrangement state has been improved from the old arrangement state. In this case, the total wiring length of the old arrangement is 8, whereas the total wiring length of the new arrangement is 5, and the circuit arrangement state is improved (S8). Therefore, this new arrangement state is registered (S10), and the number of times of performing the exchange movement of the circuit block is reset (S11). However,
When the circuit blocks ₁₁ and ₁₅ are selected as shown in FIG. 2D from the arrangement state of FIG. 2B and the second replacement movement is executed, the total wiring length becomes 11 There is no improvement compared to the total wiring length 8 of the arrangement. Here, the number of times of performing the exchange movement is set in advance to two times, and thus the processing ends.
Since the arrangement state has not been improved, the state is returned to the initial arrangement state shown in FIG. 2A.

As described above, when the circuit block is arranged using the present arrangement method, a more optimal arrangement state can be generated without falling into a local minimum solution depending on the initial arrangement state. .

Note that the set value of the number of times the circuit block is exchanged is not necessarily limited to two, and may be three or more.

Although the total wiring length is used here as a method of evaluating the arrangement state, the evaluation function may be, for example, a degree of congestion of the wiring or how many wirings pass through a certain area.
For a standard cell type semiconductor integrated circuit, the total area of the chip can be used as the evaluation function.

〔The invention's effect〕

As described above, according to the present invention, in an arrangement method of determining the arrangement position of a circuit block by automatic processing using a computer, it is difficult to fall into a local minimum solution depending on an initial arrangement state, and a more optimal The arrangement state can be generated, and the integration degree of a standard cell type or gate array type semiconductor integrated circuit chip can be improved.

[Brief description of the drawings]

FIG. 1 is a flowchart showing a processing procedure of an embodiment of the present invention, FIG. 2 is a layout diagram processed by using the present layout method, and FIG. 3 is a schematic configuration of a general standard cell type semiconductor integrated circuit chip. FIG. 4 is a layout diagram processed using a conventional layout method. In the figure, 1 ... circuit block, 2 ... wiring, 10 ... circuit block, 11 ... wiring, 12 ... circuit cell row, 13 ... wiring area, 14 ... input / output circuit area.

Claims (1)

(57) [Claims] A first circuit arrangement state is generated by arranging circuit blocks on a semiconductor substrate by automatic arrangement processing.
A second step of generating a second circuit arrangement state by exchanging and moving some circuit blocks in the first circuit arrangement state; and a second step of generating a second circuit arrangement state. A step of comparing and evaluating the circuit arrangement state with a predetermined arrangement evaluation criterion; and, as a result of the comparison evaluation, (a) when the second circuit arrangement state is improved from the first circuit arrangement state (B) newly registering the second circuit arrangement state as a first circuit arrangement state, resetting the number of exchange movements so far, and returning to the second step; (b) the second circuit arrangement state; If the circuit arrangement state has not been improved from the first circuit arrangement state and the number of exchange movements so far is within a preset number, a part of the second circuit arrangement state Third circuit layout by exchanging and moving circuit blocks It generates a state, the second this newly
(C) the second circuit arrangement state is not improved from the first circuit arrangement state, and the number of exchange movements so far is previously determined. Returning the circuit arrangement state to the first circuit arrangement state when the set number of times has been reached.