JP3225823B2 - Semiconductor integrated circuit layout method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a layout method for a semiconductor integrated circuit using a computer, and more particularly to a layout method for a master slice type semiconductor device.

[0002]

2. Description of the Related Art In recent years, in the field of semiconductor integrated circuits, there has been a remarkable reduction in the number of products of various types, and there is a demand for shortening the development and manufacturing period. Therefore, transistors, capacitors,
Prepare up to the element formation process such as resistance in advance,
After that, a so-called master slice method is used, in which only necessary wiring is performed to realize a semiconductor integrated circuit. Further, in order to shorten the development period, a computer is generally used for the layout of the arrangement and wiring of the semiconductor integrated circuit.

A layout method of a master slice type semiconductor device using a conventional computer will be described below with reference to FIGS.

In FIG. 2, reference numerals 11 to 15 denote transistors. Each of the transistors 11 to 15 has the following coordinates on the drawing.

[0005] transistors _{11: (x 11, y 11} ) transistors _{12: (x 12, y 12} ) transistors _{13: (x 13, y 13} ) transistors _{14: (x 14, y 14} ) transistors _15: (x 15, y ₁₅ ) Here, the relationship between these coordinate position values is as follows.

X ₁₁ <x ₁₄ <x ₁₂ <x ₁₃ <x ₁₅ y ₁₄ = y ₁₅ <y ₁₁ = y ₁₂ <y ₁₃ The transistors 11 to 15 are elements (cells) corresponding to the transistors on the master slice. Are connected in parallel to realize an element, and the number required for each connection is two for the transistor 11, two for the transistor 12, six for the transistor 13, and two for the transistor 14. , And 15 are two.

FIG. 8 is a diagram showing a layout result of a conventional master slice type semiconductor device.

In FIG. 8, reference numerals 21 to 44 denote cells on the master slice. Elements on the circuit diagram allocated and arranged on the master slice are denoted by the same reference numerals, and on the master slice, if the element is configured by a combination of a plurality of elements, The reference numeral is attached to the end of the reference numeral in the figure. For example, since six cells are required for the element 13 on the master slice, the combinations 13-1, 13-2, 1 on the master slice of the transistor 13 are shown in FIG.
3-3, 13-4, 13-5, and 13-6.

In the conventional layout method, an initial arrangement position is determined based on a relative position on a circuit diagram, and when an overlap occurs, the elements are replaced and the empty cells in the arrangement area are replaced. Is repeated so as to minimize the number. At this time, in order to obtain circuit characteristics, the cells of one element must be arranged in a horizontal line, and elements requiring further relative accuracy are arranged in a horizontal line as in the case of the one element. I had to.

The arrangement area is the cell 21 on the master slice.
Since the transistor 13 has the largest y-coordinate value on the circuit diagram, the cell 2
The initial arrangement position is determined to be one of 1, 25, 29, and 33. Similarly, the initial position of the transistor 13 is determined by the cell 29 from the relative positional relationship of the x coordinate.

The transistor 13 requires six cells, and since it is one element, the six cells must be arranged in a horizontal row. However, in the current arrangement area, only four cells can be arranged side by side on the master slice. Therefore, cells 37 to 44 are newly added as arrangement areas on the master slice so that six cells can be arranged in one row. by this,
The transistor 13 is arranged in the cells 21, 25, 29, 33, 37, and 41 on the master slice.
Other transistors 11, 12 and transistor 1
4 and 15 are processed in the same manner, but since each is a balance element requiring relative accuracy,
Must be arranged in a horizontal row. As a result of such processing, the arrangement result shown in FIG. 8 is obtained.

[0012]

However, when such a conventional semiconductor integrated circuit layout method is used, necessary relative accuracy and the like can be maintained due to the characteristics of the circuit, but there is much waste in the layout. , FIG.
Also, in the cell 24, which exists on the master slice,
28, 32, 36, 38, 39, 40, 42, 43, and 44 are not used.

The present invention is intended to solve such a problem in the conventional method, and it is possible to maintain a necessary relative accuracy and the like in terms of circuit characteristics while performing an efficient layout. It is an object to provide a semiconductor integrated circuit layout method.

[0014]

In order to solve the above-mentioned problems, a semiconductor integrated circuit layout method according to the present invention provides a maximum unit of cell arrangement within a given arrangement area, that is, the maximum number of cells that can be arranged side by side. , The step of dividing the transistor data according to the size of the arrangement area, the constraint of arranging necessary cells in one horizontal line for one element, and the balance element as one element For the constraints to be handled and arranged, and for the divided elements, each of the divided elements is treated as one element, but the arrangement must always be arranged at least apart from the adjacent cell column, the process of arranging under these constraints, and the arrangement The step of determining whether or not has been completed, gradually releasing the constraint, the step of redoing the arrangement, including a step of increasing the arrangement area,
It is characterized by sequentially processing using a computer.

[0015] With this arrangement, the layout shape can be determined according to the layout area, and the layout restrictions are sequentially removed. I can keep it to the maximum. In other words, it is possible to maintain necessary relative accuracy and the like in terms of circuit characteristics while performing an efficient layout.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a semiconductor integrated circuit layout method according to the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing a processing flow in one embodiment of the present invention. In FIG. 1, 101 is a step of obtaining the maximum number of cells that can be arranged side by side, which is the maximum unit of cell arrangement, 102 is a step of dividing elements to be arranged based on the maximum number of cells, and 103 is a table that holds predetermined constraints. While arranging cells 104, determining whether the arrangement has succeeded, 105 ending a restriction on the arrangement of elements (balance elements) requiring relative accuracy, 10
6 is a step of performing arrangement in the same manner as in step 103; 107 is a step of determining whether or not the arrangement is successful in the same manner as in step 104;
8 is a step of releasing the restriction on arrangement so that individual elements can be divided into arrangement cell units, 109 is a step of performing arrangement as in step 103, and 110 is a step of determining whether or not the arrangement is successful as in step 104 , 111 are steps for increasing the arrangement area.

FIG. 2 is a circuit diagram for explaining this embodiment. In FIG. 2, 11 to 15 are transistors.

FIG. 3 is a view showing a result of the arrangement in the step 103. Reference numerals 21 to 32 denote cells on the master slice.

Elements corresponding to elements on the circuit diagram allocated and allocated on the master slice are denoted by the same reference numerals,
In addition, on the master slice, if it is composed of a combination of a plurality of elements, the corresponding symbol is attached after the symbol on the circuit diagram. For example, for the element 11, four cells are required on the master slice, and therefore, in FIG. 3, they are described as combinations 13-1, 13-2, 13-3, and 13-4 on the master slice. ing.

FIG. 4 is a diagram showing the arrangement result in step 106. 4 are assigned the same reference numerals as those in FIG.

FIG. 5 is a diagram showing the arrangement result in step 109. The reference numerals in FIG. 5 are the same as those in FIG.

FIG. 6 is a diagram showing another example of the arrangement result in step 106. In FIG. 6, reference numerals 21 to 32 denote cells on the master slice, and the other components are denoted by the same reference numerals as those in FIG.

FIG. 7 is a diagram showing another example of the arrangement result in the step 109. 7 are assigned the same reference numerals as those in FIG.

First, this embodiment will be described with reference to FIGS. In FIG. 2, transistors 11, 1
Assume that 2, 13, 14, 15 each require a combination of two, two, four, two, and two cells on the master slice.

In step 101, the maximum unit of cell arrangement, that is, the maximum number of cells that can be arranged side by side (M)
Get. This is obtained by examining the data of the area to be arranged.

The area to be arranged in FIG. 3 is an area from cells 21 to 32 on the master slice. The maximum number of cells (M) that can be arranged next to this area is three.

In step 102, the elements to be arranged are divided based on the maximum number (M) of cells.

The transistors 11, 12, 14, 1 in FIG.
No. 5 requires two cells each, which is less than the maximum cell number (M) of three. Therefore, no particular processing is performed on these transistors 11, 12, 14, and 15.

However, the transistor 13 requires four cells. If the number of cells required for each element exceeds the maximum number of cells, division processing is performed. The cells required for the element are divided by the maximum number of cells, and the quotient (Q) and the remainder (R) are obtained. Then, the element is divided into Q elements that require M cells on the master slice and one element that requires R cells on the master slice. In the case of the transistor 13, the element is divided into one element requiring three cells on the master slice and one element requiring one cell on the master slice.

In step 103, the arrangement is performed. Step 1
The restrictions on the arrangement at 03 are the following items. (A) In one element, necessary cells are arranged in one horizontal row. (B) The balance elements are collectively treated and arranged as one element. (C) Regarding the divided elements, each of the divided elements is treated as one element, but they cannot be arranged apart from adjacent cell columns without exception.

FIG. 3 shows an arrangement result in step 103. The initial position arrangement is determined based on the relative positions on the circuit diagram. When an overlap occurs, the elements are moved and replaced under the above-described restrictions on the arrangement, and the arrangement is repeated so that the number of vacant cells in the arrangement area is minimized. The transistor 13 has the largest arrangement y on the circuit diagram.
Since it has coordinates, an initial arrangement position is determined in any of the cells 21, 25, and 22. Similarly, the initial position of the transistor 13 is determined in the cell 29 from the relative positional relationship of the x coordinate.

Since the transistor 13 is divided into data of three cells and data of one cell in the step 102, first, three data are arranged. Restriction (a) requires three horizontal cells, and 13-1 is replaced with cell 21 by 1
3-2 is arranged in the cell 25, and 13-3 is arranged in the cell 29. Also, due to the restriction (c), the cell 13-2 can be arranged only in the adjacent cell column,
It can be arranged only in any one of 6 and 30. Here, 13-4
Is arranged in the cell 22. Next, transistors 11 and 12 are arranged. Since this element requires relative accuracy due to its characteristics,
Designated as a balance element. Therefore, it must be treated as one element due to the restriction (b).
That is, four cells are required in a row. When the arrangement is determined in the same manner as the transistor 13, the arrangement is not possible because the arrangement area is exceeded as shown in FIG. The same applies to the transistors 14 and 15.

In step 104, the state shown in FIG. 3 is checked, and it is found that the arrangement cannot be performed in the arrangement area.
Since the arrangement has not been completed, the process proceeds to step 105.

In step 105, the restriction on the arrangement of the balance element is released. That is, the restriction (b) in the step 103 is released, and division can be performed for each element. However, due to the effect of the constraint (c), the cells cannot always be arranged more than adjacent cell rows.

In step 106, the transistors 11, 12 and 14,
Arrangement is performed in the same manner as in step 103 under the new arrangement constraint, centering on 15. FIG. 4 shows the arrangement result. In FIG. 4, no matter how the transistor 15 moves, the transistor 15 cannot be arranged unless it exceeds the arrangement region.

In step 107, the state shown in FIG. 4 is checked, and it is found that the arrangement cannot be made in the arrangement area. Since the arrangement has not been completed, the process proceeds to step 108.

In step 108, restrictions on the arrangement of one element are released. That is, the constraint (a) is released, and
Division into cells is possible. However, since the effect of the constraint (c) is still in effect, it is not always possible to dispose the cells more than adjacent cell rows.

In step 109, the arrangement is performed by the same procedure as in step 103 with the new restrictions placed on the transistor 15 which has exceeded the arrangement area. FIG. 5 shows the arrangement result.

In step 110, the state shown in FIG. 5 is checked, and it is determined that the arrangement is completed. Next, another example of the embodiment will be described with reference to FIGS. In FIG. 2, transistors 11, 12, 13, 14, and 15 are 2, 2, 6, and 2, respectively, on the master slice.
Assume that a combination of two cells is required. By sequentially executing the steps 101 to 110 in the same manner as in the first embodiment, the arrangement result FIG. 6 can be obtained.

In step 110, the state shown in FIG. 6 is checked, and it is found that the arrangement cannot be performed. Since the arrangement has not been completed, the process proceeds to step 111.

In step 111, the arrangement area is increased. Since it was found that the arrangement was not possible in step 110, the arrangement could not be performed even if the processing was repeated many times.
Therefore, the arrangement area is expanded. The cells 33, 34, 35, and 36 on the master slice are registered as cells that can be newly arranged, and the processing from step 101 to step 110 is sequentially performed. FIG. 7 shows the result.

Here, FIG. 8 showing the arrangement result by the conventional method and FIG. 7 showing the arrangement result of the second embodiment of the present invention.
Try to compare. Elements such as the transistor 13 that require six cells on the master slice are divided in advance according to the size of the arrangement region, so that elements on the master slice can be used without waste. Also, the transistors 11 and 12 and the transistors 14 and 15, which require relative accuracy, that is, the balance elements, can be efficiently arranged in a shape that maintains a sufficient distance between cells to maintain the accuracy. Furthermore, even in a standard cell type semiconductor integrated circuit in which these arrangement results are registered and reused, the overall arrangement shape is close to a rectangle, so that there is little waste and it is very easy to use.

[0044]

According to the present invention, the transistor data is divided in accordance with the size of the arrangement area, the necessary cells are arranged in one horizontal row for one element, and one element is collectively arranged for the balance element. Constraints to be treated and arranged as elements, and for divided elements, each of the divided elements is treated as one element, but cannot be arranged at a distance of more than adjacent cell columns, and When processing is performed and placement is not possible, constraints are sequentially released, and when the placement area is insufficient,
By gradually increasing the required area and repeating the arrangement, a compact arrangement within the defined arrangement area is possible, and the relative accuracy of the circuit characteristics due to the separation distance between elements or cells is increased. A semiconductor integrated circuit layout method capable of minimizing deterioration can be provided.

[Brief description of the drawings]

FIG. 1 is a processing flowchart for explaining an embodiment of a semiconductor integrated circuit layout method according to the present invention;

FIG. 2 is a circuit diagram illustrating an embodiment of the present invention.

FIG. 3 is a view showing an arrangement result in a step 103 in the processing flow shown in FIG. 1;

FIG. 4 is a view showing an arrangement result in step 106 in the processing flow shown in FIG. 1;

FIG. 5 is a view showing an arrangement result in step 109 in the processing flow shown in FIG. 1;

FIG. 6 is a view showing another example of the arrangement result in step 106 in the processing flow shown in FIG. 1;

FIG. 7 is a view showing another example of the arrangement result in step 109 in the processing flow shown in FIG. 1;

FIG. 8 is a diagram showing an arrangement result by a conventional method.

[Explanation of symbols]

11-15 Transistors 11-1 and 11-2 Combination of transistors 11 on master slice 12-1 and 12-2 Combination of transistors 12 on master slice 13-1 to 13-6 Combination of transistors 13 on master slice 14 -1,14-2 Combination of transistor 14 on master slice 15-1,15-2 Combination of transistor 15 on master slice 21-44 Cell on master slice

Claims (4)

(57) [Claims] A step of performing placement under one or more constraints; determining whether the placement is complete;
As a result of the determination, when the arrangement is not completed, a step of sequentially releasing the restrictions, and a step of increasing the arrangement area when the arrangement is not completed even if all the restrictions are released And a layout method for a semiconductor integrated circuit. 2. A required cell for one element is set to one side.
Constraints to be arranged in rows, constraints to balance elements as a single element and arrangement, and for split elements, each split is treated as one element, but must always be at least 2. The layout method for a semiconductor integrated circuit according to claim 1, wherein there is a restriction that the semiconductor integrated circuit cannot be arranged apart from each other. 3. A step of dividing an element according to the size of a given arrangement area, a step of performing arrangement under one or more restrictions, and a step of judging whether or not the arrangement is completed. And, as a result of the determination, when the arrangement is not completed, sequentially releasing the restrictions, and when the arrangement is not completed even after all the restrictions are released, the arrangement area is increased. A semiconductor integrated circuit layout method. 4. A required cell for one element is set to one side.
Constraints to be arranged in rows, constraints to balance elements as a single element and arrangement, and for split elements, each split is treated as one element, but must always be at least 4. The apparatus according to claim 3, wherein the apparatus has a restriction that the apparatus cannot be located apart from each other.
14. A semiconductor integrated circuit layout method according to claim 1.