JPH09205203A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress a sub-threshold coefficient and the leakage current of a semiconductor device which is operated at a low, voltage. SOLUTION: A gate insulation film 3 is formed on the surface of a semiconductor substrate 1 and a silicon thin film 5 is formed on the gate insulation film 3. Then, a P-type impurity is ion-implanted to the silicon thin film 5 and the substrate 1 is heat-treated at 700-900 deg.C, thus forming the silicon thin film 5 into Ptype. Then, a silicide film 6 is formed on the silicon thin film 5 and a gate electrode is subjected to patterning. Then, 5-1,000Å CVD insulation film 7 is formed on the entire surface of the semiconductor substrate 1. Then, an impurity is ion-implanted to the surface of the semiconductor substrate 1 with the gate electrode as a mask, thus forming a source/drain region 8.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect semiconductor device capable of low voltage operation and a method of manufacturing the same.

[0002]

2. Description of the Related Art FIG. 2 shows a final sectional view of a semiconductor device manufactured by a conventional manufacturing method. A gate insulating film 103 is formed on the N-type semiconductor region on the surface 102 of the semiconductor substrate by thermal oxidation.
To form Channel doping 104 is performed to the N-type semiconductor region through the gate insulating film. A silicon thin film 105 is deposited on the gate insulating film by a CVD method, P-type impurity boron is ion-implanted, and then heat treatment is performed to make the silicon thin film P-type. Further, a silicide film 106 is deposited on the polysilicon thin film, the photoresist is patterned, and the silicon thin film and the silicide film are etched at the same timing to form a gate electrode. Next, after the surface of the semiconductor substrate is thermally oxidized to form an oxide film, impurities are ion-implanted using the gate electrode as a mask to form the source / drain regions 108. Then, a BPSG interlayer film 109 is formed on the entire surface. This interlayer film is formed by, for example, the CVD method or the like, and is subsequently flattened by heat treatment. Then, the interlayer film is selectively etched and heat-treated to form contact holes communicating with the source / drain regions and the gate electrode. Subsequently, a metal material or the like is formed on the entire surface by vacuum evaporation or sputtering, and then photolithography and etching are performed to form a patterned metal wiring 110. Finally, the entire substrate is covered with a surface protective film.

[0003]

A portable device or a desktop device usually uses a battery as a power source. From the viewpoint of device miniaturization and power saving, for example, the power supply voltage (1.
An increasing number of devices are required to operate at about 5V. Therefore, low-voltage operation ICs are listed as an important development item.

In order to lower the operating voltage, it is necessary to keep the threshold voltage of the MOS transistor low. However, if the threshold voltage of the MOS transistor is lowered to about 0.5V required for 1.5V operation,
There is a problem or a problem that the leak current of the transistor increases. If the leak current increases, there is a problem in that the battery is exhausted rapidly even if a portable device using the battery is not operated, and the battery runs out quickly.

However, in the above semiconductor manufacturing method, since the oxide film is formed by thermal oxidation before the source / drain ion implantation, the process temperature is high, and boron in the P-type polysilicon becomes a silicide film. The concentration in the polysilicon becomes low due to diffusion. In such a gate electrode field-effect transistor, a depletion layer is formed in the gate electrode, so that the threshold voltage varies,
The channel conductance becomes small and the leak current becomes large.

[0006]

Means for Solving the Problems In order to solve the above problems, the following manufacturing means were taken. That is, (1) a gate insulating film is formed on the surface of a semiconductor substrate, a gate electrode is patterned and formed on the gate insulating film, and a film thickness of 5 to 5 is formed on the entire surface of the semiconductor substrate at a temperature of 850 ° C. or less. A 1000 Å CVD insulating film was formed, and impurities were ion-implanted into the surface of the semiconductor substrate using the gate electrode as a mask to form source / drain regions.

(2) For patterning the gate electrode, a silicon thin film is formed on the gate insulating film, P-type impurities are ion-implanted into the silicon thin film, and the semiconductor substrate is heated at a temperature of 700 to 900 ° C. By heat-treating, the silicon thin film was made P-type, and a silicide film was formed on the silicon thin film.

(3) The source / drain regions are 80
It was activated by a short time heat treatment within 3 minutes at a temperature of 0 to 1050 ° C. (4) A method of manufacturing a semiconductor device, wherein a P-type insulated gate field effect transistor and an N-type insulated gate field effect transistor are integrated in an N-type semiconductor region and a P-type semiconductor region provided on a surface of a semiconductor substrate, respectively. A gate insulating film is formed on the surface of the semiconductor substrate, a silicon thin film is formed on the gate insulating film, P-type impurities are ion-implanted into the silicon thin film on the N-type semiconductor region, and the P-type semiconductor region is formed. N-type impurities are ion-implanted into the upper silicon thin film, and the semiconductor substrate is heat-treated at a temperature of 700 to 900 ° C. to make the silicon thin film P-type and N-type. Forming a silicide film, selectively etching the silicon thin film and the silicide film at the same time to form a gate electrode on the gate insulating film,
A CV having a film thickness of 5 to 1000Å is formed on the entire surface of the semiconductor substrate.
A D insulating film is formed, P-type impurities are ion-implanted into the surface of the N-type semiconductor region using the gate electrode as a mask to form source / drain regions, and the P-type semiconductor region surface is formed using the gate electrode as a mask. Source / drain regions were formed by ion implantation of N-type impurity phosphorus.

(5) In the step of forming the source / drain regions, the source / drain regions are formed by 800 to 10
It was formed by activation by short-time heat treatment within 3 minutes at a temperature of 50 ° C. (6) A gate insulating film provided on a semiconductor substrate, a gate electrode provided on the gate insulating film, the gate electrode including a plurality of layers of P-type and N-type polysilicon thin films and conductor thin films, and both sides of the gate electrode. Of the P-type and N-type polysilicon thin films, the source-drain regions being provided on the surface of the semiconductor region so as to be separated from each other, and a voltage is applied between the conductor thin film and the semiconductor substrate. At this time, the P-type and N-type polysilicon thin films have a sufficient amount of impurity concentration that a depletion layer is not formed.

(7) The P-type polysilicon thin film has a P-type impurity concentration of 2E19 atom / cm ³ or more and the N-type
-Type polysilicon thin film with N-type impurity concentration of 2E19ato
m / cm ³ or more was included. (8) A method of manufacturing a CMOS semiconductor device, wherein a P-type insulated gate field effect transistor and an N-type insulated gate field effect transistor are integrated in an N-type semiconductor region and a P-type semiconductor region provided on a surface of a semiconductor substrate, respectively. Forming a gate insulating film on the surface of the semiconductor substrate, ion-implanting N-type impurities into the surface of the N-type semiconductor region to form a channel dope region, and ion-implanting P-type impurities into the surface of the P-type semiconductor region. A channel dope region is formed, a silicon thin film is formed on the gate insulating film, P-type impurities are ion-implanted into the silicon thin film on the N-type semiconductor region, and silicon on the P-type semiconductor region is formed. N-type impurities are ion-implanted into the thin film, and the semiconductor substrate is heat-treated at a temperature of 700 to 900 ° C. And N-type, a silicide film is formed on the silicon thin film, the silicon thin film and the silicide film are selectively etched simultaneously to form a gate electrode on the gate insulating film, and a film is formed on the entire surface of the semiconductor substrate. Forming a CVD insulating film having a thickness of 5 to 1000Å, forming source / drain regions by ion-implanting P-type impurities into the surface of the N-type semiconductor region using the gate electrode as a mask, and using the gate electrode as a mask The P
Source / drain regions were formed by ion-implanting N-type impurity phosphorus on the surface of the type semiconductor region, and the source / drain regions were activated by a short-time heat treatment at a temperature of 800 to 1050 ° C. for 3 minutes or less.

(9) In the step of forming the channel-doped region, the channel-doping species and the ion-implantation acceleration energy are 30 KeV or less for N-type impurities and 70 KeV or less for arsenic and 70 KeV for BF ₂ for P-type impurities.
It was as follows. (10) In the step of forming the channel dope region, a P-type impurity BF ₂ is ion-implanted on the entire surface of the semiconductor substrate, and then an N-type impurity phosphorus is ion-implanted on the surface of the N-type semiconductor region to form the channel dope region. .

(11) In the method of manufacturing a CMOS semiconductor device, a silicon thin film is formed on the gate insulating film, P-type impurities are ion-implanted into the silicon thin film, and the semiconductor substrate is heated to 700 to 900 ° C. By heat-treating at a temperature, the silicon thin film is made P-type, a silicide film is formed on the silicon thin film, and the silicon thin film and the silicide film are simultaneously selectively etched to form a gate electrode on the gate insulating film. Then, an insulating film is formed on the entire surface of the semiconductor substrate at a temperature of 800 to 1050 ° C. in an oxygen atmosphere for a short time within 3 minutes, and an N-type impurity is ion-deposited on the surface of the P-type semiconductor region using the gate electrode as a mask. By implanting, the source / drain regions are formed and at the same time, ions are implanted into the silicide film, and the gate electrode is used as a mask Then, P-type impurities are ion-implanted into the surface of the N-type semiconductor region to form source / drain regions.
At the same time, it is activated and formed by heat treatment at a temperature of 50.degree.
The N-type silicon thin film was changed into the N-type silicon thin film by diffusing N-type impurities from the ion-implanted silicide film to the silicon thin film below the silicide film.

(12) A semiconductor device in which the P-type insulated gate field effect transistor and the N-type insulated gate field effect transistor are integrated in the N-type semiconductor region and the P-type semiconductor region provided on the surface of a semiconductor substrate, respectively. A gate insulating film having a thickness of 30 to 200 Å was formed on the surface of the semiconductor substrate, and the minimum length of the gate electrode formed on the gate insulating film was 1.0 μm.

(13) In a semiconductor manufacturing method in which a P-type well layer and an N-type well layer are formed on a semiconductor substrate using one mask, the N-type well layer is formed after the P-type well layer is formed. (14) A silicon oxide film and a silicon nitride film are sequentially formed on a semiconductor substrate, the silicon nitride film is selectively removed by a photomask process to define a region of the P well layer, and a P-type impurity is added to the semiconductor. Ion implantation is performed on the substrate to form a silicon oxide film in the P well region where the silicon nitride film is removed, and the silicon nitride film is removed to define an N well layer region, and N type impurities are added to the semiconductor substrate. Ions are implanted, and the semiconductor substrate is heat-treated to diffuse and activate impurities.

[0015]

EXAMPLE A first example of a semiconductor manufacturing method according to the present invention will be described in detail. A process of forming a PMOS transistor having a P ⁺ polycide gate structure will be described with reference to FIG.
In step A, N-type impurities such as phosphorus are ion-implanted into the surface of the P-type silicon substrate 1 and heat-treated at 1150 ° C. to diffuse and activate the implanted impurity phosphorus, and the N-well layer 2 is formed as shown in the figure. (N-type silicon substrate may be used instead of forming the N-well layer on the P-type silicon substrate). A gate oxide film 3, for example 15
Channel dope 4 after forming 0Å by heat treatment at 860 ℃
I do. The channel dope 4 is for adjusting the threshold voltage of the PMOS transistor, and N-type impurities such as phosphorus and arsenic are implanted.

Next, in step B, polysilicon 5 is deposited on the gate oxide film by the CVD method. In the product of the present invention, 2000 Å polysilicon is formed. P-type impurities are ion-implanted to make this polysilicon P-type. In the product of the present invention, the compound BF _{2 of} boron is used as an ion species instead of boron alone as a P-type impurity for implantation. The implantation concentration is ion implantation / polysilicon film thickness = 2E19 atom / cm ³ or more. That is, when the polysilicon film thickness is 2000Å, it is 4E14 atom / c.
m ² or more, more preferably 8E15 atom / cm ² is ion-implanted. Alternatively, when the polysilicon film thickness is 3000 Å, 6E14 atom / cm ² or more, more preferably 1.2E16 atom / cm ² is ion-implanted. The higher the concentration of ion implantation (more), the longer the implantation time. Therefore, the lower the ion implantation concentration is, the shorter the treatment time can be.
If it is too thin, the following problems occur. The MOS transistor operates by applying a constant voltage to the drain and applying a voltage equal to or higher than the threshold voltage to the gate electrode so that the channel is inverted and a current flows between the source and the drain. If the concentration is low, a depletion layer is formed in the polysilicon, and the applied voltage is taken by the depletion layer, so a voltage higher than necessary is required. As a result, the voltage will increase in absolute value. To explain more clearly, the threshold voltage is simply expressed as VTH = V _FB + 2Φ _F −Q _B / C _OX . Here, V _FB is the flat band voltage, Φ _F is the Fermi potential, Q _B is the substrate surface depletion layer charge, and C _OX is the gate oxide film capacitance. Since the depletion layer in the polysilicon has a capacitance and is connected in series with the capacitance of the gate oxide film, it is apparently the same as C _OX becoming smaller and VT
H becomes larger in the negative direction and rises in absolute value.

The channel conductance g _m is g _m =
(W / L) * μC _OX V _D (where W is the width of the gate electrode of the transistor, L is the length of the gate electrode of the transistor,
μ is a mobility and V _D is a drain voltage), and C _OX is small and channel conductance is small.

When the threshold voltage is lowered to about 0.5 V, the channel weakly inverts without applying a gate voltage, and a current flows between the source and the drain (leakage current). To make this easier to understand,
This will be described with reference to FIG. In the graph, the horizontal axis represents the gate voltage V _G and the vertical axis represents the drain current I _D in a logarithmic memory, and the data measured at the drain voltage V _D = 0.1 V is shown. All values are absolute. According to this, the gate voltage V _G = 0V and the drain current I _D ≠ 0A. That is, the current has flown without operating the MOS transistor. Here, the reciprocal of the slope of this characteristic V _G / lo
g (I _D ) is called a subthreshold coefficient S, and MOS
An important value that determines the switching performance of a transistor,
It is proportional to C _D / C _OX (C _D is the substrate surface depletion layer capacitance). Therefore, decreasing C _OX means increasing S and increasing leakage current. The ion implantation acceleration energy is set to about 40 KeV, for example.
Since BF ₂ has a larger molecular weight than B alone and has a small range at the time of ion implantation, it can be ion-implanted on the surface of polysilicon. On the contrary, since B has a large range, if it is carried out with the same acceleration energy as BF ₂ , boron will even enter the silicon substrate. To prevent entry, the acceleration energy must be lowered considerably. After that, in order to activate and diffuse the ion-implanted impurities, heat treatment is performed at a temperature of 700 to 900 ° C., for example, 850 ° C., so that the polysilicon becomes P-type. If the heat treatment is insufficient, boron is not evenly distributed in the polysilicon and a large amount of boron is present on the surface, and a depletion layer is easily formed. On the contrary, when the high temperature heat treatment is performed, boron diffuses over the gate oxide film to the silicon substrate and changes the threshold voltage (it becomes lower in absolute value).

Next, in step C, the tungsten silicide 6 is deposited on the polysilicon 5 to 2000 liters or less, for example 100
A 0Å film is deposited by the CVD method, the photoresist is patterned, and the polysilicon and the silicide film are etched at the same timing to form a polycide gate electrode.

Next, in step D, 85 is formed on the entire surface of the substrate.
CV of 5 to 1000Å at a temperature of 0 ° C or lower, for example, 400 ° C
The D insulating film 7 is formed. FIG. 4 shows the relationship between the CVD film thickness and the source / drain region forming ion implantation energy. Since the source / drain regions are formed after the CVD film forming step, the ion implantation is carried out through this CVD film. That is, FIG. 4 shows the maximum CVD film thickness with respect to the ion implantation energy for forming the source / drain regions. When the ion-implanted impurity is boron, it is preferable to set it in the region of the oblique line obliquely downward to the right and in the case of BF ₂ , it is set to the region of the oblique line obliquely downward to the left. In the product of the present invention, C of 400Å or 40Å
A VD insulating film was formed. Conventionally, since the film is formed by thermal oxidation, there is a problem that boron in polysilicon is diffused into tungsten silicide to lower the concentration and raise the threshold voltage. Also, when a large amount of boron is present on the surface of polysilicon, more boron diffuses into the tungsten silicide than is evenly distributed in the polysilicon, and the thicker the silicide film, the more boron. It is spreading. After the insulating film 7 is formed, P-type impurities are ion-implanted at a high concentration to form source / drain regions. In the product of the present invention, the CVD film thickness of 400 Å is subjected to boron with an energy of 30 KeV, and the 40 Å is subjected to BF ₂ of 80 Ke.
V.

Finally, in step E, a BPSG interlayer film 9 is formed on the entire surface. This interlayer film 9 is formed by, for example, the CVD method or the like, and is subsequently flattened by heat treatment. Since the conventional heat treatment has been performed at 920 ° C. for about 75 minutes to flatten, boron in the polysilicon diffuses into the tungsten silicide to lower the concentration and raise the threshold voltage, as described above. In the present invention, short-time heat treatment (RTA) is performed at a temperature of 800 to 1050 ° C., for example, at about 1025 ° C. for about 45 seconds, and the proportion of phosphorus in the BPSG interlayer film is changed from 5 wt% to 6 wt% to facilitate flattening. This suppressed the diffusion of boron into tungsten silicide. This heat treatment also activates and diffuses impurities in the source / drain regions ion-implanted. Subsequently, the interlayer film 9 is selectively etched to form contact holes communicating with the source / drain regions and the gate electrode. After that, contact reflow treatment is performed.
A heat treatment (RTA) at 850 ° C. for about 30 seconds was performed for a heat treatment for about 0 minutes to suppress the diffusion of boron into tungsten silicide. Subsequently, a metal material or the like is formed on the entire surface by vacuum vapor deposition or sputtering, and then photolithography and etching are performed to form a patterned metal wiring 10. Finally, the entire substrate 1 is covered with the surface protective film 11.

FIG. 5 is a diagram showing the capacitance characteristics of the gate electrode. In the graph of FIG. 5A, the horizontal axis represents the gate applied voltage, and the vertical axis represents the measured value obtained by dividing the total capacitance C of the gate electrode by the gate oxide film capacitance C _OX . FIG.
(B) is a cross-sectional view of the substrate and the state of connection when measured. FIG. 5C shows an equivalent circuit of FIG. 5B. Here, C _POLY is the gate electrode capacitance. FIG. 5 (a)
In the graph, the region where the gate applied voltage is negative is the capacitance of the gate electrode and the gate oxide film, and the positive region is the substrate depletion layer capacitance. The product of the present invention in the region where the gate applied voltage is negative has C / C _ox = 1 in almost all regions, whereas the conventional product has a value of 0.
It is 86. This is as follows. Since there is no depletion layer in the gate electrode of the present invention, there is no gate electrode capacitance C _{POLY and} C / C _OX = C _OX / C _OX = 1.
Since there is a depletion layer in the gate electrode of the conventional product and C / C _OX = C _POLY / (C _OX + C _POLY ) due to the gate electrode capacitance C _POLY , it is 1 or less. That is, C / C _ox <1 means that the concentration of the gate electrode is low. The threshold voltage of the PMOS transistor in both cases is
Compared to VTH _P | = 0.05V, the conventional product has risen to 0.71V.

FIG. 6 shows the change amount of the boron implantation concentration into polysilicon versus the threshold voltage when each step is performed. The horizontal axis shows the boron implantation concentration, and the vertical axis shows the amount of change in the threshold voltage. The present invention has an injection concentration of 2E1.
Although | VTH | has not changed at 9 atom / cm ³ or more, conventionally, even if 1E21 atom / cm ^{3 is} injected, | VT
H | has changed. It took a considerable time to inject a concentration of 1E21 atom / cm ³ .

A second embodiment of the semiconductor manufacturing method according to the present invention will be described in detail. A process of forming a P ⁺ polycide gate and a PMOS transistor having an LDD structure will be described with reference to FIGS. In step I, an N-type impurity such as phosphorus is ion-implanted into the surface of the P-type silicon substrate 1 at 1150 ° C.
Then, the implanted impurity phosphorus is diffused and activated to form the N well layer 2 as shown in FIG. A gate oxide film 3 such as 150 Å is formed thereon by heat treatment at 860 ° C., and then channel doping 4 is performed. The channel dope 4 is for adjusting the threshold voltage of the PMOS transistor, and N-type impurities such as phosphorus and arsenic are implanted. Next, the polysilicon 5 is deposited on the gate oxide film 3 by C
It is deposited by the VD method. In the product of the present invention, 2000 Å polysilicon is formed. P-type impurities are ion-implanted to make this polysilicon P-type. In the product of the present invention, the compound BF _{2 of} boron is used as an ion species instead of boron alone as a P-type impurity for implantation. Implantation concentration is ion implantation / polysilicon film thickness = 2E19 at
om / cm ³ or more. After that, in order to activate and diffuse the ion-implanted impurities, heat treatment is performed at a temperature of 700 to 900 ° C., for example, 850 ° C., so that the polysilicon becomes P-type. Next, tungsten silicide 6 is formed on the polysilicon 5.
A film having a thickness of 2000 Å or less, for example, 1000 Å is deposited by the CVD method, the photoresist is patterned, and the polysilicon and the silicide film are etched at the same timing to form a polycide gate electrode. Next, a CVD insulating film 7 of 5 to 1000 Å is formed on the entire surface of the substrate at a temperature of 850 ° C. or lower, for example, 400 ° C. In the product of the present invention, C of 400Å
A VD insulating film was formed. In the past, since the film was formed by thermal oxidation, there was a problem that boron in polysilicon was diffused into tungsten silicide to lower the concentration and raise the threshold voltage. Further, when a large amount of boron is present on the surface of polysilicon, more boron is diffused into the tungsten silicide than is evenly distributed in the polysilicon. Then LDD (LightlyDope)
dDrain) 12 regions are formed. Also in this case, since the ions are implanted into the semiconductor substrate through the CVD insulating film 7 similarly to the above, there is a maximum CVD film thickness with respect to the ion implantation energy (equivalent to FIG. 4). In the product of the present invention, the impurity BF ₂ is 3E13 atom / cm ² at an acceleration energy of 70 KeV.
Was ion-implanted. The CVD insulating film 7 here is LDD
It is used as a cushioning material for semiconductor substrate damage due to ion implantation.

In step II, CVD is performed on the entire surface of the substrate.
Side spacers 13 are formed by depositing and etching an insulating film, for example, 2500 Å. In step III, heat treatment is performed in an oxygen atmosphere at a temperature of 800 to 1050 ° C. for a short time, for example, at 960 ° C. for about 45 seconds to form the oxide film 14 and recover damage caused by etching in the previous step. Conventionally, since a film was formed by thermal oxidation at 950 ° C. for 45 minutes, there was a problem that boron in polysilicon was diffused into tungsten silicide to lower the concentration and raise the threshold voltage. Then, P-type impurities are ion-implanted at a high concentration through the oxide film 14 to form source / drain regions. In the product of the present invention, the impurity BF ₂ is 80 Ke.
5E15 atom / cm ² was ion-implanted at V.

Finally, in step IV, a BPSG interlayer film 9 is formed on the entire surface. This interlayer film 9 is formed by, for example, the CVD method or the like, and is subsequently flattened by heat treatment. Since the conventional heat treatment has been performed at 920 ° C. for about 75 minutes to flatten, boron in the polysilicon diffuses into the tungsten silicide to lower the concentration and raise the threshold voltage, as described above. In the present invention, short-time heat treatment (RTA) is performed at a temperature of 800 to 1050 ° C., for example, at 980 ° C. for about 45 seconds, and the proportion of phosphorus in the BPSG interlayer film is changed from 5 wt% to 6 wt% to facilitate flattening. This suppressed the diffusion of boron into tungsten silicide. This heat treatment also activates and diffuses impurities in the source / drain regions ion-implanted. Subsequently, the interlayer film 9 is selectively etched to form contact holes communicating with the source / drain regions and the gate electrode. After this, contact reflow processing is performed, which is also 880 ° C 30
Heat treatment for about 30 seconds at 850 ° C (R
TA) to suppress the diffusion of boron into tungsten silicide. Subsequently, a metal material or the like is formed on the entire surface by vacuum vapor deposition or sputtering, and then photolithography and etching are performed to form a patterned metal wiring 10. Finally, the entire substrate 1 is covered with the surface protection film 11
Cover with.

A third embodiment of the semiconductor manufacturing method according to the present invention will be described in detail. First, the steps up to the step of forming a gate oxide film of a CMOS transistor having a bipolar polycide gate structure will be described with reference to FIG. In step a, the N well layer 2 is formed on the surface of the P type silicon substrate 1. Oxide film 14 patterned into a predetermined shape as a mask on the substrate surface
After the formation of N, an N-type impurity such as phosphorus is added to 2E12ato.
Ion implantation is performed with a dose amount of m / cm ² . After this, 11
A heat treatment is performed at 50 ° C. for 6 hours to diffuse and activate the implanted impurity phosphorus to form the N well layer 2 as shown in the figure. A P channel MOS transistor is formed in the N well layer 2 and an N channel MOS transistor is formed in the adjacent portion.

Field doping is performed in step b.
For this purpose, first, the silicon nitride film 15 is patterned so as to cover the active region where the transistor element is formed. Particularly, a silicon nitride film 15 is formed on the N well 2.
A photoresist 16 is also formed by overlapping. In this state, the impurity boron is accelerated with an acceleration energy of 30 KeV and 2E13.
Ion implantation is performed at a dose amount of atom / cm ² to perform field doping. As shown, a field dope region is formed in the portion surrounding the device region.

Then, in step c, so-called LOCOS treatment is performed to form a field oxide film 17 so as to surround the element region. After that, sacrificial oxidation and its removal treatment are performed to remove foreign matters left on the surface of the substrate 1 for cleaning. Finally, in step d, the surface of the substrate 1 is thermally oxidized to form a gate oxide film 3 so as to cover the element region. This thermal oxidation treatment is performed at a temperature of 860 ° C. in an H ₂ O atmosphere and the temperature is about 150 Å
An oxide film is formed to some extent.

Next, the subsequent process will be described with reference to FIG. First, in step e, channel doping is performed to adjust the threshold voltage of the P-channel MOS transistor. P
N well layer 2 in which a channel MOS transistor is formed
A photoresist 16 is formed by patterning other than the above. Then, N type impurities such as phosphorus and arsenic are implanted.
The photoresist 16 serves as a mask in the adjacent region where the N-channel MOS transistor is to be formed, and is not doped with impurities. The implantation acceleration energy has a minimum and maximum for each impurity with respect to the oxide film thickness that intervenes during ion implantation.
The relationship is shown in FIG. In FIG. 12, the vertical axis represents the gate oxide film thickness, and the horizontal axis represents the channel doping energy. The possible acceleration energy region is the range from the right side of the MIN line of various impurities to the left side of the MAX line. For example, oxide film thickness is 1
In the case of 50Å, arsenic is changed from 16 KeV to 61 KeV and phosphorus is changed from 12 KeV to 26 KeV, and in the case of 120Å,
Arsenic is 13 KeV to 58 KeV, phosphorus is 10 KeV to 25 KeV, and at 100 Å, arsenic is 11 KeV.
From V to 56 KeV, phosphorus is from 8 KeV to 24 KeV. FIG. 13 shows the leak current per unit gate electrode width with respect to the threshold voltage of the P-channel MOS transistor. In FIG. 13, the vertical axis represents the leak current and the horizontal axis represents the threshold voltage. Here, for channel doping, N-type impurity phosphorus was ion-implanted at an acceleration energy of 25 KeV. Also P
Channel MOS transistor gate electrode length is 1.4μ
In m, the leak current was measured when the drain voltage (Vd) was −1.5V. Gate oxide film thickness (Gate) is 12
It can be seen that the leakage current of 100Å is about 4 times as large as that of 0Å. This is 2 for 100Å of gate oxide film
This is because the ions are implanted with the acceleration energy of 5 KeV. Next, FIG. 14 shows the subthreshold coefficient S with respect to the channel doping energy. The sub-threshold coefficient S is plotted on the vertical axis and the channel doping energy is plotted on the horizontal axis in FIG. It can be seen that the smaller the energy is, the smaller S is. Arsenic has an acceleration energy of 60 KeV and S of 71.8 mV /
Phosphorus is 7 at 40 KeV, while less than decade
It is 4.7 mV / decade. This means that arsenic can make S smaller than phosphorus even with the same energy. As described above, the smaller S is, the faster the transistor operates, and the more the leak current when the threshold voltage is low can be suppressed. FIG.
Shows the sub-threshold coefficient vs. leakage current per unit gate electrode width of the P-channel MOS transistor.
In FIG. 15, the ordinate represents the leak current and the abscissa represents the subthreshold coefficient S. When the gate oxide film thickness is 150 Å, the leak current has a drain voltage (Vd) of −. At 5V,
The threshold voltage was measured at -0.4V. It can be seen that when S exceeds 74 mV / decade, the leak current increases about twice or more.

Then, in step f, channel doping for adjusting the threshold voltage of the N-channel MOS transistor is performed. After removing the photoresist 16 formed in the previous step, the photoresist 16 is masked except for the region where the N-channel MOS transistor is formed, and a P-type impurity such as BF ₂ is implanted. As in the case of the P-channel MOS transistor, the acceleration energy has a minimum value and a maximum value for each impurity with respect to the oxide film thickness that intervenes during ion implantation (FIG. 12). For example, if the oxide film thickness is 150Å, 2
From 0 KeV to 60 KeV, in case of 120Å, 16 Ke
When V is 58 KeV and 100 Å, it is 14 KeV to 56 KeV. FIG. 16 shows the leak current per unit gate electrode width with respect to the threshold voltage of the N-channel MOS transistor. In FIG. 16, the vertical axis represents the leak current and the horizontal axis represents the threshold voltage. Here, the channel dope is P
Type impurity BF ₂ was ion-implanted at an acceleration energy of 25 KeV. In addition, the leak current was measured when the gate electrode length of the P-channel MOS transistor was 1.0, 1.4 and 10 μm and the drain voltage (Vd) was −1.5V.
Gate oxide film thickness (Gate) for each gate electrode length
The leakage currents of 100 and 120Å are almost the same.

Next, in step g, the photoresist 16 formed in the previous step is removed, and then polysilicon 5 is deposited on the gate oxide film by the CVD method. 2 in the product of the present invention
It forms 000Å polysilicon. N channel M
In order to form the gate electrode for the OS transistor, first, the region other than the region where the N-channel MOS transistor is formed is masked with the photoresist 16. Then, N-type impurities are ion-implanted in order to make this polysilicon N-type. In the product of the present invention, implantation is performed using phosphorus or arsenic as an ion species as an N-type impurity. Implantation concentration is ion implantation / polysilicon film thickness = 2E19 atom / cm
Set to ³ or more. That is, when the polysilicon film thickness is 2000 Å, 4E14 atom / cm ² or more, more preferably 5E15 atom / cm ² is ion-implanted. Or 6E14 atom when the polysilicon film thickness is 3000Å
/ Cm ² or more, more preferably 8E15 atom / cm ²
Is ion-implanted. The higher the concentration of ion implantation (more), the longer the implantation time. When the polysilicon film thickness is 2000 Å, the ion implantation acceleration energy is, for example, 40 K for phosphorus.
eV, arsenic to about 90 KeV, or 3000
When Å, for example, phosphorus is about 60 KeV and arsenic is 110
Set to about KeV.

Next, in step h, the photoresist 16 formed in the previous step is removed, and then the gate electrode for the P-channel MOS transistor is formed. Therefore, the region where the N-type impurity is ion-implanted is the photoresist 16 first. Keep a mask. Subsequently, P-type impurities are ion-implanted in order to make the polysilicon P-type. In the product of the present invention, as a P-type impurity, a boron compound BF is used instead of boron alone.
Implantation is performed using ₂ as the ion species. Implantation concentration is ion implantation / polysilicon film thickness = 2E19 atom / c
m ³ or more. The ion implantation acceleration energy is set to about 40 KeV, for example. Since BF ₂ has a larger molecular weight than B alone and has a small range at the time of ion implantation, it can be ion-implanted on the surface of polysilicon. On the contrary, since B has a large range, if it is carried out with the same acceleration energy as BF ₂ , boron will even enter the silicon substrate. To prevent entry, the acceleration energy must be lowered considerably. After that, in order to activate and diffuse the ion-implanted impurities, heat treatment is performed at a temperature of 700 to 900 ° C., for example, 850 ° C. to change the polysilicon into N / P type.

Next, the subsequent process will be described with reference to FIG. In step i, a tungsten silicide 6 of 2000 Å or less, for example, a film of 1000 Å C is formed on the polysilicon 5.
The photoresist is patterned by the VD method, the photoresist is patterned, and the polysilicon and the silicide film are etched at the same timing to form the P-type polycide gate electrode 18 and the N-type polycide gate electrode 19. The thicker the silicide film, the more boron in the polysilicon diffuses into the silicide.

Next, in step j, 85 is formed on the entire surface of the substrate.
CV of 5 to 1000Å at a temperature of 0 ° C or lower, for example, 400 ° C
The D insulating film 7 is formed. As described above, the CVD insulating film thickness depends on the ion implantation energy for forming the source / drain regions in the subsequent process. In the product of the present invention, a 400 Å or 40 Å CVD insulating film was formed. In the past, since the film was formed by thermal oxidation, there was a problem that boron in polysilicon was diffused into tungsten silicide to lower the concentration and raise the threshold voltage. Further, when a large amount of boron is present on the surface of polysilicon, more boron is diffused into the tungsten silicide than is evenly distributed in the polysilicon.

Next, in step k, the source / drain regions of the N-channel MOS transistor are formed. On this occasion,
The upper surface of the N well layer 2 where the P channel MOS transistor is formed is masked with a photoresist 16. In this state, N-type impurity phosphorus is ion-implanted by self alignment using the gate electrode 19 as a mask. The ion implantation conditions are as follows: For CVD film thickness of 400 Å, phosphorus is made to have an energy of 70 KeV and a dose of 5E15 atom / cm ^2.
3.5E15ato with 40 KeV energy for 0Å
The dose was m / cm ² . Since phosphorus is used as the N-type impurity unlike the prior art, it is possible to obtain a predetermined conductivity of the source / drain regions without subsequent heat treatment. Conventionally, arsenic having a small diffusion coefficient was used as an N-type impurity, so that high temperature thermal diffusion treatment at 950 ° C. for about 30 minutes was required, so that boron in polysilicon was diffused into tungsten silicide to lower the concentration. There was a problem of raising the threshold voltage.

Finally, the source / drain regions of the P-channel MOS transistor left in step 1 are formed. At this time, the portion of the N-channel MOS transistor previously formed is masked with the photoresist 16.
In this state, P-type impurities are ion-implanted at high concentration by self alignment using the gate electrode 18 as a mask. In the product of the present invention, boron is added to the CVD film thickness of 400 Å.
With energy of KeV to 5E15atom / cm ² or BF ₂ at an energy of 80KeV 6E15atom /
The dose is cm ² and BF ₂ is 5E15 atom / cm ² or 3.5E at an energy of 80 KeV for 40 Å.
The dose was 15 atom / cm ² .

Next, with reference to FIG. 11, a step of forming metal wiring will be described. Note that FIG. 11 shows a completed state of a CMOS transistor having a bipolar polycide gate structure. As shown, the source / source of the P-channel MOS transistor
After forming the drain region, the photoresist 16 is removed and the BPSG interlayer film 9 is formed on the entire surface. This interlayer film 9 is formed by, for example, the CVD method or the like, and is subsequently flattened by heat treatment. Since the conventional heat treatment has been performed at 920 ° C. for about 75 minutes to flatten, boron in the polysilicon diffuses into the tungsten silicide to lower the concentration and raise the threshold voltage, as described above. In the present invention, 800 to 10
Short time heat treatment (RTA) at a temperature of 50 ° C., for example 1000
The heat treatment was carried out at about ° C for about 45 seconds, and the proportion of phosphorus in the BPSG interlayer film was changed from 5 wt% to 6 wt% so as to facilitate flattening. This suppressed the diffusion of boron into tungsten silicide. Ion-implanted source by this heat treatment /
The impurities in the drain region are also activated and diffused.
Subsequently, the interlayer film 9 is selectively etched to form contact holes communicating with the source / drain regions and the gate electrode. After that, contact reflow treatment is performed, which was also performed by heat treatment (RTA) at 850 ° C. for about 30 seconds in comparison with the conventional heat treatment at 880 ° C. for about 30 minutes to suppress the diffusion of boron into tungsten silicide. Subsequently, a metal material or the like is formed on the entire surface by vacuum vapor deposition or sputtering, and then photolithography and etching are performed to form a patterned metal wiring 10. Finally, the entire substrate 1 is covered with the surface protective film 11.

A fourth embodiment of the semiconductor manufacturing method according to the present invention will be described in detail. A process of forming a channel dope layer of a CMOS transistor having a bipolar polycide gate structure will be described with reference to FIG. The steps up to the step α are the same as in FIG. In step α, the N-channel MOS transistor is channel-doped. P-type impurity BF2 is implanted into the entire surface of the semiconductor substrate.

Next, in step β, the N-channel MOS transistor formation region previously doped with BF ₂ is masked with the photoresist 16 and the channel doping of the P-channel MOS transistor, that is, N-type impurity phosphorus is implanted.
At this time, the previously formed P-type region is overridden to form an N-type channel layer. According to this,
When the channel doping of the N-channel MOS transistor is performed as in (f), it is not necessary to mask the P-channel MOS transistor formation region with the photoresist 16, which shortens the process. However, if arsenic with a small range is used instead of phosphorus, the P-type region previously formed cannot be completely overridden and the leak current increases. 18 P
The impurity profile of the channel dope layer of a channel MOS transistor is shown. In FIG. 18, the vertical axis represents the impurity concentration and the horizontal axis represents the distance. FIG. 18A shows a profile when phosphorus is used as an impurity for ion implantation. From this, the channel dope layer is completely N-type, whereas when arsenic is used as an impurity (see FIG. 18).
(B)) It can be seen that the P-type region remains. Conversely, first, N-type impurity phosphorus is ion-implanted over the entire surface of the semiconductor substrate, the P-channel MOS transistor region is masked with the photoresist 16, and the channel doping of the N-channel MOS transistor, that is, P-type impurity BF ₂ or boron is performed. It is possible even when ion implantation is performed.

A fifth embodiment of the semiconductor manufacturing method according to the present invention will be described in detail. A process of forming a gate electrode of a CMOS transistor having a bipolar polycide gate structure will be described with reference to FIG. The steps up to the step A are the same up to f in FIG. In step A, after removing the photoresist 16 formed in the previous step, polysilicon 5 is deposited on the gate oxide film by the CVD method. P-type impurity BF ₂ is ion-implanted on the entire surface of the polysilicon 5, and 700 to 900
A heat treatment is carried out at a temperature of 850 ° C., for example, to activate and diffuse the implanted impurities so that the polysilicon becomes P-type.

In step B, a tungsten silicide film having a thickness of 2000 Å or less, for example 1000 Å, is deposited on the polysilicon 5 by the CVD method, the photoresist is patterned, and the polysilicon and the silicide film are etched at the same timing to form a gate electrode. At this time, both the gate electrode on the N well layer 2 where the P channel MOS transistor is formed and the gate electrode on the region where the N channel MOS transistor is formed are P-type polycide gate electrodes 18. After that, a short time heat treatment is performed at a temperature of 800 to 1050 ° C. in an oxygen atmosphere, for example, 9
Heat treatment is performed at about 60 ° C. for about 45 seconds to form the oxide film 14.

Next, in step C, the source / drain regions of the N-channel MOS transistor are formed. On this occasion,
The upper surface of the N well layer 2 where the P channel MOS transistor is formed is masked with a photoresist 16. In this state, N-type impurity phosphorus is ion-implanted at a dose of 5E15 atom / cm ^{2 with} energy of 70 KeV, for example, by self alignment using the gate electrode 18 as a mask. At this time, phosphorus also enters the tungsten silicide.

In step D, the source / drain regions of the P channel MOS transistor are formed. At this time, the portion of the N-channel MOS transistor previously formed is masked with the photoresist 16. In this state, P-type impurity BF ₂ or boron is ion-implanted by self alignment using the gate electrode 18 as a mask. In the present invention, boron is used for 5E15a at an energy of 30 KeV.
Tom / cm ² or BF ₂ was performed at an energy of 80 KeV and a concentration of 5E15 atom / cm ² . Then, the photoresist 16 is removed and the BPSG interlayer film 9 is formed on the entire surface. This interlayer film 9 is formed by, for example, the CVD method or the like, and is subsequently flattened by heat treatment. 800 in the present invention
Short time heat treatment (RTA) at a temperature of 1050 ° C., for example 1
Heat treatment is performed at about 000 ° C. for about 45 seconds. At this time, when the source / drain regions of the N-channel MOS transistor are formed, phosphorus that has entered tungsten silicide of the gate electrode is diffused into the polysilicon below to form the P-type polycide gate electrode as N
Type polycide gate electrode. The heat treatment also activates and diffuses the impurities in the ion-implanted source / drain regions. Subsequently, the interlayer film 9 is selectively etched to form contact holes communicating with the source / drain regions and the gate electrode. After that, contact reflow treatment is performed, which was also performed by heat treatment (RTA) at 850 ° C. for about 30 seconds in comparison with the conventional heat treatment at 880 ° C. for about 30 minutes to suppress the diffusion of boron into tungsten silicide. Subsequently, a metal material or the like is formed on the entire surface by vacuum vapor deposition or sputtering, and then photolithography and etching are performed to form a patterned metal wiring 10. Finally, the entire substrate 1 is covered with the surface protection film 11 to manufacture the same structure as that shown in FIG.

By adopting this measure, the masking step for forming the polycide gate electrode can be omitted as compared with the manufacturing method described in the third embodiment, so that the manufacturing step is shortened.
A sixth embodiment of the semiconductor manufacturing method according to the present invention will be described in detail with reference to FIG. The surface of the p ⁻ type semiconductor substrate 1 is heat treated at 900 ° C. to form a thermal oxide film 14,
A silicon nitride film 15 is formed thereon. After selectively etching the silicon nitride film 15 using a photoresist patterned using a P-type well region mask,
The P-type impurity boron is added from 1E12 / cm ² to 5E12 /
Ion implantation is performed within a dose range of cm ² . More preferably, ion implantation is performed with a dose amount of 3E12 / cm ² . In the region where the silicon nitride film 15 is present, this serves as an implantation mask and boron is not implanted. Then, heat treatment at 950 ° C. is performed to further grow the thermal oxide film 14 in the region where the silicon nitride film 15 is not present. Since the silicon nitride film 15 exists in the other regions, the thermal oxide film 14 does not grow. The impurity boron implanted at this time is diffused and activated, and the P well layer 2
0 is formed. Then, only the remaining silicon nitride film 15 is removed, and N-type impurity phosphorus is ion-implanted at a dose of 2E12 / cm ² , for example. At this time, since the thick thermal oxide film 14 is formed on the P well layer 20 previously formed, this serves as a mask, and phosphorus does not enter the P well layer. After that, heat treatment is performed at 1150 ° C. for 6 hours to diffuse and activate the implanted impurity phosphorus to form the N well layer 2 as illustrated. At this time, the P well layer 20 previously formed is subjected to heat treatment and further diffused. In a later step, an N channel MOS transistor will be formed in the P well layer 20 and a P channel MOS transistor will be formed in the N well layer 2.

FIG. 21 is a graph showing the depth profile of the impurity phosphorus concentration of the N well layer formed on the p ⁻ type silicon substrate 1. The vertical axis of the graph shows the impurity concentration and the horizontal axis shows the depth. Here, the acceleration energy of ion implantation was 150 KeV. In the case of the invention product, the concentration profile curve rises near the substrate surface, and the surface concentration is small. On the other hand, in the case of the conventional product, the profile curve rises gently and the surface concentration is high. As a result, the invention product has a lower impurity concentration on the substrate surface. If the concentration is low, the subthreshold coefficient S described in FIG. 3 becomes small, so the characteristics of the invention product have a small slope as shown in the figure, and the drain current ID becomes small when the gate voltage VG = 0V, and the leakage current becomes small. Since the number is reduced, high speed driving becomes possible and low voltage driving can be achieved.

Although the embodiment in which the polysilicon thin film is used as the silicon thin film has been described above, a silicon single crystal silicon thin film or an amorphous silicon thin film can be used and is not limited to the polysilicon thin film. Furthermore, although a P-type silicon substrate is used as the substrate,
A type silicon substrate can also be used.

[0048]

As described above, according to the present invention, since the depletion layer does not exist in the gate electrode, the subthreshold coefficient S can be reduced. As a result, the switching performance of the MOS transistor can be improved. Further, it is possible to suppress an increase in leak current due to the lowering of the threshold voltage, and it is possible to achieve high-speed operation and low voltage.

[Brief description of drawings]

FIG. 1 is a process drawing showing a manufacturing method of a first embodiment of the present invention.

FIG. 2 is a final sectional view in a conventional manufacturing method.

FIG. 3 is a subthreshold characteristic of a MOS transistor.

FIG. 4 is a CVD maximum film thickness with respect to ion implantation energy for forming source / drain regions.

FIG. 5 is a capacitance characteristic of a gate electrode.

FIG. 6 is a change amount of a boron implantation concentration in polysilicon versus a threshold voltage.

FIG. 7 is a process drawing showing the manufacturing method of the second embodiment of the present invention.

FIG. 8 is a process drawing showing the manufacturing method of the third embodiment of the present invention.

FIG. 9 is a process drawing showing the manufacturing method of the third embodiment of the present invention.

FIG. 10 is a process drawing showing the manufacturing method of the third embodiment of the present invention.

FIG. 11 is a process diagram showing a completed product state of a third embodiment of the present invention.

FIG. 12 is a channel doping energy range with respect to a gate oxide film thickness.

FIG. 13 is a leak current with respect to a threshold voltage of a P-channel MOS transistor.

FIG. 14 is a subthreshold characteristic with respect to channel doping energy.

FIG. 15 is a leak current with respect to a subthreshold coefficient of a P-channel MOS transistor.

FIG. 16 is a leak current with respect to a threshold voltage of an N-channel MOS transistor.

FIG. 17 is a process drawing showing the manufacturing method of the fourth example of the present invention.

FIG. 18 is an impurity profile of a channel dope layer of a P channel MOS transistor.

FIG. 19 is a process drawing showing the manufacturing method of the fifth embodiment of the present invention.

FIG. 20 is a process drawing showing the manufacturing method of the sixth embodiment of the present invention.

FIG. 21: Impurity profile of N well layer

[Explanation of symbols]

1 p ^- type Si substrate 2 N well layer 3 Gate oxide film 4 Channel dope layer 5 Polysilicon 6 Tungsten silicide 7 Oxide film 8 Source / drain 9 BPSG interlayer film 10 Metal wiring 11 Surface protection film 12 LDD 13 Side spacer 14 Oxide film 15 silicon nitride film 16 photoresist 17 field oxide film 18 P type polycide gate electrode 19 N type polycide gate electrode 20 P well layer

Claims (15)

[Claims] 1. A step of forming a gate insulating film on a surface of a semiconductor substrate, a step of patterning a gate electrode on the gate insulating film, and a step of forming a gate electrode on the entire surface of the semiconductor substrate with a film thickness of 5 to 1000 Å. A method of manufacturing a semiconductor device, comprising: forming a CVD insulating film; and forming source / drain regions by ion-implanting impurities into the surface of the semiconductor substrate using the gate electrode as a mask. 2. The step of patterning and forming the gate electrode includes a step of forming a silicon thin film on the gate insulating film, a step of ion-implanting a P-type impurity into the silicon thin film, and the semiconductor substrate. 700-900 ℃
The silicon thin film is heated at a temperature of
The method of manufacturing a semiconductor device according to claim 1, comprising a step of forming a mold and a step of forming a silicide film on the silicon thin film. 3. The source / drain regions are 800 to 1
2. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is formed by activation by a short-time heat treatment within 3 minutes at a temperature of 050 [deg.] C. 4. A method of manufacturing a semiconductor device, wherein a P-type insulated gate field effect transistor and an N-type insulated gate field effect transistor are integrated in an N-type semiconductor region and a P-type semiconductor region provided on a surface of a semiconductor substrate, respectively. Forming a gate insulating film on the surface of the semiconductor substrate; forming a silicon thin film on the gate insulating film; and ion-implanting P-type impurities into the silicon thin film on the N-type semiconductor region. A step of ion-implanting an N-type impurity into the silicon thin film on the P-type semiconductor region, and a step of heat-treating the semiconductor substrate at a temperature of 700 to 900 ° C. to make the silicon thin film P-type and N-type. And a step of forming a silicide film on the silicon thin film,
A step of selectively etching the silicon thin film and the silicide film to form a gate electrode on the gate insulating film; a step of forming a CVD insulating film having a film thickness of 5 to 1000Å on the entire surface of the semiconductor substrate; Forming a source / drain region by ion-implanting P-type impurities into the surface of the N-type semiconductor region using the gate electrode as a mask; and ion-implanting N-type impurity phosphorus in the surface of the P-type semiconductor region using the gate electrode as a mask. And a step of forming source / drain regions by implanting. 5. The step of forming the source / drain regions includes forming the source / drain regions at 800 to 1050 ° C.
5. The method for manufacturing a semiconductor device according to claim 4, wherein the semiconductor device is formed by being activated by a short-time heat treatment within 3 minutes at the temperature. 6. A gate insulating film provided on a semiconductor substrate, a gate electrode provided on the gate insulating film, comprising a plurality of layers of P-type and N-type polysilicon thin films and conductor thin films, and the gate electrode. Of the source / drain regions provided on the surface of the semiconductor region on both sides of the semiconductor substrate so as to be separated from each other, and the P-type and N-type polysilicon thin films apply a voltage between the conductor thin film and the semiconductor substrate. A semiconductor device having a sufficient amount of impurity concentration that a depletion layer is not formed in the P-type and N-type polysilicon thin films when applied. 7. The P-type polysilicon thin film having a P-type impurity concentration of 2E19 atom / cm ³ or more and the N-type polysilicon thin film having an N-type impurity concentration of 2E19 atom / cm ³ or more.
7. The semiconductor device according to claim 6, which contains m ³ or more. 8. A method of manufacturing a CMOS semiconductor device, wherein a P-type insulated gate field effect transistor and an N-type insulated gate field effect transistor are integrated in an N-type semiconductor region and a P-type semiconductor region provided on a surface of a semiconductor substrate, respectively. Forming a gate insulating film on the surface of the semiconductor substrate, and forming a channel dope region by ion-implanting N-type impurities into the surface of the N-type semiconductor region,
Forming a channel dope region by implanting P-type impurities into the surface of the P-type semiconductor region; forming a silicon thin film on the gate insulating film; and forming a silicon thin film on the N-type semiconductor region. The step of ion-implanting P-type impurities, the step of ion-implanting N-type impurities into the silicon thin film on the P-type semiconductor region, and the heat treatment of the semiconductor substrate at a temperature of 700 to 900 ° C. Converting the thin film into P-type and N-type, forming a silicide film on the silicon thin film,
A step of selectively etching the silicon thin film and the silicide film to form a gate electrode on the gate insulating film; a step of forming a CVD insulating film having a film thickness of 5 to 1000Å on the entire surface of the semiconductor substrate; Forming a source / drain region by ion-implanting P-type impurities into the surface of the N-type semiconductor region using the gate electrode as a mask; and ion-implanting N-type impurity phosphorus in the surface of the P-type semiconductor region using the gate electrode as a mask. A method of manufacturing a semiconductor device, comprising: a step of forming source / drain regions by implantation; and a step of activating and forming the source / drain regions by heat treatment at a temperature of 800 to 1050 ° C. for a short time within 3 minutes. 9. A channel dope seed and an ion implantation acceleration energy in the step of forming the channel dope region are 30 KeV or less for phosphorus as an N-type impurity or 7 for arsenic.
9. The method of manufacturing a semiconductor device according to claim 8, wherein 0 KeV or less and P-type impurities of BF ₂ are 70 KeV or less. 10. A channel dope region is formed by ion-implanting a P-type impurity BF ₂ on the entire surface of a semiconductor substrate in the step of forming the channel-doped region, and then ion-implanting an N-type impurity phosphorus on the surface of the N-type semiconductor region. 9. The method for manufacturing a semiconductor device according to claim 8, wherein the method is formed. 11. A channel dope region is formed by ion-implanting N-type impurity phosphorus over the entire surface of a semiconductor substrate in the step of forming the channel dope region, and then ion-implanting P-type impurity at the surface of the P-type semiconductor region. 9. The method of manufacturing a semiconductor device according to claim 8, wherein. 12. A method of manufacturing a semiconductor device, wherein a P-type insulated gate field effect transistor and an N-type insulated gate field effect transistor are integrated in an N-type semiconductor region and a P-type semiconductor region provided on a surface of a semiconductor substrate, respectively. Forming a gate insulating film on the surface of the semiconductor substrate; implanting P-type and N-type impurities into the surfaces of the N-type and P-type semiconductor regions, respectively; and forming a silicon thin film on the gate insulating film. A step of forming, a step of ion-implanting a P-type impurity into the silicon thin film, a step of converting the silicon thin film into a P-type by heat-treating the semiconductor substrate at a temperature of 700 to 900 ° C., and the silicon thin film. Forming a silicide film on the gate insulating film, and selectively etching the silicon thin film and the silicide film simultaneously to form a gate insulating film. Forming a gate electrode on top,
An oxygen atmosphere of 800 to 105 is formed on the entire surface of the semiconductor substrate.
Source / drain regions are formed by forming an insulating film by heat treatment at a temperature of 0 ° C. for a short time within 3 minutes, and by ion-implanting N-type impurities into the surface of the P-type semiconductor region using the gate electrode as a mask. At the same time, ion-implanting into the silicide film, forming source / drain regions by ion-implanting P-type impurities into the surface of the N-type semiconductor region using the gate electrode as a mask, and the source / drain regions. 800 ~ 1050 ℃
At the same time, the P-type silicon thin film on the surface of the P-type semiconductor region is activated and formed by short-time heat treatment for 3 minutes or less at the same time from the ion-implanted silicide film to the silicon thin film below the silicide film to form an N-type impurity. And a step of diffusing into a N-type silicon thin film to produce a semiconductor device. 13. The N provided on the surface of a semiconductor substrate
In a semiconductor device in which the P-type insulated gate field effect transistor and the N-type insulated gate field effect transistor are integrated in a P-type semiconductor region and a P-type semiconductor region, respectively, a gate insulating film of 30 to 200 Å is formed on a surface of a semiconductor substrate. 13. The method of manufacturing a semiconductor device according to claim 8, wherein the minimum length of the gate electrode formed on the gate insulating film is 1.0 μm. 14. A semiconductor manufacturing method for forming a P-type well layer and an N-type well layer on a semiconductor substrate using one mask, wherein the N-type well layer is formed after the P-type well layer is formed. A characteristic semiconductor manufacturing method. 15. A step of sequentially forming a silicon oxide film and a silicon nitride film on a semiconductor substrate, and a step of selectively removing the silicon nitride film by a photomask process to define a region of the P well layer. Ion-implanting P-type impurities into the semiconductor substrate, forming a silicon oxide film in the P well region where the silicon nitride film is removed, and removing the silicon nitride film to define an N well layer region. 15. The method of manufacturing a semiconductor according to claim 14, further comprising: a step of implanting N-type impurities into the semiconductor substrate, a step of heat treating the semiconductor substrate to diffuse and activate the impurities.