JPH09204352A - Storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce time for reading consecutive addresses by providing a means comparing an address inputted from an external controller and an output from a preceding address latch means and controlling the latch timing of the preceding address latch means based on a comparing result and a means selecting reading data from plural memory array areas. SOLUTION: An address comparing means 101 compares addresses A19 to A1 inputted from the external controller and an address provided for a memory array 105 on a bus 111 to output the result to a signal 112. A preceding address latch control means 102 outputs an address latch control signal 113 from an address comparing result signal 112 and a CS signal. Then a 2to1 selector 107 converts data outputted from the memory arrays 105 and 106 by an address A0 inputted from the external controller.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a storage device.

[0002]

2. Description of the Related Art Since a ROM does not lose data even when the power is turned off, an information processing apparatus stores an initial program at the time of turning on the power, a program loader, character font data, and the like. Further, in a small-sized information processing device having no hard disk drive, the application program may be stored in the ROM.

Further, since the access speed of the ROM is slower than that of the random access memory (RAM), there is a problem that the processing speed becomes low when the program stored in the ROM is run. On the other hand, a ROM with a page mode access function has been proposed because of the characteristic that the program is read from consecutive addresses. As a known example, NEC Technical Report Vol. 47 No. 3/1994 9
There are pages 3-94.

[0004]

FIG. 3 shows a schematic configuration of a ROM with a page mode access function. In this conventional example,
The read data width is 16 bits (D15-0) and the storage capacity is 16 megabits. As the address, 20 bits (A19 to 0) are input in word units from the storage capacity. Further, a CS signal is provided as a selection signal of this ROM, and an OE signal is provided as an output permission signal of read data.

In the conventional configuration, four data are simultaneously output from the memory array in the ROM, and the four output data are switched by the 4to1 selector according to the lower address (A1, A0), so that the upper address (A19 to A2). One of the data selected in step 1 was selected and output.

In the conventional configuration, high-speed reading is possible when the same page is accessed without changing the upper address, but the access time is long when the page is modified. was there. Therefore, since there is a high probability that the program will be read from consecutive addresses, in the case of a page configuration of 16 bits × 4 words as shown in FIG. 3, the access time becomes long at a rate of almost every four word accesses. was there.

An object of the present invention is to provide a high-speed ROM which has a short access time when reading consecutive addresses.

[0008]

A plurality of (n) memory array areas are divided, and an address adding means for generating an address which is likely to be accessed next with respect to an address input from an external control device. Comparing the preceding address latching means for holding the address output from the address adding means, the address comparing means for comparing the address input from the external control device with the output from the preceding address latching means, and the address comparing means. It can be constituted by a leading address latch control means for controlling the latch timing of the leading address latch means based on the result and a read data selecting means for selecting one read data from the plurality of memory array areas.

Similar to the conventional example, the output data from the n memory array areas is read out by using the lower address and selected by the data selecting means and output. In the conventional example, since the upper address is fixed, the access speed becomes slower when the upper address is switched. However, in the present invention, the address near the address being accessed that is likely to be accessed next (the address being accessed is +1 to (n-
(1)) is generated by the address adding means and the preceding address is supplied to the memory array area before the access request is received to start the access, so that the access can be performed at high speed regardless of the page as in the conventional configuration. it can.

The preceding address latch control means latches the preceding address output from the address adding means, and the preceding address latch control means latches the address latch means based on the comparison result output from the address comparing means. Control timing.

Further, since the address input from the external control device may not be close to the address being accessed, the preceding address generated by the address addition device and the address input from the external control device are compared by the address comparison device. If the addresses match, the address data held in the address latch means is held, and if the addresses do not match, the address input from the external control device is held again in the address latch means and a new address is supplied to the memory array area. To do so. This guarantees normal access when the address input from the external control device does not come close to the address being accessed.

Due to the above-described operation, the slow access which always occurs in each page switching in the conventional configuration,
According to the present invention, if the address of the next access to the address being accessed is from +1 to (n-1), the slow access does not occur.

Therefore, according to the present invention, it is possible to realize a high-speed ROM having a short access time when reading consecutive addresses.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows an example of the configuration of the storage device of the present invention. In this embodiment, the read data width and storage capacity are 16 bits (D15 to 0), respectively, as in the conventional example.
16 megabits and 20 bits for the address (A19-
0) is input. Further, the number of memory arrays is n = 2 for simplification of description.

The address adder 103 has an A0 bit of an address input from an external control device (not shown) set to 0.
When the A0 bit is 1, the addresses A19 to A1 are directly output to the bus 110 without performing the address addition.

The preceding address latch means 104 is based on an address latch control signal 113 which will be described later, and the bus 110.
Address data is latched and output to the bus 111. The address data on the bus 111 is supplied to the memory array 105.

The address comparison means 101 compares A19 to 1 of the address input from the external control device with the address supplied to the memory array 105 on the bus 111, and outputs the result as a signal 112.

The preceding address latch control means 102 outputs an address latch control signal 113 from the address comparison result signal 112 and the CS signal. This signal 113 controls the preceding address latch means 104 as described above. The operation of the control means 102 is expressed by the following equation.

Address latch signal 113 = CS signal +
(! CS signal / address comparison result signal 112) The symbol “!” Is a logical negation, the symbol “+” is a logical sum,
The symbol “•” indicates a logical product.

Since the number (n) of memory arrays is 2, the memory array 105 stores data at address A0 = 0. In the memory array 106, data of address A0 = 1 is stored as in the above.

The 2to1 selector 107 is used for the memory array 1
The data output from 05 and the data output from the memory array 106 are selected by the address A0 input from the external control device.

The 3-state output buffer 108 has 2to1
The data output from the selector 107 is output as data (D15-0) when the data output control signal 114 is valid.

The data output control signal 114 is a logical product of the CS signal and the OE signal by the logical product circuit 109.

FIG. 2 is a timing chart showing the operation of this configuration example. Next, the operation of this configuration example will be described.

The read operation of this ROM is carried out at the address (A
19-0), the selection signal (CS signal) of this ROM, and the output enable signal (OE signal),
It is executed by outputting the data (D15-0).

First, addresses A19 to 1 = X, A0 = 0
Since A0 = 0 by the input of, the address addition means 103 does not perform address addition and
Is output to the bus 110 as it is. Here, the preceding address 111 and the address X which have already been latched are compared by the address comparison means 101. At this time, the preceding address 1
It is assumed that 11 is Y (Y ≦ X, X + n−1 <Y), and the address comparison result 112 is “mismatch” = 0.
As described above, the address latch control means 102 outputs the address latch control signal 113 (latch permission = 1) according to the address comparison result 112 and the CS signal. In response to the address latch control signal 113, the preceding address latch means 104 latches the address data X on the bus 110 and outputs it to the preceding address bus 111.

The memory array 105 outputs stored data at the address X input from the bus 111. The data is selected by the 2to1 selector 107 by the address A0 signal and output through the 3-state output buffer 108. The 3-state output buffer 108 has a CS signal and an O signal.
The output is enabled by the signal 114 which is the logical product of the E signals.

The above is the operation of the first access to the ROM.

Next, the address (A
It is assumed that the address (A19 to 1 = X, A0 = 1) is input as the second access to 19 to 1 = X, A0 = 0.

Since the address (A19-1 = X) has already been supplied to the memory array 106 from the time of the first access, it is only necessary to select the stored data by the 2to1 selector 107 immediately after the address A0 is switched to 1. , Data (D15-0) can be output.

Therefore, it is understood that the access can be performed at high speed when the memory array 105 access is switched to the memory array 106 access, that is, when the even address is incremented by 1 to the consecutive address access.

Next, the address (A
It is assumed that an address (A19-1 = X + 1, A0 = 0) is input as the third access to 19-1 = X, A0 = 1).

At the time when the address A0 of the second access becomes 1, the address adding means 103 determines that the address (A
19 to 0 = X) is added with 1 and is output to the bus 110. The preceding address latch means 104, the address comparing means 101, and the preceding address latch control means 102 have the same address (A19 to 1 = X +) as the first access.
1) is supplied to the memory array 105. When the third access is started, the address output from the preceding address latch means 104 is compared with the address of the third access, and in this case, the addresses match, so the address comparison means 10
1 outputs “match” = 1. The preceding address latch control means 102 keeps the latch control signal at 0, and the preceding address latch means 104 does not latch the address data.

In this way, the address (A19-1 =
Since (X + 1) can be already supplied to the memory array 105 from the second access, the data (D15 to 0) can be output only by selecting the storage data by the 2to1 selector 107 immediately when the address A0 is switched to 0. .

Therefore, it can be understood that high speed access can be achieved even when the memory array 106 access is switched to the memory array 105 access, that is, even when the consecutive address is incremented by 1 from the odd address to the even address.

From the above, it can be seen that the stored data can be read at high speed when the addresses for accessing the ROM are continuous.

Next, the case where access to the ROM is not continuous will be described in the fourth access. 4th
The address of the second access is A19-1 = X + 1 +
2, A0 = 0, and the address (A
19-1 = X + 1, A0 = 0), there is no continuity. In this case, since the address A0 = 0, the memory array 105
Since the preceding address 111 and the address A19-1 of the fourth access do not match, the fourth address address A19-1 is latched again and accessed. As a result, it can be seen that when the addresses for accessing the ROM are not consecutive, the reading of the stored data is slow, but the correct data can be read.

Reading of programs and data is very likely to occur at consecutive addresses. According to the above embodiment, it is possible to realize a ROM having a short access time at the time of reading consecutive addresses, and to address addresses such as pages. There is no decrease in access speed due to breaks.

In this embodiment, the number of memory arrays is n = 2.
However, it is possible to easily increase n by the same method as in this embodiment. If n is increased, the number of addresses that start access in advance increases, and the frequency of low-speed access can be reduced.

When the ROM of the present invention is used, high-speed access and low-speed access occur as in the conventional ROM with a page access function, so that the external control device must control the access timing. Since the present invention has the address comparison means 101, the timing control of the external control device can be simplified by generating the access timing control information from the comparison result and outputting it to the external control device.

[0041]

According to the present invention, it is possible to provide a high-speed ROM which has a short access time when reading consecutive addresses.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment showing a configuration of a storage device of the present invention.

FIG. 2 is a timing chart showing the operation of FIG.

FIG. 3 is a block diagram of a conventional storage device.

[Explanation of symbols]

101 ... Address comparison means, 102 ... Leading address latch control means, 103 ... Address adding means, 104 ... Leading address latch means, 105, 106 ... Memory array,
107 ... 2to1 selector, 108 ... 3-state output buffer, 109 ... AND circuit, 110, 111 ... Bus, 1
12 ... Address comparison result signal, 113 ... Leading address latch control signal, 114 ... Data output control signal.

Claims (1)

[Claims] 1. A storage device capable of reading from an arbitrary address, which generates a memory array area divided into a plurality of addresses and an address which is likely to be accessed next with respect to an address input from an external control device. Address adding means, preceding address latching means for holding the address output from the address adding means, address comparing means for comparing the address input from the external control device with the output from the preceding address latching means, Leading address latch control means for controlling the latch timing of the leading address latch means based on the comparison result of the address comparing means, and read data selecting means for selecting one read data from the plurality of memory array areas. A storage device having.