JPH11355536A - Image processing method and image processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the method and device for processing image by which processing rate can be accelerated in the case of storing image data in an image storage memory by subjecting them to logical operations. SOLUTION: This image processor for storing data inputted from the outside is provided with an image storage memory 40 for storing the data, a memory control means 110 for controlling the access method of the image storage memory 40, a write data discriminating means 100 for discriminating whether or not the respective bits of a data stream capable of simultaneously writing in the image storage memory 40 are completely equal to each other, a read data discriminating means 90 for discriminating whether or not all the respective bits of the data stream capable of simultaneously reading out of the image storage memory 40 are equal to each other and a logic setting means 30 for setting the logic of data written in the image storage memory 40. Based on the information from the write data discriminating means 100, the read data discriminating means 90 and the logic setting means 30, the memory control means 110 changes the method of access to the image storage memory 40.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing method and an image processing apparatus, and more particularly to an improvement in memory control when storing bit map image data for image formation in an image storage memory.

[0002]

2. Description of the Related Art In a conventional apparatus, logical writing (AND, OR, NOT, etc.) is performed in a memory (image storage memory) in which image data is written, as shown in FIG.

That is, when the logical writing process is started, first, data (hereinafter, referred to as destination data) stored at an address to which all data is to be written is read from the memory (FIG. 9S).
1).

Then, the data to be written (hereinafter referred to as source data) is turned off (FIG. 9S2), and the address to be written (hereinafter referred to as destination) is overwritten (FIG. 9S3).

[0005]

In the above-described processing procedure, it is necessary to perform readout, logic application, and overwriting, which has had a great adverse effect on the image processing speed.

[0006] In recent years, the processing speed of the CPU has been remarkably improved due to the expansion of internal memories and the introduction of peripheral devices. However, the processing speed of a memory such as a DRAM as a storage unit for storing the processing result has not been improved so much, and may be a bottleneck in the overall processing speed.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to realize an image processing method and an image processing apparatus capable of improving the processing speed when storing image data in an image storage memory by performing a logic cling. .

[0008]

The present invention for solving the above problems is as described below. (1) The invention according to claim 1 is an image processing method for storing data input from the outside in an image storage memory, wherein it is determined whether all bits of a data string that can be written to the image storage memory at one time are all the same. Then, it is determined whether or not all the bits of the data string that can be read at once from the image storage memory are the same, and by referring to the two determination results and the logic set for the data to be written to the image storage memory, And changing an access method to an image storage memory.

According to a sixth aspect of the present invention, there is provided an image processing apparatus for storing data inputted from the outside, wherein the image processing apparatus has an image storage memory for storing data and a method for controlling an access method of the image storage memory. Memory control means, write data determination means for determining whether all bits of a data string that can be written to the image storage memory at a time are the same, and all bits of a data string that can be read at a time from the image storage memory are all the same Read data determination means for determining whether or not the data is to be written to the image storage memory; and logic setting means for setting the logic of the data to be written to the image storage memory. Means for accessing the image storage memory according to the information from the means. Change, it is an image processing apparatus according to claim.

According to the present invention, it is determined whether all the bits of a data string that can be written to the image storage memory at one time are the same, and it is determined whether all the bits of the data string that can be read at a time from the image storage memory are all the same. By referring to these two determination results and the logic set for the data to be written to the image storage memory, the access method to the image storage memory is changed to be suitable.

As a result, when the image data is stored in the image storage memory by performing the logic cling, an appropriate access can be performed according to the data and the logic, so that the processing speed can be improved.

(2) According to the second aspect of the present invention, it is determined whether all the bits of a data string which can be written to the image storage memory at one time are all the same, and the determination result and the data to be written to the image storage memory are determined. 2. The image processing method according to claim 1, wherein the access method is changed by referring to the set logic so as not to read from the image storage memory.

According to a seventh aspect of the present invention, the memory control means changes an access method based on information from the write data determination means and the logic setting means so as not to read from the image storage memory. ,
7. An image processing apparatus according to claim 6, wherein:

According to the present invention, it is determined whether all the bits of a data string which can be written to the image storage memory at one time are the same, and the determination result and the logic set for the data to be written to the image storage memory are referred to. If the result does not change with the contents of the image storage memory,
The access method is changed so that reading from the image storage memory is not performed.

As a result, when the image data is stored in the image storage memory by performing the logic declination, the access can be performed in a state where the useless reading process is omitted, so that the processing speed can be improved. .

(3) According to the third aspect of the present invention, it is determined whether all the bits of the data string that can be written to the image storage memory at one time are all the same, and all the bits of the data string that can be read at once from the image storage memory are all It is determined whether or not they are the same, and by referring to the two determination results and the logic set for the data to be written to the image storage memory, the memory control means controls the writing to the image storage memory so as not to perform the writing. 2. The image processing method according to claim 1, wherein an access method is changed.

The invention according to claim 8, wherein the memory control means does not perform writing to the image storage memory based on information from the write data determination means, the read data determination means, and the logic setting means. 7. The image processing apparatus according to claim 6, wherein the access method is changed by:

According to the present invention, it is determined whether all the bits of a data string that can be written to the image storage memory at one time are all the same, and it is determined whether all the bits of the data string that can be read at a time from the image storage memory are all the same. Then, referring to these two determination results and the logic set for the data to be written to the image storage memory, if the contents of the image storage memory do not change even if the writing is performed, The access method is changed so that writing is not performed.

As a result, when the image data is stored in the image storage memory by performing the logic declination, the access can be performed in a state where the useless writing process is omitted, so that the processing speed can be improved. .

(4) The invention according to claim 4 determines whether all the bits of the data string that can be written to the image storage memory at one time are all the same, and determines that all the bits of the data string that can be read at once from the image storage memory are all Determining whether they are the same, and referring to the two determination results and the logic set for the data to be written to the image storage memory, referring to the logic of the data read from the image storage memory and the logic of the data to be written to the image storage memory. 2. The image processing method according to claim 1, wherein an access method is changed so as not to cling.

According to a ninth aspect of the present invention, the data read from the image storage memory and the data to be written to the image storage memory based on information from the write data determination unit, the read data determination unit, and the logic setting unit. 7. The image processing apparatus according to claim 6, wherein an access method is changed by said memory control means so as not to perform the above logic.

According to the present invention, it is determined whether or not all the bits of a data string which can be written to the image storage memory at one time are all the same, and whether or not all the bits of the data string which can be read at a time from the image storage memory are all the same. Then, referring to these two determination results and the logic set for the data to be written to the image storage memory, if the result can be predicted without performing the logic cling, access is performed so as not to perform the logic cling. The method has changed.

As a result, when storing the image data in the image storage memory by performing the logic cling, the access can be performed in a state where the logic cling is omitted, so that the processing speed can be improved.

(5) According to a fifth aspect of the present invention, the two determinations are performed by processing means configured by hardware.
The image processing method according to claim 1, wherein:
The invention according to claim 10 is the image processing apparatus according to claim 6, wherein the determination by the write data determination unit and the read data determination unit is performed by hardware.

According to the present invention, by performing data determination by hardware, processing can be performed at a higher speed than in the case of executing by software, and the processing speed when accessing the image storage memory can be improved. Will be possible.

[Outline of Processing] The processing in each of the above inventions will be described with reference to FIG. In the process of the invention shown in FIG. 1, when logical writing starts (S1 in FIG. 1), it is determined from the logic of the source data and the source data whether or not Condition 1 or Condition 2 is satisfied (S1 in FIG. 1).

Here, the condition 1 is: The logic of the source data is AND, the source data is all 1, the logic of the source data is OR, the source data is all 0, and the condition 2 is: The logic is AND, the source data is all 0, the logic of the source data is OR, and the source data is all 1.

If the condition 1 is satisfied in the determination S1,
Since the destination data does not change even if the logic is shifted, the logical writing is terminated without reading the destination data from the memory.

When the condition 2 is satisfied in the determination S1, the state becomes the same as the source data when the logic is applied. Therefore, the destination data is overwritten on the destination without reading the destination data from the memory (S6 in FIG. 1). , End the logical writing.

In the judgment S1, even if the condition 1 is satisfied, the condition 2 is satisfied.
Only when this is not the case, the destination data is read from the memory (S2 in FIG. 1). Next, it is determined from the logic of the source data, the source data, and the destination data whether or not Condition 3 or Condition 4 is satisfied. That is, the determination is performed by adding the destination data.

The condition 3 is as follows: The logic of the source data is AND, the source data is mixed with 0 and 1, the destination data is all 0, the logic of the source data is OR, and the source data is 0. And 1
Are mixed, destination data are all 1, and condition 4 is: ・ Logic of source data is AND, source data is mixed with 0 and 1, destination data is all 1, ・ Logic of source data is OR , Source data is 0 and 1
Are mixed, and the destination data are all 0,.

If the condition 3 is satisfied in the determination S4,
Since the destination data does not change even if the logical writing is performed, the logical writing of the destination data and the source data is not performed, and the logical writing ends.

When the condition 4 is satisfied in the judgment S4, the logic is shifted to the same state as the source data. Therefore, the logic of the destination data and the source data is not changed, and the source data is overwritten on the destination ( 1S6), the logical writing ends.

In the above determination S4, the condition 4 is satisfied even if the condition 3 is satisfied.
Otherwise, since the result is determined by the logical shift, the destination data and the source data are logically shifted (S4 in FIG. 1), the logically shifted data is overwritten on the destination data (S5 in FIG. 1), and the logical writing is completed. I do.

In the present invention, as shown in FIG. 1 and the above description, the logic of the source data, the contents of the source data and the destination data are determined, and the logical writing is performed without reading the destination data from the memory. Whether to end (condition 1), overwrite the source data to the destination without reading the destination data from the memory (condition 2), or to read the destination data from the memory and end the logical writing ( Condition 3) Or, read the destination data from the memory and overwrite the source data with the destination (Condition 4), or read the destination data from the memory and overwrite the destination with the source data, and then overwrite the destination Or (Condition 5) By controlling the memory in the most appropriate access method is omitted unnecessary operation, to improve the image processing speed.

That is, as shown in FIG. 1, by determining the logic of the source data, the source data, and the destination data, the logical writing process determined as the condition 1 can be performed by reading the destination data and storing the destination data in the source data. Logic with data can be omitted, and writing to the destination can be omitted. In the logical writing process determined to be the condition 2, the logic between the destination data and the source data can be omitted. In the logical writing process determined to be the condition 3, the logic between the destination data and the source data is applied, and writing to the destination can be omitted. In the logical writing process determined to be the condition 4, the logic between the destination data and the source data can be omitted.

As a result, the image processing speed of the apparatus can be improved as compared with the conventional technique in which the destination data is read out for all data, the source data is logically turned on, and then the data is written to the destination.

[0038]

DESCRIPTION OF THE PREFERRED EMBODIMENTS <Configuration of Image Processing Apparatus> An embodiment of the present invention will be described below with reference to a screen. FIG. 2 is a configuration block diagram illustrating a configuration of the image processing apparatus according to the embodiment.

Reference numeral 10 denotes an input interface (input I / F) for receiving external data, and reference numeral 20 denotes a CPU as control means for controlling the operation of the apparatus. Note that the input I / F 10, the CPU 30, and some units described later are connected by a data bus.

Numeral 30 denotes logic setting means for latching the logic of the source data output to the data bus by the CPU 20. When the AND logic is latched, the output-side AND signal and the OR logic are latched. Outputs "1" to the OR signal on the output side. As described above, the logic of the source data is output to a part of the data bus simultaneously with the source data, and is latched by the logic setting means 30. It is not necessary to perform the latch in the logic setting means 30 every time, and it can be omitted when the same logic continues. In order to use the data bus effectively, the logic output of the source data and the output of the source data can be performed by the same data bit, and the latch by the logic setting means 30 can be performed before the output of the source data.

Reference numeral 40 denotes D for storing image data.
An image storage memory 50 composed of a RAM is a latch for temporarily storing destination data read from the DRAM when the DRAM of the image storage memory 40 is operated in a read-modify-write cycle.

Reference numeral 60 denotes a DRAM of the image storage memory 40.
Is operated in the read-modify-write cycle, the destination read from the DRAM temporarily stored in the latch 50, the source data output by the CPU 20, and the logic of the source data latched by the logic setting means 30. And a data modify circuit for generating modify data to be written to the DRAM.

Numeral 70 is a selector for selectively outputting either the source data output from the CPU 20 or the modified data output from the data modifying circuit 60 as data to be written to the DRAM. Either data is output according to the SL signal of the means.

Reference numeral 80 denotes a buffer for controlling the selector output of the selector 70. The output is controlled to a data output or a high impedance state by a BE signal of a memory control means described later.

Reference numeral 90 denotes D temporarily stored in the latch 50.
The destination data read from RAM is
This is read data determination means for determining whether all data are 0 or 1 by comparing them with a comparator.
In the case of (1), "1" is output as the output side all 0 signal, and when the data is all 1, "1" is output as the output side all 1 signal.

Numeral 100 is a write data judging means for judging whether or not the source data outputted by the CPU is all 0 or 1 by a comparator. When all the data are 0, an all 0 signal on the output side is outputted. When the data is all 1, "1" is output as the all-one signal on the output side.

Reference numeral 110 denotes an SL signal for switching the selector 70, a BL signal for controlling the buffer 80, and an image storage memory 40 based on information from the logic setting means 30, read data determination means 90, and write data determination means 100. RAS, CAS, WE, OE for control
This is a memory control unit that generates a signal.

Although the example shown here is provided with the input interface 10 and performs processing on data input from the outside, it can also be executed on data input from the same device.

<Description of Principle> Here, the principle of operation of the embodiment of the present invention will be described with reference to the flowchart of FIG.

That is, in the image processing apparatus configured as described above, the logic setting unit 30 and the write data determination unit 10
0, based on the information from the read data determination means 90, the memory control means 110 selects an access method which can be accessed at the highest speed.
0, by controlling the control signal of the buffer 80, to improve the image processing speed of the apparatus as compared with the conventional technology in which the destination data is read out from all the data, the logic is applied to the source data, and then the destination is overwritten. Can be.

FIG. 3 shows that the memory control means 110 includes the read data determination means 90 and the write data determination means 100.
And a flow of processing when selecting an access method based on information from the logic setting means 30.

The access method can be divided into the following five types. Access method 1 (AC1): neither read-modify-write nor write to the destination is performed. • Access method 2 (AC2): The source data is overwritten on the destination without performing read-modify-write. Access method 3 (AC3): The process is interrupted in the middle of the read-modify-write, and writing to the destination is not performed. Access method 4 (AC4): The process is interrupted in the middle of the read modify write, and the source data is overwritten on the destination. Access method 5 (AC5): Performs read modify write.

When logical writing starts (S1 in FIG. 3),
The memory control means 110 determines how the logic (AND, OR, etc.) of the source data is set by the logic setting means 30 (S2 in FIG. 3).

If it is determined in the determination S2 that the logic setting of the logic setting means 30 is "other", the memory control means 110 selects the access method 5 (FIG. 3: A).
C5). That is, logical writing is performed on the image storage memory 40 by a read-modify-write cycle of the DRAM.

If the logic setting of the logic setting means 30 is "OR logic" in the above determination S2, the memory control means 110 checks how the source data is determined by the write data determination means 100 ( (FIG. 3S4).

In this judgment S4, the write data judgment means 10
If the determination of “0” is “all 0”, the memory control unit 110 selects the access method 1 (FIG. 3: AC
1). That is, read-modify-write is not performed, and writing to the destination is not performed.

Further, in the judgment S4, the write data judgment means 1
When the determination of “00” is “all 1”, the memory control unit 110 selects the access method 2 (FIG. 3: AC
2). That is, the source data is overwritten on the destination without performing the read modify write.

Also, in the judgment S4, the write data judgment means 1
If the determination of “00” is “other”, the memory control unit 110 checks how the destination data is determined by the read data determination unit 90 (S4 in FIG. 3).

If the read data determination means 90 determines "all 1" in the determination S4, the memory control means 11
0 selects access method 3 (FIG. 3: AC3). In other words, the process is interrupted in the middle of the read modify write cycle of the DRAM, and writing to the destination is not performed.

In the determination S4, the read data determination means 9
When the determination of “0” is “all 0”, the memory control unit 110 selects the access method 4 (FIG. 3: AC
4). That is, the processing is interrupted in the middle of the read modify write cycle of the DRAM, and the source data is overwritten on the destination.

In the determination S4, the read data determination means 9
When the determination of 0 is “other”, the memory control unit 110 selects the access method 5 (FIG. 3: AC5).
That is, logical writing is performed by a read-modify-write cycle of the DRAM.

In the above determination S2, the logic setting means 30
Is “AND logic”, the memory control unit 110 determines that the source data is the write data determination unit 100
(S5 in FIG. 3).

If the write data determination means 100 determines "all 1" in determination S5, the memory control means 11
0 selects access method 1 (FIG. 3 (A) → AC)
1). That is, read-modify-write is not performed, and writing to the destination is not performed.

Further, in the judgment S5, the write data judgment means 1
If the determination of “00” is “all 0”, the memory control unit 110 selects the access method 2 (FIG. 3B →
AC2). That is, the source data is overwritten on the destination without performing the read modify write.

Further, in the judgment S5, the write data judgment means 1
If the determination of 00 is "other", the memory control unit 110 checks how the destination data is determined by the read data determination unit 90 (FIG. 3: S4).

If the determination by the read data determination means 90 is "all 1" in the determination S4, the memory control means 11
0 selects access method 3 (FIG. 3: AC3). In other words, the process is interrupted in the middle of the read modify write cycle of the DRAM, and writing to the destination is not performed.

In the determination S4, the read data determination means 9
When the determination of “0” is “all 0”, the memory control unit 110 selects the access method 4 (FIG. 3: AC
4). That is, the processing is interrupted in the middle of the read modify write cycle of the DRAM, and the source data is overwritten on the destination.

In the determination S4, the read data determination means 9
When the determination of 0 is “other”, the memory control unit 110 selects the access method 5 (FIG. 3: AC5).
That is, logical writing is performed by a read-modify-write cycle of the DRAM.

<Detailed Description of Operation> FIGS. 4 to 8 are time charts showing a memory access method (AC1 to AC5) in the embodiment. 4 is a time chart showing the state of AC1, FIG. 5 is a time chart showing the state of AC2, FIG. 6 is a time chart showing the state of AC3,
FIG. 7 is a time chart showing the state of AC4, and FIG.
6 is a time chart showing the state of No. 5;

In these figures, the clock is the operation clock of the CPU 20, and the subsequent timing will be described using the numbers entered every half clock cycle. Various signals shown in these figures are output signals of the memory control means 110, RAS, CAS, OE, and WE are control signals of the DRAM, and BE is a control signal of a buffer for controlling the write data output of the DRAM. is there.

In the figure, the description will be made by taking a signal that is low active as an example, but the present invention is not limited to this. First, a case of operating with the access method 1 (AC1) will be described with reference to FIG.

The RAS signal is asserted at the rise of the clock 2 to take in the row address. Then, from the rising edge of the clock 2, the information of the logic setting means 30 and the source data are output, and the logic determination of the source data and the determination of the source data are performed at the clocks 2 and 3.

In the flowchart of FIG.
If the access method 1 (AC1) is determined in the determination S3, the determination S5 (A) → AC1, and the access to the DRAM is not required, the cycle ends at the rising edge of the clock 5. However, the RAS signal needs to be negated so as to satisfy the pulse width standard.

After that, when immediately accessing a different row address of the same DRAM, it is necessary to negate the RAS signal and perform RAS precharge. Therefore, the next cycle cannot be started until the rise of eight clocks.
If the immediately following cycle accesses the same row address of the same DRAM, it is not necessary to negate the RAS signal, so the next cycle can be started from the rising edge of the clock 6.

In the cycle immediately after this, the same R
RAS is also used for devices that do not use AS signals.
Since it is not necessary to have the signal negated, the next cycle can be started from the rising edge of the clock 6.

Thus, in the read-modify-write cycle of AC5 (see FIG. 8) in which all operations are the same as those in the prior art, the access cycle required up to clock 13 is completed by clock 5 (up to 7 in some cases). Can be. Thereby, the processing can be speeded up.

Next, access method 2 (AC
The case of operating in 2) will be described. At the rising edge of the clock 2, the RAS signal is asserted to take in the row address. Further, the information of the logic setting means 30 and the source data are output from the rising edge of the clock 2, and the logic determination of the source data and the determination of the source data are performed at the clocks 2 and 3.

In the flowchart of FIG.
If the access method 2 (AC2) is determined in the determination S3 and the determination S5 (B) → AC2, WE and BE are asserted from the rise of the clock 4 and the source data is output to the DRAM data bus. CAS at falling edge of clock 4
Assert the signal and overwrite the source data with the destination. The signals RAS, CAS, WE, and BE are negated, and the cycle ends.

Thus, AC which performs the same operation as the conventional one
5 (see FIG. 8), the access cycle required until clock 13 in the read-modify-write cycle
The operation can be completed by clock 7. Thereby, the processing can be speeded up.

Next, access method 3 (AC
The case of operating in 3) will be described. At the rising edge of the clock 2, the RAS signal is asserted to take in the row address. Further, the information of the logic setting means 30 and the source data are output from the rising edge of the clock 2, and the logic determination of the source data and the determination of the source data are performed at the clocks 2 and 3.

In the flowchart of FIG.
In the judgment S4, CAS and O start from the falling edge of the clock 4.
The destination data is read from the DRAM by asserting the E signal, and the destination data is determined at clocks 5 and 6.

In the flow chart of FIG. 3 described above, when AC3 is selected by all 1s of the digital data in the judgment S4, writing is not performed and RAS, C
The AS and OE signals are negated and the cycle ends.

Thus, AC which performs the same operation as the conventional one
5 (see FIG. 8), the access cycle required until clock 13 in the read-modify-write cycle
The process can be completed by clock 9.

Next, access method 4 (AC
The case of operating in 4) will be described. At the rising edge of the clock 2, the RAS signal is asserted to take in the row address. Further, the information of the logic setting means 30 and the source data are output from the rising edge of the clock 2, and the logic determination of the source data and the determination of the source data are performed at the clocks 2 and 3.

In the flowchart of FIG.
If the determination is S4, C from the falling edge of clock 4
Assertion of the AS and OE signals causes the destination data to be read from the DRAM and the clocks 5 and 6 to be read.
To determine the destination data.

That is, in the flowchart of FIG. 3 described above, when it is determined in the determination S4 that the access method is 4 based on all 0s of the destination data, the OE is negated at the falling edge of the clock 7 and the output of the destination data is stopped. At the rising edge of the clock 8, the BE signal is asserted and the source data is output to the DRAM data bus. At the falling edge of the clock 9, the WE signal is asserted and the source data is overwritten on the destination. The signals RAS, CAS, WE, and BE are negated, and the cycle ends.

Thus, AC which performs the same operation as the conventional one
5 (see FIG. 8), the access cycle required until clock 13 in the read-modify-write cycle
The processing can be completed by clock 11.

Next, access method 5 (AC
The case of operating in 5) will be described. Access method 5
Is a conventional read-modify-write cycle. At the rising edge of the clock 2, the RAS signal is asserted to take in the row address. Further, the information of the logic setting means 30 and the source data are output from the rising edge of the clock 2, and the logic determination of the source data and the determination of the source data are performed at the clocks 2 and 3.

In the flowchart of FIG.
If the determination is S4, C from the falling edge of clock 4
Assertion of the AS and OE signals causes the destination data to be read from the DRAM, and the clock 5,
At 6, the destination data is determined.

That is, in the flowchart of FIG. 3 described above, the logic “other” or the determination S
If it is determined in step 4 that the digital data is "other" and access method 5 is determined, OE is negated at the falling edge of clock 7 and output of destination data is stopped.

By the time the clock 9 rises, the data modifying circuit prepares the modified data.
At the rising edge of the clock 10, the BE signal is asserted and the modified data is output to the DRAM data bus. The WE signal is asserted at the falling edge of the clock 11, and the modified data is overwritten on the destination.
The signals RAS, CAS, WE, and BE are negated, and the cycle ends.

As described above in detail, by selecting an access method (AC1 to AC4) in which any of read, write, and logic is omitted in accordance with the determination result, an access cycle shorter than that of the prior art can be obtained. Logical writing can be performed, and the image processing speed of the device can be improved.

[0093]

As described above in detail with the embodiments, according to the inventions described in this specification, the following effects can be obtained.

(1) According to the first and sixth aspects of the present invention, it is determined whether all the bits of a data string that can be written to the image storage memory at one time are the same, and read from the image storage memory at one time. It is determined whether all the bits of the data string that can be output are the same, and these two determination results
By referring to the logic set for the data to be written to the image storage memory, the access method to the image storage memory is changed so as to be suitable.

As a result, when the image data is stored in the image storage memory by performing the logic cling, an appropriate access can be performed according to the data and the logic, so that the processing speed can be improved.

(2) According to the second and seventh aspects of the present invention, it is determined whether all the bits of a data string which can be written to the image storage memory at one time are all the same, and this determination result is stored in the image storage memory. By referring to the logic set for the data to be written, and when the result does not change depending on the contents of the image storage memory, the access method is changed so that reading from the image storage memory is not performed.

As a result, when the image data is stored in the image storage memory by performing the logic declination, the access can be performed in a state in which the useless reading process is omitted, so that the processing speed can be improved. .

(3) According to the third and eighth aspects of the present invention, it is determined whether all bits of a data string which can be written to the image storage memory at one time are the same, and read from the image storage memory at one time. It is determined whether all the bits of the data string that can be output are the same, and by referring to these two determination results and the logic set for the data to be written to the image storage memory, the image storage memory The access method is changed so that writing to the image storage memory is not performed when the contents of the image storage do not change.

As a result, when the image data is stored in the image storage memory by performing the logic declination, the access can be performed in a state where the useless writing process is omitted, so that the processing speed can be improved. .

(4) According to the fourth and ninth aspects of the present invention, it is determined whether all bits of a data string which can be written to the image storage memory at one time are the same, and read from the image storage memory at one time. It is determined whether or not all the bits of the data string that can be output are the same, and by referring to these two determination results and the logic set for the data to be written to the image storage memory, the result can be obtained without performing the logic declination. If it can be predicted, the access method is changed so as not to clutter the logic.

As a result, when the image data is stored in the image storage memory by performing the logic cling, the access can be performed without the logic cling, so that the processing speed can be improved.

(5) According to the fifth and tenth aspects of the present invention, the data determination is performed by hardware, so that the processing can be performed at a higher speed than that performed by software. The processing speed when accessing the memory can be improved.

[Brief description of the drawings]

FIG. 1 is a flowchart showing the principle operation of image processing according to the present invention.

FIG. 2 is a block diagram illustrating an electric configuration of an image processing apparatus used in the embodiment of the present invention for each functional block.

FIG. 3 is a flowchart illustrating a procedure of image processing according to the present invention.

FIG. 4 is an access method 1 according to the embodiment of the present invention.
It is a time chart which shows the operation timing of (AC1).

FIG. 5 is an access method 2 in the embodiment of the present invention.
It is a time chart which shows the operation timing of (AC2).

FIG. 6 is an access method 3 according to the embodiment of the present invention.
It is a time chart which shows the operation timing of (AC3).

FIG. 7 is an access method 4 in the embodiment of the present invention.
It is a time chart which shows the operation timing of (AC4).

FIG. 8 is an access method 5 according to the embodiment of the present invention.
It is a time chart which shows the operation timing of (AC5).

FIG. 9 is a flowchart illustrating a procedure of a conventional image processing.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Input interface 20 CPU 30 Logic setting means 40 Image storage memory 50 Latch 60 Data modify circuit 70 Selector 80 Buffer 90 Read data judgment means 100 Write data judgment means 110 Memory control means

Claims (10)

[Claims] 1. An image processing method for storing externally input data in an image storage memory, comprising: determining whether all bits of a data string that can be written to the image storage memory at a time are all the same; Determine whether all the bits of the data string that can be read at once are the same, and refer to the two determination results and the logic set for the data to be written to the image storage memory to access the image storage memory. An image processing method, wherein the method is changed. And determining whether all bits of a data string that can be written to the image storage memory at a time are the same, and referring to the determination result and logic set for data to be written to the image storage memory. 2. The image processing method according to claim 1, wherein the access method is changed so that reading from the image storage memory is not performed. Determining whether all bits of a data string that can be written to the image storage memory at a time are all the same; and determining whether all bits of the data string that can be read from the image storage memory at a time are all the same. Referring to one of the determination results and the logic set for the data to be written to the image storage memory, changing the access method by the memory control means so as not to perform writing to the image storage memory. The image processing method according to claim 1, wherein Determining whether all bits of a data string that can be written to the image storage memory at a time are all the same, and determining whether all bits of the data string that can be read from the image storage memory at a time are all the same; With reference to the two determination results and the logic set for the data to be written to the image storage memory, an access method is set so that the logic of the data read from the image storage memory and the data to be written to the image storage memory are not shifted. The image processing method according to claim 1, wherein the method is changed. 5. The image processing method according to claim 1, wherein the two determinations are performed by a processing unit configured by hardware. 6. An image processing apparatus for storing data inputted from outside, comprising: an image storage memory for storing data; a memory control means for controlling an access method of the image storage memory; Write data determination means for determining whether all bits of a data string that can be written to the memory at once are the same, and read for determining whether all bits of the data string that can be read at a time from the image storage memory are all the same A data determination unit; and a logic setting unit for setting a logic of data to be written to the image storage memory, wherein the write data determination unit, the read data determination unit, and information from the logic setting unit determine the image data. The memory control means changes an access method to a storage memory. The image processing apparatus. 7. The memory control unit changes an access method based on information from the write data determination unit and the logic setting unit so that reading from the image storage memory is not performed. 7. The image processing device according to 6. 8. An access method is changed by said memory control means based on information from said write data judgment means, said read data judgment means and said logic setting means so as to prevent writing into said image storage memory. The image processing apparatus according to claim 6, wherein: 9. The information from the write data determination unit, the read data determination unit, and the logic setting unit is configured to prevent the logic between the data read from the image storage memory and the data to be written into the image storage memory from being performed. The image processing apparatus according to claim 6, wherein an access method is changed by the memory control unit. 10. The image processing apparatus according to claim 6, wherein the determination by the write data determination unit and the read data determination unit is performed by hardware.