JPH09198888A - Apparatus and method for writing memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily deal with the alteration of an EEPROM value during producing by copying the content of the EEPROM master inserted to a function checker board side after a function checker test is finished, and writing normal factory delivery data in an EEPROM on a main board. SOLUTION: When data is read from or written in the address corresponding to each register, an address decoder 1123 sets the decode signal to truth in each register. A counter register 1124 holds the number of times for automatically generating by the number of clocks when a CPU 108 writes the data. The CPU 108 reads the data of the EEPROM via the data and a logic circuit connected to a data bus, and writes it in an EEPROM 107 for a target. Thus, even if the value of the EEPROM 107 is altered during producing, the data can be written in the EEPROM without altering the program of the function checker board.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory writing device.

[0002]

2. Description of the Related Art Recently, an electrically erasable memory (EEPROM) has been used as a memory in many electronic devices. When writing data to such an EEPROM,
First, after checking the read / write of the EEPROM, all FFh data (data at the time of manufacturer arrival) is written, and EE
When the firmware of the target board having the PROM recognizes that all the data in the EEPROM is FFh, the factory shipment data is newly written in the EEPROM. In this process, since the writing process is performed for a long time after the power is turned on, the power may be turned off during writing. Therefore, the factory shipment data was written with the factory jig at the end of the read / write check.

Further, conventionally, in the serial EEPROM,
Signal level of I / O port can be changed from L to H by software
→ It was set to L. In that case, the clock and the data were written alternately with the clock and the data.

[0004]

However, in the former case described above, the shipping data is written by the jig for the factory. However, even if the data of the EEPROM is changed after mass production, or the same model is used. If the shipping destination is different, or if the model is the same hardware but different software, the jig program must be changed accordingly, which is difficult to handle.

In the latter case, even when the clock is automatically generated, parallel / serial conversion is performed inside the logic, and data is output in synchronization with the clock serially, EEPR
The method of writing the OM varies from company to company, and the number of clocks and the like differ depending on the manufacturer. Therefore, it was necessary to change the writing method when the type of EEPROM of the target board was changed.

Therefore, an object of the present invention is to provide a memory writing device which can cope with different factory shipment data without changing the program and can also cope with a change in the type of memory.

[0007]

In order to achieve the above object, a memory writing device according to claim 1 of the present invention is a memory writing device for writing data into a memory, wherein a master memory is mounted. A function check board for checking the function of the master memory, a target board which is connected to the function check board through a signal line, and which initializes the data of the mounted target memory. And a data writing circuit for writing the data of the master memory transferred from the check board to the target memory.

According to a second aspect of the present invention, there is provided a memory writing device according to the first aspect, wherein the memory is a serial EEPROM and the data writing circuit comprises:
A counter for setting a count number, and a clock generator for generating a clock by the set count number;
The serial EEPRO is synchronized with the generated clock.
And a data register for writing data into M.

According to a third aspect of the present invention, there is provided a memory writing method for writing data in a memory, wherein the function of the master memory mounted on the function check board is checked and the function check board and the signal line are connected. The data of the target memory mounted on the target substrate connected via the memory is initialized, and the data of the master memory transferred from the function check substrate is written to the initialized target memory.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a memory writing device of the present invention will be described. The memory writing device according to the present embodiment is applied to a function checker system.

FIG. 1 is an explanatory diagram showing the configuration of an EEPROM function checker system. In the figure,
1 is a main board as a target to be checked at the factory. In the main board 1, 101 is an expansion interface (I / F) to which an Ethernet board or the like can be connected. A hard disk drive (HDD) I / F 102 includes, for example, IDE, SCSI, and S.
It is ASI I / F.

103 is RS422 (Apple Tal)
k) I / F. Reference numeral 104 denotes an RS232C I / F, and in this apparatus, an instruction command is sent from the function checker board 2 described later to the main board 1 via the RS232C.

Reference numeral 105 is a Centronics I / F. 1
An engine I / F 06 can be connected to the printer engine. 107 is an E for writing shipping data
EPROM, 108 is a CPU that controls the operation of the main board 1 as a target.

ROM-DIs 109 and 110 are provided with a program ROM for operating this board.
It is MM. 111 is a RAM, RAM-DIMM
It is arranged in. 112 is a gate array (GA) for controlling the main board 1, 113 is a static RAM (S)
RAM).

On the other hand, in the function checker board 2 connected to the main board 1, 201 is an expansion I / O.
Expansion I for monitoring the signal line 301 connected to F101
/ F, 202 is an HDD I / F for monitoring the signal line 302 connected to the HDD I / F 102, and 203 is an RS422
RS422 I / F for monitoring the signal line 303 connected to the I / F 103, and 204 for RS232C I for monitoring the signal line 104 connected to the RS232C I / F.
/ F and 205 are Centronics I / Fs that monitor the signal line 305 connected to the Centronics I / F 105. An engine I / F 206 monitors a signal line 306 connected to the engine I / F and supplies electric power to the main board 1.

Reference numeral 207 is a master EEPROM in which factory shipping data is written. A CPU 208 controls the operation of the function checker board 2. Reference numeral 209 is a ROM in which a program for operating the faction checker board 2 is installed, 210 is a function checker panel, and 211 is a function checker monitor, which may be a notebook personal computer, for example. R for monitor 211 for the function checker
The character is sent through S232C.

Reference numeral 212 is a power supply for operating the faction checker system. 213 is a thermal printer for the function checker. Reference numeral 214 is a logic circuit for operating the function checker board 2.

Reference numeral 3 is a cable group for connecting the function checker board 2 and the main board 1, and 301 is a cable for connecting the expansion I / F. 302 is the HDD cable, 303 is the RS422 cable, and 304 is the RS2
32C cable, 305 is Centronics cable, 3
Reference numeral 05 is an engine cable.

In the function checker system, an instruction command is sent from the function checker board 2 to the main board 1 via the RS232C, the main board 1 analyzes the instruction command, and the ROM, RAM or each I / O is analyzed according to the analyzed contents. Check F

The check contents of the main board 1 are RS2
It is sent back to the function checker board 2 via 32C. The check in the present embodiment is mainly to inspect the validity of the board pattern, defective solder, and defective semiconductor before the factory shipment.

In this check, the values of the address and data of the main board 1 to be inspected are changed from 0 to 1 to 0 so that the semiconductor pins are not short-circuited next to each other or the board pattern is cut. Whether the board can operate normally, such as whether or not there is a defect in the semiconductor itself, is verified in the minimum operation time.

When the present system finally finishes the check, in the case of the main board 1 on which the EEPROM is mounted, the individual inspection of the EEPROM 107 is also performed.
The data set in the EEPROM 107 will be destroyed.

In the main board 1, the CPU 108 is the RO
An image signal as output information is output to a printing unit (printer engine) 213 connected via an engine I / F 106, which controls access to various devices based on a control program stored in the M-DIMM 109. Is output.

The CPU 108 is an RS422I which is an input unit.
/ F103, RS232C I / F104, Centronics I / F105, and expansion I / F101 can perform communication processing with a host computer (not shown). Reference numeral 111 denotes a RAM-DIMM that functions as a main memory and a work area of the CPU 108.
The memory capacity can be expanded by adding an M-DIMM option. still,
The RAM-DIMM 111 is used as an output information expansion area, an environment data storage area, an EEPROM (NVRAM), and the like.

FIG. 2 is a block diagram showing the configuration of a logic circuit incorporated in the gate array 112. In the figure, 108 is a CPU and 107 is an EEPROM. In the logic circuit inside the gate array 112, an address decoder 1123 sets a decode signal to each register to be true when data is read / written to an address corresponding to each register. Reference numeral 1124 denotes a counter register, which holds the number of times that the CPU 108 automatically generates a clock when the CPU 108 writes data. 1125 is a register for generating a CS signal, and the CPU 108 has a register 1
The CS signal is controlled by writing arbitrary data in 125.

Reference numeral 1126 is a clock generator,
The number of clocks generated by the counter register 1124 is automatically generated. Reference numeral 1127 is a read / write register for the EEPROM, which performs parallel-serial conversion when sending data to the EEPROM and conversely performs serial-parallel conversion when receiving data from the EEPROM. In this case, the expansion I / F 101 is assumed to be connected to the buffered address bus and data bus of the CPU 108. The CPU 108 reads the data in the master EEPROM 207 via the logic circuit 214 connected to the address and data buses,
Data is written in the EEPROM 107 for the target.

Further, for example, when the address data bus of the CPU 108 is not directly connected to the function checker board 2, the CPU 208 uses the Centronics I / F.
Master EEPROM using 205 or RS232C
M data is passed to the main board 1, and the data is CP
The data is temporarily saved in the RAM-DIMM 111 by U108, and the CPU 108 writes the data in the EEPROM 107.

The check operation of the EEPROM 107 will be described. FIG. 3 is a flowchart showing the data transfer processing procedure of the EEPROM. As mentioned above, EEP
The ROM 107 is a serial EEPROM and is controlled by the CPU 108 via the gate array 112. EEP
When writing data to the ROM 107, first, the CPU 1
08 writes data in the counter register 1124 (step S1). Furthermore, CPU 108 is EEPRO
When it is desired to write data in M107, the data is written in the data register 1127 (step S2).

When the writing is completed, the clock generator 112
The flag 6 is on, that is, writing and reading are prohibited. When the signal CS = H (ON), the data of the EEPROM 107 written in the data register 1127 is transferred in synchronization with the clock SK (step S4).

The data register 1127 has the EEPROM 1
Clock generator 1126 for writing data to 07
When the clock SK from No. is lost, the data transfer is ended, the flag is turned off (step S5), the signal CS = L (off) is set (step S6), and the process is ended.

As described above, if the internal data is changed by testing the EEPROM mounted on the main board in the related art, an EEPROM initialization error will occur when the power is turned on.
When the set value of the ROM is changed, the program of the function checker board 2 also needs to be changed, but in the function checker system of the present embodiment,
EEP that can be inserted on the function checker board 2 side
The ROM master is inserted in the IC socket, and the content is copied after the function checker test is completed and the normal factory shipping data is written in the EEPROM 107 on the main board 1. With such a system configuration, even if the value of the EEPROM 107 is changed during production, the data can be written in the EEPROM 107 without changing the program of the function checker board 2.

Further, even if the type of the target EEPROM is changed, the data transfer of the EEPROM can be performed without making a large modification to the program. Further, it is possible to change the number of times the clock is automatically generated by the external pins of the gate array 112 by using the external pins and jumpers without changing the program.

[0033]

According to the memory writing device of the first aspect of the present invention, when writing data to the memory, the function of the master memory is checked on the function check board on which the master memory is mounted, and the function is checked. Data of the master memory transferred from the function check board by the data write circuit provided on the target board to initialize the data of the target memory mounted on the target board connected to the check board via the signal line. Is written in the target memory, the data can be written in the memory without changing the program when the factory shipment data is different.

According to another aspect of the memory writing device of the present invention, the memory is a serial EEPROM, and the data writing circuit includes a counter for setting a count number.
Since the clock generator for generating the clock by the set count number and the data register for writing the data in the serial EEPROM in synchronization with the generated clock are provided, when the data to be transferred differs depending on the type of the serial EEPROM. However, data can be written in the serial EEPROM simply by changing the write count number.

According to the memory writing method of the third aspect, the function of the master memory mounted on the function check board is checked and mounted on the target board connected to the function check board through the signal line. Since the data of the master memory transferred from the function check board is written to the initialized target memory and the data of the master memory is written to the initialized target memory without changing the program when the factory shipment data is different. You can write

[Brief description of drawings]

FIG. 1 is an explanatory diagram showing a configuration of an EEPROM function checker system.

FIG. 2 is a block diagram showing a configuration of a logic circuit incorporated in a gate array 112.

FIG. 3 is a flowchart showing an EEPROM data transfer processing procedure.

[Explanation of symbols]

 1 Main Board 2 Function Checker Board 104, 204 RS232C I / F 107, 207 EEPROM 108, 208 CPU 112 Gate Array 1124 Counter Register 1126 Clock Generator 1127 Data Register

Claims (3)

[Claims] 1. In a memory writing device for writing data to a memory, a master memory is mounted, a function check board for checking the function of the master memory, and the function check board is connected via a signal line and mounted. A target substrate for initializing the data of the target memory, and a data writing circuit provided on the target substrate for writing the data of the master memory transferred from the function check substrate to the target memory. Characteristic memory writing device. 2. The memory is a serial EEPROM, and the data write circuit includes a counter for setting a count number, a clock generator for generating a clock for the set count number, and a clock for synchronizing with the generated clock. Then the serial EEPRO
2. The memory writing device according to claim 1, further comprising a data register for writing data into M. 3. A memory writing method for writing data to a memory, wherein the function of a master memory mounted on a function check board is checked and mounted on a target board connected to the function check board via a signal line. A method for writing data in a memory, wherein the data in the target memory is initialized, and the data in the master memory transferred from the function check board is written in the initialized target memory.