JPH09190405A - Interruption controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the occurrence of illegal interruption by outputting an interruption release signal when address data coincide with each other and releasing the interruption processing of CPU. SOLUTION: When CPU 11 access to an I/O address 12, address data showing this accessed I/O address is outputted to an FIFO buffer 13. The FIFO buffer 13 sequentially stores address data showing the address read out by CPU 11. Then comparator 15 stores the pattern of a specific address and outputs the interruption release signal when the pattern of address data stored in the FIFO buffer 13 and the pattern of stored specific address data coincide with each other. In addition when the interruption release signal is outputted from the comparator 15, an interruption controller 16 releases the interruption of CPU 11.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interrupt controller, and more particularly to an interrupt controller used in a computer system.

[0002]

2. Description of the Related Art In a conventional interrupt control device, as shown in FIG. 7, the interrupt is released by outputting an interrupt release signal from the I / O module 1 to the interrupt controller 2.

The method of outputting an interrupt release signal from the I / O module 1 has been performed by the following method, for example. 1. A method of outputting an interrupt release signal by reading data of a specific I / O address from the CPU 1.

[0004] 2. A method of outputting an interrupt release signal by writing data from the CPU 1 to a specific I / O address. 3. A method of outputting an interrupt release signal by writing specific data from the CPU 1 to a specific I / O address.

[0005]

However, in the interrupt method of the interrupt control device having the above-mentioned configuration, I
/ O is assigned to memory (memory-mapped I / O
O), and when applied to a system in which the user can freely read and write the memory contents by using a maintenance tool, the following problems occur.

Now, as shown in FIG. 8, the memory area used by the maintenance tool has addresses 1000H to 1F.
Assume FFH. First, in the case of the method of releasing the interrupt by reading the memory, as shown in the flowchart of FIG. 9, by reading the memory from the maintenance tool, the address A to which the interrupt release is assigned even though it is originally not desired to release the interrupt. In some cases, data may be read from the memory, resulting in the output of the interrupt release signal.

That is, an interrupt is canceled in a process other than the interrupt process, so that an illegal interrupt (malfunction) occurs. In such a case,
In the interrupt processing as shown in 0, it becomes impossible to specify the interrupt factor from which I / O module is outputting the interrupt request, and as a result, the interrupt processing becomes impossible.

Further, even when the interrupt is released by writing to the memory, if the maintenance tool writes the data to the address assigned to the interrupt release by the memory writing, the interrupt release signal is output.

Even in such a case, in the interrupt processing, it becomes impossible to specify the interrupt factor from which I / O module the interrupt request is output, and the interrupt processing cannot be performed.

Further, also in the case of the method of writing specific data from the CPU 1 to a specific I / O address, the problem that the interrupt release signal is unduly output occurs as described above.

The present invention has been made in view of the above circumstances, and is a highly reliable interrupt that does not cause an illegal interrupt (malfunction) caused by an interrupt release signal being output in a process other than the interrupt process. An object is to provide a control device.

[0012]

Therefore, first of all, in order to achieve the above object, the invention according to claim 1 is an interrupt control device for canceling an interrupt process by accessing a predetermined I / O address by a CPU. In address data storage means for sequentially storing a plurality of address data of I / O addresses accessed by the CPU, address data stored by the address data storage means, and a plurality of preset address data. Interrupt release signal output means for outputting an interrupt release signal when they match, and interrupt release means for releasing the interrupt processing of the CPU based on the interrupt release signal output from the interrupt release signal output means. It is characterized by

According to a second aspect of the present invention, in the interrupt control device according to the first aspect, address data clear means for clearing a plurality of I / O address data stored in the address data storage means is added. Is characterized by.

Further, the invention according to claim 3 is the invention according to claim 2.
In the interrupt control device described above, the address data clearing means clears the address data stored in the address data storage means, at every minimum access interval time with respect to the I / O address of the CPU.

Further, in the invention according to claim 4, in the interrupt control device for canceling interrupt processing by writing predetermined data to a predetermined I / O address by the CPU, the CPU controls the predetermined I / O address. An interrupt release signal is output when write data storage means for sequentially storing a plurality of written write data, the write data stored by the write data storage means, and a plurality of preset write data match And an interrupt releasing means for releasing interrupt processing of the CPU based on the interrupt releasing signal output from the interrupt releasing signal outputting means.

Further, the invention according to claim 5 is the invention according to claim 4.
The interrupt control device described above is characterized in that a write data clear means for clearing a plurality of write data stored in the write data storage means is added.

Further, the invention according to claim 6 is the invention according to claim 5.
In the interrupt control device described above, the process of clearing the write data stored in the write data storage unit by the write data clear unit is performed at every minimum access interval time with respect to the I / O address of the CPU.

According to the first aspect of the present invention, the address data storage means sequentially stores a plurality of address data of I / O addresses accessed by the CPU, and the interrupt release signal output means stores the address data storage means. When the generated address data matches a plurality of preset address data, the interrupt release signal is output. Then, the interrupt canceling means cancels the interrupt processing of the CPU based on the interrupt canceling signal output from the interrupt canceling signal output means, so that the interrupt canceling signal is erroneously output and the interrupt processing is not canceled. .

According to the second aspect of the present invention, the address data clearing means clears the plurality of I / O address data stored in the address data storing means. Therefore, the interrupt release signal is erroneously output more reliably. Can be prevented.

According to the third aspect of the present invention, the address data clearing means clears the I / O address data stored in the address data storage means at every minimum access interval time with respect to the I / O address of the CPU. Furthermore, it is possible to prevent the interruption processing from being interrupted and the malfunction from occurring as a result of the erroneous output of the interruption cancellation signal.

According to a fourth aspect of the present invention, the write data storage means sequentially stores a plurality of write data written by the CPU at a predetermined I / O address, and the interrupt release signal output means outputs the write data storage means. When the stored write data matches a plurality of preset write data, the interrupt release signal is output. Then, the interrupt canceling means cancels the interrupt processing of the CPU based on the interrupt canceling signal output from the interrupt canceling signal output means, so that the interrupt canceling signal is erroneously output and the interrupt processing is not canceled. .

In the invention according to claim 5, the plurality of write data stored in the write data storage means are cleared by the data clear means, so that the interrupt release signal is more surely prevented from being erroneously output. be able to.

In the invention according to claim 6, the data clearing means clears a plurality of write data stored in the write data storing means at every minimum access interval time with respect to the I / O address of the CPU. ,
As a result of the erroneous output of the interrupt release signal, it is possible to prevent interrupt processing from being interrupted and causing a malfunction.

[0024]

Embodiments of the present invention will be described below with reference to the drawings. <First Embodiment> FIG. 1 is a diagram showing a configuration of an interrupt control device according to a first embodiment of the present invention.

As shown in the figure, the interrupt control device according to the present embodiment has a FIFO buffer 13 and a timer 1.
4, a comparator 15, and an interrupt controller 16. When the CPU 11 accesses the I / O address 12, this I / O address 12 is accessed.
Address data indicating the / O address is output to the FIFO buffer 13.

The FIFO buffer 13 sequentially stores the address data indicating the I / O address read by the CPU 11. Here, the FIFO buffer 13 is configured to be able to store two address data.

The timer 14 clears the contents of the address data stored in the FIFO buffer 13 when the I / O address 12 is not accessed by the CPU 11 within a preset time.

The comparator 15 stores a specific address pattern, and releases the interrupt when the pattern of the address data stored in the FIFO buffer 13 matches the specific pattern of the stored specific address data. Output a signal.

In this case, the comparator 15 has 2
It is assumed that one address data (B, A) is stored. When the interrupt cancel signal is output from the comparator 15, the interrupt controller 16 cancels the interrupt of the CPU 11.

Next, the operation of the interrupt control device configured as described above will be described. Here, the reading of the memory by the maintenance tool is, as shown in FIG. 2 and FIG. 3, the I / O address 1000H → address 1FFF.
It is assumed that reading is performed in the H direction.

Further, it is assumed that the comparator 15 stores (address B, address A) as a specific address pattern. Now, with the maintenance tool,
When the CPU 11 reads the addresses A to E among the I / O addresses shown in FIG. 1 in the direction of I / O address 1000H → address 1FFFFH, the FIFO buffer 13 stores (A, B) → (B, C). ) → (C, D) →
It is stored in the order of (D, E).

On the other hand, since (B, A) is stored in the comparator 15, there is no case where the contents of the FIFO buffer 13 and the contents stored in the comparator 15 match, and as a result, an interrupt occurs. The interrupt cancellation signal for canceling is not output to the interrupt controller 16.

That is, by storing an address pattern in which the interrupt release signal is not erroneously output in the comparator 15, the interrupt release signal is erroneously output when the memory is read from the maintenance tool,
As a result, malfunction does not occur.

When the interrupt processing is performed, as shown in FIG. 4, after the interrupt processing is performed, the I / O address B and the I / O address A are sequentially read from the CPU 11 to address the FIFO buffer 13. (B,
A) are stored sequentially, resulting in comparator 1
An interrupt release signal is output from 5 to the interrupt controller 16.

Then, the interrupt controller 16 terminates the interrupt processing of the CPU 11 based on the interrupt release signal output from the comparator 15. Further, the timer 14 keeps the I / O address 1 from the CPU 11 for a certain period of time.
If No. 2 is not accessed, the address data stored in the FIFO buffer 13 is cleared.

With this timer 14, the FIFO buffer 1
The time interval for clearing the contents of 3 is, for example, the CPU 11
Is set to the minimum access interval time for the I / O address.

As a result, even when the CPU 11 first accesses the address A to the address B and then accesses the address A with a time interval, the FIFO buffer 13 is provided between the first access and the second access. Since the content of the address data stored in is cleared, the content of the comparator 15 does not match the content of the FIFO buffer 13.

Therefore, the interrupt release signal is not output from the comparator 15, and as a result, the interrupt controller 16
Does not interrupt the CPU 11. In the above description, the interrupt release signal is output based on the address read by the CPU 11, but the interrupt release signal may be output from the comparator 22 based on the address written by the CPU 11. good.

Therefore, according to the interrupt control device of the present embodiment, when the maintenance tool reads the memory, the interrupt release signal is erroneously output, so that the interrupt process is not performed. It is possible to prevent the generation of an illegal interrupt due to a malfunction. <Second Embodiment> FIG. 5 is a diagram showing the configuration of an interrupt control device according to a second embodiment of the present invention. The same parts as those in FIG. 1 are designated by the same reference numerals, and the description thereof will be omitted. Here, only different parts will be described.

The difference between the interrupt control device according to the first embodiment and the interrupt control device according to the present embodiment lies in the pattern of addresses set in the comparator.
The case where the address (B, A) is registered as a pattern in the comparator 15 in the above-described first embodiment has been described, but the comparator 21 of the interrupt control device in the present embodiment has the same configuration as in FIG. As shown, the address (A, D, B,
C) is registered as a pattern.

By setting a complicated address pattern in the comparator 21 in this way, it is possible to more reliably prevent malfunction due to an illegal interrupt, as compared with the interrupt control device according to the first embodiment. You can <Third Embodiment> FIG. 6 is a diagram showing a configuration of an interrupt control device according to a third embodiment of the present invention. The same parts as those in FIG. 1 are designated by the same reference numerals, and the description thereof will be omitted. Here, only different parts will be described.

The difference between the interrupt control device according to the first embodiment and the interrupt control device according to the present embodiment is that the address data is not stored in the comparator but is written in the I / O address. Data is stored in the comparator, and the interrupt release signal is output by comparing the data written in the I / O address with the data stored in the comparator.

As shown in the figure, when the CPU 11 writes data to the I / O address 12 in the interrupt control device of the present embodiment, the written data is stored in the FIFO.
It is configured to be output to the buffer 13.

Further, the comparator 22 stores predetermined write data, and here, "K", "E",
The data "Y" is stored. The FIFO buffer 13 sequentially stores the write data output from the I / O address 12.

Then, the comparator 22 outputs an interrupt release signal to the interrupt controller 16 when the write data stored in the FIFO buffer 13 and the write data stored in the comparator 22 match.

The interrupt controller 16 includes a comparator 22.
When the interrupt release signal is input from, the interrupt processing of the CPU 11 is ended. As described in the description of the first embodiment above, the function of the timer 14 is that the I / O address 12 is sent to the CP within the predetermined time set beforehand.
If the specified data is not written by U11,
The contents of the data written in the FIFO buffer 13 are cleared.

If the interrupt control devices according to the above-described first to third embodiments are applied to the I / O output device, it is possible to suppress the above output due to a user's operation error or runaway.

Therefore, also in the interrupt control device according to the present embodiment, like the interrupt control device described in the above-mentioned first embodiment, the interrupt release signal is erroneously mistaken when the memory is read by the maintenance tool. Is output, interrupt processing is not performed, so that it is possible to prevent occurrence of an illegal interrupt due to a malfunction.

[0049]

As described above in detail, according to the present invention,
It is possible to provide a highly reliable interrupt control device that does not generate an illegal interrupt (malfunction) caused by the output of an interrupt release signal in a process other than the interrupt process.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of an interrupt control device according to a first embodiment of the present invention.

FIG. 2 is a diagram for explaining a memory area used by the maintenance tool of the interrupt control device in the embodiment.

FIG. 3 is a flowchart for explaining memory reading by the maintenance tool of the interrupt control device in the embodiment.

FIG. 4 is a flowchart for explaining an interrupt processing routine of the interrupt control device in the same embodiment.

FIG. 5 is a diagram showing a configuration of an interrupt control device according to a second embodiment of the present invention.

FIG. 6 is a diagram showing a configuration of an interrupt control device according to a third embodiment of the present invention.

FIG. 7 is a diagram showing a configuration of a conventional interrupt control device.

FIG. 8 is a diagram for explaining a memory area used by the maintenance tool.

FIG. 9 is a flowchart for explaining memory reading by a maintenance tool.

FIG. 10 is a flowchart illustrating an interrupt processing routine.

[Explanation of symbols]

11 ... CPU, 12 ... I / O address, 13 ... FIFO
Buffer, 14 ... Timer, 15 ... Comparator, 16 ... Interrupt controller, 21, 22 ... Comparator.

Claims (6)

[Claims] 1. An interrupt control device for canceling interrupt processing by accessing a predetermined I / O address by a CPU, wherein an address for sequentially storing a plurality of address data of I / O addresses accessed by the CPU Data storage means, interrupt release signal output means for outputting an interrupt release signal when the address data stored by the address data storage means and a plurality of preset address data match, and the interrupt release signal output And an interrupt canceling unit for canceling the interrupt processing of the CPU based on the interrupt canceling signal output from the interrupt controlling unit. 2. The interrupt control device according to claim 1, further comprising address data clearing means for clearing a plurality of I / O address data stored in the address data storing means. 3. The address data clearing means for clearing the address data stored in the address data storage means is performed at every minimum access interval time to the I / O address of the CPU. The interrupt control device described. 4. An interrupt control device for canceling interrupt processing by writing predetermined data to a predetermined I / O address by a CPU, wherein a plurality of write data written by the CPU to a predetermined I / O address are written. Write data storage means for sequentially storing, write data stored by the write data storage means, and interrupt release signal output means for outputting an interrupt release signal when a plurality of preset write data match, An interrupt control device, comprising: an interrupt release means for releasing interrupt processing of the CPU based on an interrupt release signal output from the interrupt release signal output means. 5. The interrupt control device according to claim 4, further comprising write data clear means for clearing a plurality of write data stored in the write data storage means. 6. The write data clearing process by the write data clearing unit is performed at every minimum access interval time with respect to an I / O address of the CPU. The interrupt control device described.