JPH09186287A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH09186287A
JPH09186287A JP7352992A JP35299295A JPH09186287A JP H09186287 A JPH09186287 A JP H09186287A JP 7352992 A JP7352992 A JP 7352992A JP 35299295 A JP35299295 A JP 35299295A JP H09186287 A JPH09186287 A JP H09186287A
Authority
JP
Japan
Prior art keywords
package
heat
semiconductor device
lead frame
sub
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7352992A
Other languages
Japanese (ja)
Inventor
Yoshio Yokota
芳夫 横田
Koji Furusato
広治 古里
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shindengen Electric Manufacturing Co Ltd
Original Assignee
Shindengen Electric Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shindengen Electric Manufacturing Co Ltd filed Critical Shindengen Electric Manufacturing Co Ltd
Priority to JP7352992A priority Critical patent/JPH09186287A/en
Publication of JPH09186287A publication Critical patent/JPH09186287A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601Structure
    • H01L2224/0603Bonding areas having different sizes, e.g. different heights or widths
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4911Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49171Fan-out arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49175Parallel arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/494Connecting portions
    • H01L2224/4943Connecting portions the connecting portions being staggered
    • H01L2224/49431Connecting portions the connecting portions being staggered on the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • H01L2924/13091Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having a uniform heat distribution without using an insulating board. SOLUTION: When lead frames 51 to 519 electrically insulated from each other are provided in the package of a multi-chip module 2 formed of sealing material and a plurality of electronic components including at least two or more heating components 61 , 62 and one or more sub-chips 31 , 32 are mounted thereon, the two or more components 61 , 62 are disposed on lead frames 51 , 52 disposed at both ends in a package 7. Mounting means 111 , 112 for mounting radiating fins are provided at both ends of the package. Even if an insulating board is not provided, the temperature distribution becomes uniform. When the frames 51 , 52 disposed with the components 61 , 62 are widely formed, the distribution becomes further uniform.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は絶縁基板を用いない
半導体装置の技術分野にかかり、特に、複数の発熱部品
を有するマルチチップモジュールに関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the technical field of semiconductor devices that do not use an insulating substrate, and more particularly to a multi-chip module having a plurality of heat-generating components.

【0002】[0002]

【従来の技術】近年は、電子装置の小型・高密度化が増
々進んでおり、従来では個別部品で使用されていたパワ
ーデバイスも、駆動回路や保護回路とを共に1つのパッ
ケージ内に組み込まれた半導体装置として用いられる場
合が多くなって来た。そのような従来技術の半導体装置
はハイブリッドICと呼ばれており、そのパッケージの
中に複数のパワーデバイスを納める場合には、熱分布の
均一性を向上させ、同時にパワーデバイス間を電気的に
絶縁させるために、アルミナ等のセラミック材料で作ら
れた絶縁基板上にパワーデバイスを搭載することが行わ
れていた。
2. Description of the Related Art In recent years, the size and density of electronic devices have been increasing, and power devices, which have been conventionally used as individual components, have both a drive circuit and a protection circuit incorporated in one package. It has been increasingly used as a semiconductor device. Such a conventional semiconductor device is called a hybrid IC, and when a plurality of power devices are housed in the package, the uniformity of heat distribution is improved and at the same time the power devices are electrically insulated. In order to do so, a power device has been mounted on an insulating substrate made of a ceramic material such as alumina.

【0003】従来技術のハイブリッドICを、図2
(a)、(b)の符号102に示して説明すると、このハイ
ブリッドIC102は、5個の端子108と、エポキシ
樹脂で構成された1個のパッケージ107とを有してお
り、このパッケージ107内には、アルミナで構成され
た絶縁基板109が設けられている。
A prior art hybrid IC is shown in FIG.
The hybrid IC 102 has five terminals 108 and one package 107 made of epoxy resin. Is provided with an insulating substrate 109 made of alumina.

【0004】絶縁基板109表面には、互いに電気的に
絶縁された銅配線膜101a、101bが設けられ、各銅
配線膜101a、101b上に、パワーデバイス106
a、106bが半田によって固定されている。この絶縁基
板109上には、銅配線101a、101bと絶縁して回
路領域112が設けられており、該回路領域112内に
は、図示しない電子部品と共にサブチップ103a、1
03bが配置され、絶縁基板109によってパワーデバ
イス106a、106bと熱結合するように構成されてい
る。
Copper wiring films 101a and 101b electrically insulated from each other are provided on the surface of the insulating substrate 109, and the power device 106 is provided on each of the copper wiring films 101a and 101b.
a and 106b are fixed by solder. A circuit region 112 is provided on the insulating substrate 109 so as to be insulated from the copper wirings 101a and 101b. Within the circuit region 112, sub-chips 103a, 1
03b are arranged and configured to be thermally coupled to the power devices 106a and 106b by the insulating substrate 109.

【0005】前記パワーデバイス106a、106bは絶
縁基板109表面の上方位置に配置され、他方、回路領
域112は、絶縁基板109表面の下方位置に配置され
ており、該回路領域112内に設けられたボンディング
パッド114と、絶縁基板109下方に分離して配置さ
れた端子108とが金線ワイヤー104によって接続し
やすいように構成されている。
The power devices 106a and 106b are arranged above the surface of the insulating substrate 109, while the circuit region 112 is arranged below the surface of the insulating substrate 109 and provided in the circuit region 112. The bonding pad 114 and the terminal 108 separately arranged below the insulating substrate 109 are configured to be easily connected by the gold wire 104.

【0006】また、各パワーデバイス106a、106b
は、その表面に設けられたボンディングパッドが金線ワ
イヤー104によって回路領域112内のボンディング
パッドにそれぞれ接続され、回路領域112を介してコ
ントロールIC106a、106bや端子108に接続さ
れており、更に、各パワーデバイス106a、106bの
底面は、前記銅配線101a、101bに接続された金線
ワイヤー104によって、それぞれ端子108に接続さ
れている。同様に、サブチップ103a、103b表面に
設けられたボンディングパッドは金線ワイヤー104に
よって、回路領域112を介してそれぞれ端子108に
接続されている。
Further, each power device 106a, 106b
The bonding pads provided on the surface are connected to the bonding pads in the circuit area 112 by the gold wire 104, respectively, and are connected to the control ICs 106a and 106b and the terminals 108 via the circuit area 112. The bottom surfaces of the power devices 106a and 106b are connected to the terminals 108 by the gold wire 104 connected to the copper wirings 101a and 101b, respectively. Similarly, the bonding pads provided on the surfaces of the sub chips 103a and 103b are connected to the terminals 108 by the gold wire 104 through the circuit region 112, respectively.

【0007】このようなハイブリッドIC102では、
絶縁基板112上にパワーデバイス106a、106bが
配置されていることから、パワーデバイス106a、1
06bが発生する熱は、絶縁基板112を伝わってパッ
ケージ107内に分散されるため、パッケージ107内
の熱分布が均一となり、また、その絶縁基板109によ
って、直接回路領域112が熱せられるため、サブチッ
プ103a、103b内の温度分布も均一となることか
ら、従来より、大きな電流を扱う回路に広く使用されて
いる。
In such a hybrid IC 102,
Since the power devices 106a and 106b are arranged on the insulating substrate 112, the power devices 106a and 1
The heat generated by 06b is transmitted through the insulating substrate 112 and dispersed in the package 107, so that the heat distribution in the package 107 becomes uniform, and the insulating substrate 109 directly heats the circuit region 112. Since the temperature distribution in 103a and 103b is also uniform, it has been widely used in circuits that handle large currents.

【0008】しかしながらコスト低減のため、絶縁基板
109の削減が求められており、近年では、絶縁基板1
09や銅薄膜101a、101bに代え、アルミニウムや
銅合金等の金属材料で構成され、互いに分離されたリー
ドフレーム上に直接半導体チップ等の電子部品を搭載し
たハイブリッドICが用いられるようになってきた。
However, in order to reduce the cost, reduction of the insulating substrate 109 is required, and in recent years, the insulating substrate 1 has been reduced.
09 or copper thin films 101a and 101b, hybrid ICs made of a metal material such as aluminum or a copper alloy and having electronic components such as semiconductor chips directly mounted on lead frames separated from each other have come to be used. .

【0009】このようなリードフレームは、互いに電気
的に絶縁されるように形成されているので、搭載する電
子部品間を金線ワイヤーボンディングで接続し、一端を
端子状に成形してパッケージ外部へ導出することで、プ
リント基板上に実装できるハイブリッドICを構成でき
ることから、近年注目されている。
Since such a lead frame is formed so as to be electrically insulated from each other, the electronic parts to be mounted are connected by gold wire wire bonding, and one end is molded into a terminal shape to the outside of the package. By deriving it, a hybrid IC that can be mounted on a printed circuit board can be configured, and thus has been attracting attention in recent years.

【0010】ところが、そのようなハイブリッドICで
は、内部に配置された電子部品同士の熱結合は、パッケ
ージを構成する封止材料で行われる。そのような封止材
料は、金属やセラミックに比べて熱伝導率の低いエポキ
シ樹脂等のモールド材が用いられるのが普通であるた
め、従来のハイブリッドICと同じように電子部品を配
置した場合には、パッケージ内の熱分布が不均一にな
り、部分的に温度上昇をしてしまうという問題があっ
た。このような不均一な熱分布は、熱放散効率を低下さ
せるばかりでなく、サブチップ内の温度分布も不均一と
なった場合には、熱バランスの問題からサブチップ内の
回路誤動作を招く場合もあり、その解決が望まれてい
た。
However, in such a hybrid IC, the thermal coupling between the electronic components arranged inside is performed by the sealing material that constitutes the package. As such a sealing material, a molding material such as epoxy resin, which has a lower thermal conductivity than metals and ceramics, is usually used, and therefore, when electronic parts are arranged in the same manner as in a conventional hybrid IC. However, there is a problem that the heat distribution in the package becomes non-uniform and the temperature rises partially. Such non-uniform heat distribution not only lowers the heat dissipation efficiency, but when the temperature distribution in the sub-chip is also non-uniform, it may cause circuit malfunction in the sub-chip due to heat balance problem. , The solution was desired.

【0011】[0011]

【発明が解決しようとする課題】本発明は上記従来技術
の不都合を解決するために創作されたもので、その目的
は、絶縁基板を用いなくても均一な熱分布を得ることが
できる半導体装置を提供することにある。
The present invention was created in order to solve the above-mentioned disadvantages of the prior art, and its purpose is to obtain a semiconductor device capable of obtaining a uniform heat distribution without using an insulating substrate. To provide.

【0012】[0012]

【課題を解決するための手段】上記課題を解決するため
に、請求項1記載の発明は、封止材料で構成されたパッ
ケージと、互いに接触しないように構成され、前記パッ
ケージ内部に納められるリードフレームと、少なくとも
2個以上の発熱部品と1個以上のサブチップとを含んだ
複数の電子部品とを有し、前記電子部品が前記リードフ
レーム上に設けられた半導体装置であって、前記パッケ
ージの平面形状は長方形に成形され、その両端には半導
体装置を放熱フィンに密着固定させるための取付手段が
設けられ、前記パッケージの温度分布を均一にするよう
に構成されたことを特徴とし、
In order to solve the above-mentioned problems, the invention according to claim 1 is configured such that a package made of a sealing material and a lead housed inside the package are configured so as not to come into contact with each other. A semiconductor device having a frame and a plurality of electronic components including at least two or more heat-generating components and one or more sub-chips, wherein the electronic components are provided on the lead frame. The planar shape is formed in a rectangular shape, and mounting means for closely fixing the semiconductor device to the heat radiation fins is provided at both ends thereof, and the temperature distribution of the package is made uniform,

【0013】請求項2記載の発明は、封止材料で構成さ
れたパッケージと、互いに接触しないように構成され、
前記パッケージ内部に納められるリードフレームと、少
なくとも2個以上の発熱部品と1個以上のサブチップと
を含んだ複数の電子部品とを有し、前記電子部品が前記
リードフレーム上に設けられた半導体装置であって、前
記発熱部品は前記パッケージ内の両端に位置するリード
フレーム上に設けられ、前記パッケージの温度分布を均
一にするように構成されたことを特徴とし、
According to a second aspect of the present invention, a package made of a sealing material is configured so as not to contact each other,
A semiconductor device having a lead frame housed inside the package, and a plurality of electronic components including at least two or more heat generating components and one or more sub chips, the electronic components being provided on the lead frame. The heat generating component is provided on lead frames located at both ends in the package, and is configured to make the temperature distribution of the package uniform,

【0014】請求項3記載の発明は、請求項1又は請求
項2のいずれか1項記載の半導体装置であって、前記発
熱部品が設けられたリードフレームの面積は、その上に
位置する発熱部品の面積の2倍以上になるように形成さ
れたことを特徴とする。
According to a third aspect of the present invention, in the semiconductor device according to any one of the first and second aspects, the area of the lead frame on which the heat generating component is provided has a heat generation position above the lead frame. It is characterized in that it is formed to be more than twice the area of the component.

【0015】上述した本発明の構成によれば、封止材料
で構成された半導体装置のパッケージ内に、リードフレ
ームを設ける際、各リードフレームを互いに接触しない
ように構成し、互いに電気的に絶縁されるようにしたの
で、その表面には少なくとも2個以上の発熱部品と1個
以上のサブチップとが含まれる複数の電子部品を搭載す
ることが可能となる。
According to the above-described structure of the present invention, when the lead frames are provided in the package of the semiconductor device made of the encapsulating material, the lead frames are configured so as not to contact each other, and are electrically insulated from each other. Since this is done, it becomes possible to mount a plurality of electronic components including at least two or more heat generating components and one or more sub chips on the surface thereof.

【0016】このような半導体装置では、剛体となる絶
縁基板を内蔵していないため、パッケージには温度上昇
による反りや歪みが生じやすいが、前記パッケージの平
面形状を長方形に成形しておき、そのパッケージの両端
に半導体装置を放熱フィンに密着固定させるための取付
手段を設け、発熱部品をパッケージの両端に配置してお
けば、パッケージにそりが生じた場合でも、パッケージ
内で最も発熱する部分を放熱フィンに密着させることが
できるので、半導体装置の放熱性が向上し、熱分布も均
一にすることができる。また、発熱部品をパッケージの
両端に位置するリードフレーム上に設けるようにすれ
ば、絶縁基板を設けなくても熱分布を均一にでき、更
に、発熱部品の間にサブチップを位置させれば、発熱部
品とサブチップとの距離を大きくすることができ、サブ
チップ内の温度勾配をなだらかにすることができる。
In such a semiconductor device, since a rigid insulating substrate is not built in, the package is apt to warp or distort due to a temperature rise. If mounting means for closely fixing the semiconductor device to the heat radiation fins is provided at both ends of the package, and heat-generating components are arranged at both ends of the package, even if the package is warped, the portion that generates the most heat in the package can be provided. Since it can be closely attached to the heat dissipation fin, the heat dissipation of the semiconductor device is improved and the heat distribution can be made uniform. In addition, if the heat-generating components are provided on the lead frames located at both ends of the package, the heat distribution can be made uniform without providing an insulating substrate. The distance between the component and the sub chip can be increased, and the temperature gradient in the sub chip can be made gentle.

【0017】また、前記発熱部品が配置されるリードフ
レームを幅広に形成しておくと、前記発熱部品が発生す
る熱がそのリードフレームを伝わって前記パッケージ内
に拡散されるので、前記パッケージ内の熱分布を一層均
一にすることができる。この場合、リードフレームの面
積を、その上に配置される発熱部品の面積の2倍以上の
面積になるようにしておくと均熱性がよい。
If the lead frame on which the heat-generating component is arranged is formed wide, the heat generated by the heat-generating component is transferred to the lead frame and diffused into the package. The heat distribution can be made more uniform. In this case, the soaking property is good when the area of the lead frame is set to be twice or more the area of the heat-generating component arranged thereon.

【0018】[0018]

【発明の実施の形態】本発明の実施の形態を図面を用い
て説明する。図1を参照し、符号2は本発明の一実施の
形態の半導体装置であり、一般にはマルチチップモジュ
ールと呼ばれているものである。このマルチチップモジ
ュール2は、このパッケージ7は、エポキシ樹脂がトラ
ンスファーモールドによって成形されて成るパッケージ
7を有しており、該パッケージ7は、厚み約4mm、平
面は約50mm×20mmの長方形形状になるようにさ
れている。
Embodiments of the present invention will be described with reference to the drawings. Referring to FIG. 1, reference numeral 2 is a semiconductor device according to an embodiment of the present invention, which is generally called a multi-chip module. This multi-chip module 2 has a package 7 formed by transfer molding of epoxy resin. The package 7 has a rectangular shape with a thickness of about 4 mm and a plane of about 50 mm × 20 mm. Is being done.

【0019】その内部にはリードフレーム51〜519
納められており、各リードフレーム51〜519の一端
は、パッケージ7の一側面に並べられ、棒状に成形され
た端子81〜819が電気的・機械的に接続されている。
また、各端子81〜819がパッケージ7長辺の一側面か
ら導出され、後工程でZIP(ジグザグインラインパッ
ケージ)型の端子配列に成形できるようにされている。
Lead frames 5 1 to 5 19 are housed inside, and one end of each of the lead frames 5 1 to 5 19 is arranged on one side surface of the package 7 and formed into a rod-shaped terminal 8 1 to. 8 19 are electrically and mechanically connected.
Further, each of the terminals 8 1 to 8 19 is led out from one side surface of the long side of the package 7 and can be formed into a ZIP (zigzag inline package) type terminal array in a later step.

【0020】各リードフレーム51〜519は予め互いに
分離するように成形されており、トランスファーモール
ドの際には各端子81〜819を連設するタイバーによっ
て一体に取り扱えるようにされているが、パッケージ7
の形成後、前記タイバーが切断されて各端子81〜819
が分離されると、各リードフレーム51〜519の電気的
短絡状態が解消されるように構成されている。
The lead frames 5 1 to 5 19 are formed in advance so as to be separated from each other, and can be integrally handled by a tie bar that connects the terminals 8 1 to 8 19 in series during transfer molding. But package 7
After the formation of the tie bar, the tie bar is cut and each of the terminals 8 1 to 8 19 is cut.
Is separated, the electrical short-circuit state of each of the lead frames 5 1 to 5 19 is eliminated.

【0021】各リードフレーム51〜519は電気導電性
を有する銅合金で構成されており、それらのうち、両端
に位置するリードフレーム51、519には、大面積に形
成されたダイボンディング部131、132が設けられて
おり、各ダイボンディング部131、132上には、発熱
部品であるパワーMOS-FETチップ61、62が配置
され、それぞれ半田付けで固定されている。このリード
フレーム51、519の面積は、その上に配置されるパワ
ーMOS-FETチップ61、62の面積の2倍以上にな
るようにされており、熱抵抗が小さくなるように構成さ
れている。
Each of the lead frames 5 1 to 5 19 is made of a copper alloy having electrical conductivity. Among them, the lead frames 5 1 and 5 19 located at both ends have a die formed in a large area. Bonding portions 13 1 and 13 2 are provided, and power MOS-FET chips 6 1 and 6 2 which are heat-generating components are arranged on the die bonding portions 13 1 and 13 2 and fixed by soldering. ing. The areas of the lead frames 5 1 and 5 19 are made to be at least twice as large as the areas of the power MOS-FET chips 6 1 and 6 2 arranged thereon, and the thermal resistance is reduced. Has been done.

【0022】前記リードフレーム51、519には、でき
るだけ幅広で、パッケージ7全体に熱が伝わるように、
電流経路以外の部分にも張り出し部101、102が形成
されており、パワーMOS-FETチップ61、62が発
熱したときに、その熱が各リードフレーム51、519
伝わって、パッケージ7内で電子部品が配置されていな
い部分にも熱分配がされ、パッケージ7全体の温度分布
が均一になるように構成されている。
The lead frames 5 1 , 5 19 are as wide as possible so that heat can be transferred to the entire package 7.
Overhangs 10 1 and 10 2 are also formed in portions other than the current path, and when the power MOS-FET chips 6 1 and 6 2 generate heat, the heat is transmitted to the lead frames 5 1 and 5 19. The heat distribution is performed even in a portion of the package 7 where no electronic component is arranged, so that the temperature distribution of the entire package 7 becomes uniform.

【0023】前記2つのパワーMOS-FETチップ
1、62は、前記端子81〜819が導出される側面から
離れた位置に、互いに離間して配置されており、パッケ
ージ7内ではその長手方向の両端付近(左右付近)に位置
するようにされている。また、各パワーMOS-FET
チップ61、62は、パッケージ7の短辺からの距離と、
互いの間隔とが略等しくなるように分散して配置されて
おり、各パワーMOS-FET61、62に電流が流れて
発熱したときに、その熱がパッケージ7内に均一に分配
されるように構成されている。
The two power MOS-FET chips 6 1 and 6 2 are arranged apart from each other at a position away from the side surface from which the terminals 8 1 to 8 19 are led out. It is located near both ends (near left and right) in the longitudinal direction. In addition, each power MOS-FET
Chips 6 1 and 6 2 are the distance from the short side of the package 7,
The power MOS-FETs 6 1 and 6 2 are arranged so as to be spaced apart from each other so as to be substantially equal to each other, and when the current flows through each of the power MOS-FETs 6 1 and 6 2 to generate heat, the heat is uniformly distributed in the package 7. Is configured.

【0024】また、各パワーMOS-FETチップ61
2の中間位置には、リードフレーム516の幅広に形成
された先端部分が位置されており、その表面上には電子
部品であるサブチップ32が銀ペーストによって固定さ
れている。従って、各パワーMOS-FETチップ61
2が発熱したときは、サブチップ32は均等に加熱さ
れ、このチップ内で熱分布の不均一が生じないようにさ
れている。
In addition, each power MOS-FET chip 6 1 ,
A wide tip portion of the lead frame 5 16 is located at an intermediate position of 6 2 , and a sub chip 3 2 which is an electronic component is fixed on the surface by a silver paste. Therefore, each power MOS-FET chip 6 1 ,
When 6 2 generates heat, the sub-chip 3 2 is evenly heated so that uneven heat distribution does not occur in this chip.

【0025】また、リードフレーム510の先端部分は幅
広に形成され、パッケージ7の前記各端子81〜819
導出される付近であって、前記ダイボンディング部13
1、132から略等距離のところに位置しており、その表
面には電子部品であるサブチップ31が銀ペーストで固
定されている。従って、このサブチップ32は、2つの
パワーMOS-FETチップ61、62から略等距離のと
ころにあり、各パワーMOS-FETチップ61、62
発熱を均等に受けて、チップ内で熱分布の不均一が生じ
ないようにされている。
Further, the tip portion of the lead frame 5 10 is formed wider, a nearby each terminal 8 1-8 19 package 7 is derived, the die bonding portion 13
1, 13 2 is located at a substantially equal distance from the sub chip 3 1 is fixed with a silver paste which is an electronic component on the surface. Therefore, the sub chip 3 2 are 1 two power MOS-FET chip 6, from 6 2 at a substantially equal distance, equally subjected to heat generation of the power MOS-FET chip 6 1, 6 2, in the chip In order to prevent uneven heat distribution.

【0026】前述のサブチップ31、32は、パワーMO
S-FETチップ61、62を駆動・制御するコントロー
ルICであり、サブチップ31、32表面に設けられたボ
ンディングパッド間は、チップ間を接続する金線ワイヤ
ー4aによって接続され、サブチップ31、32の内部回
路同士が互いに電気的に接続されるように構成されてい
る。また、サブチップ31、32上の他のボンディングパ
ッドと、パワーMOS-FET61、62表面のボンディ
ングパッドとは、チップとリードフレームとを接続する
金線ワイヤー4bによって、リードフレーム82〜818
それぞれ接続されており、端子81〜819をプリント基
板に挿入し、半田付けによって実装すると、このマルチ
チップモジュール2を動作させられるように構成されて
いる。
The above-mentioned sub chips 3 1 and 3 2 have a power MO.
This is a control IC for driving and controlling the S-FET chips 6 1 , 6 2 , and the bonding pads provided on the surface of the sub chips 3 1 , 3 2 are connected by a gold wire 4a for connecting the chips to each other. 1, 3 2 of the internal circuit to each other are configured so as to be electrically connected to each other. Further, the other bonding pads on the sub chips 3 1 and 3 2 and the bonding pads on the surface of the power MOS-FETs 6 1 and 6 2 are connected to the lead frame 8 2 through the gold wire 4b for connecting the chip and the lead frame. 8 18 are respectively connected to, and insert the pin 8 1-8 19 on the printed circuit board and implemented by soldering, is configured to be operated with this multi-chip module 2.

【0027】このパッケージ7の裏面は滑らかに形成さ
れており、プリント基板へ実装する際に、マルチチップ
モジュール2の裏面に放熱フィンを密着・固定させてお
けば熱放散を大きくできるようにされている。一般的
に、エポキシ樹脂のトランスファーモールドで成形した
パッケージにおいて、内部に剛体となる絶縁基板を有さ
ない場合は、リードフレーム表面部と裏面部のエポキシ
樹脂の厚みの相違によって、加熱されたときに長手方向
に反りが生じやすいことが知られている。このマルチチ
ップモジュール2では、前記パワーMOS-FETチッ
プ61、62は前記パッケージ7の短辺付近に位置してお
り、その短辺上には取付手段である孔111、112が設
けられているので、各孔111、112と放熱フィンにね
じを挿通し、マルチチップモジュール2を放熱フィンに
ねじ止め固定すると、パッケージ7の長手方向に反りが
生じるようなときでも、パワーMOS-FETチップ
1、62が位置する発熱部分と放熱フィンとの密着を維
持できるようにされている。
The back surface of the package 7 is formed smoothly, and when mounted on a printed circuit board, a heat radiation fin can be adhered and fixed to the back surface of the multi-chip module 2 to increase heat dissipation. There is. Generally, in a package formed by transfer molding of epoxy resin, when there is no rigid insulating substrate inside, when heated due to the difference in the thickness of the epoxy resin on the front and back of the lead frame It is known that warpage is likely to occur in the longitudinal direction. In this multi-chip module 2, the power MOS-FET chips 6 1 and 6 2 are located near the short side of the package 7, and holes 11 1 and 11 2 as mounting means are provided on the short side. Therefore, if screws are inserted into the holes 11 1 and 11 2 and the heat radiation fins and the multi-chip module 2 is screwed and fixed to the heat radiation fins, even if the package 7 warps in the longitudinal direction, the power MOS -It is possible to maintain close contact between the heat generating portions where the FET chips 6 1 and 6 2 are located and the heat radiation fins.

【0028】以上は、発熱部品として2個のパワーMO
S-FETチップ61、62を有するマルチチップモジュ
ール2について説明したが、発熱部品の個数はそれに限
定されるものではない。発熱部品を3個有する場合は、
それらを三角形の頂点上の位置に配置し、更に、サブチ
ップをその三角形の中央付近に配置するとよい。発熱部
品が4個の場合は、各発熱部品が四角形の頂点上の位置
に配置し、更に、その四角形の中央付近にサブチップを
配置するとよい。発熱部品が5個以上の場合も同様であ
る。それらの場合、各サブチップが各発熱部品から略等
距離の位置に置かれるようにすれば、サブチップ内の熱
分布の均一性が高まって都合がよい。
Above, two power MOs are used as heat-generating components.
Although the multi-chip module 2 having the S-FET chips 6 1 and 6 2 has been described, the number of heat-generating components is not limited to that. If you have 3 heating components,
It is advisable to arrange them at the positions on the vertices of the triangle, and further arrange the sub-chips near the center of the triangle. When there are four heat-generating components, each heat-generating component may be arranged at a position on the apex of the quadrangle, and the sub chip may be arranged near the center of the quadrangle. The same applies when the number of heat-generating components is five or more. In those cases, it is convenient to arrange each sub-chip at a position approximately equidistant from each heat-generating component because the uniformity of heat distribution in the sub-chip is enhanced.

【0029】なお、上述の発熱部品はパワーMOS-F
ETに限定されるものではなく、バイポーラートランジ
スタチップやサイリスタチップ等、マルチチップモジュ
ール内に実装可能な電子部品であって使用の際に発熱す
るものが広く含まれる。また、パッケージの材質もエポ
キシ樹脂に限定されるものではなく、例えばシリコン樹
脂等のマルチチップモジュールパッケージを構成できる
材料が広く含まれる。電子部品をリードフレームへ固定
する材料については、上述のように、半田や銀ペースト
に限定されるものではない。リードフレームの材質も、
電気伝導性があり、電子部品が搭載できるものであれば
よいが、熱伝導性が高いことが望ましい。
The above-mentioned heat-generating component is a power MOS-F.
The invention is not limited to ET, but widely includes electronic components that can be mounted in a multi-chip module, such as a bipolar transistor chip and a thyristor chip, that generate heat when used. Further, the material of the package is not limited to the epoxy resin, and a wide range of materials such as silicon resin that can form a multi-chip module package are included. As described above, the material for fixing the electronic component to the lead frame is not limited to solder or silver paste. The material of the lead frame is also
Any material that has electrical conductivity and on which electronic components can be mounted may be used, but high thermal conductivity is desirable.

【0030】[0030]

【発明の効果】絶縁基板を内蔵しなくても、マルチチッ
プモジュールの熱分布を均一にすることができる。ま
た、サブチップ内の熱分布が不均一にならず、誤動作を
生じない。マルチチップモジュールのパッケージにそり
や歪みが生じた場合でも、発熱部分が放熱フィンから離
れることがない。
The heat distribution of the multi-chip module can be made uniform without incorporating an insulating substrate. Further, the heat distribution in the sub chip does not become non-uniform, and no malfunction occurs. Even if warpage or distortion occurs in the package of the multi-chip module, the heat generating portion does not separate from the heat radiation fin.

【図面の簡単な説明】[Brief description of the drawings]

【図1】 本発明の一実施の形態のマルチチップモジュ
ールの平面図
FIG. 1 is a plan view of a multi-chip module according to an embodiment of the present invention.

【図2】 (a):従来技術のハイブリッドICの斜視図 (b):その内部を説明するための図FIG. 2A is a perspective view of a conventional hybrid IC. FIG. 2B is a diagram for explaining the inside.

【符号の説明】[Explanation of symbols]

2……マルチチップモジュール 31、32……サブチ
ップ 51〜519……リードフレーム 61、62……発熱部
品 7……パッケージ 111、112……取付手段
2 ... Multi-chip module 3 1 , 3 2 ...... Sub chip 5 1 to 5 19 ...... Lead frame 6 1 , 6 2 ...... Heat generating component 7 ...... Package 11 1 , 11 2 ...... Mounting means

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 封止材料で構成されたパッケージと、 互いに接触しないように構成され、前記パッケージ内部
に納められるリードフレームと、 少なくとも2個以上の発熱部品と1個以上のサブチップ
とを含んだ複数の電子部品とを有し、 前記電子部品が前記リードフレーム上に設けられた半導
体装置であって、 前記パッケージの平面形状は長方形に成形され、その両
端には放熱フィンを密着固定させるための取付手段が設
けられ、 前記パッケージの温度分布を均一にするように構成され
たことを特徴とする半導体装置。
1. A package including a package made of an encapsulating material, a lead frame configured so as not to contact each other and housed inside the package, at least two or more heat-generating components, and one or more sub-chips. A semiconductor device having a plurality of electronic components, wherein the electronic components are provided on the lead frame, wherein the planar shape of the package is formed into a rectangle, and both ends of the package are provided for closely fixing heat radiation fins. A semiconductor device, comprising mounting means, configured to make the temperature distribution of the package uniform.
【請求項2】 封止材料で構成されたパッケージと、 互いに接触しないように構成され、前記パッケージ内部
に納められるリードフレームと、 少なくとも2個以上の発熱部品と1個以上のサブチップ
とを含んだ複数の電子部品とを有し、 前記電子部品が前記リードフレーム上に設けられた半導
体装置であって、 前記発熱部品は前記パッケージ内の両端に位置するリー
ドフレーム上に設けられ、 前記パッケージの温度分布を均一にするように構成され
たことを特徴とする半導体装置。
2. A package including a package made of an encapsulating material, a lead frame configured so as not to come into contact with each other and housed inside the package, at least two or more heat-generating components, and one or more sub-chips. A semiconductor device having a plurality of electronic components, wherein the electronic components are provided on the lead frame, wherein the heat generating components are provided on lead frames located at both ends in the package, and the temperature of the package is A semiconductor device having a uniform distribution.
【請求項3】 前記発熱部品が設けられたリードフレー
ムの面積は、その上に位置する発熱部品の面積の2倍以
上になるように形成されたことを特徴とする請求項1又
は請求項2のいずれか1項記載の半導体装置。
3. The lead frame provided with the heat-generating component is formed to have an area that is at least twice as large as the area of the heat-generating component located on the lead frame. The semiconductor device according to claim 1.
JP7352992A 1995-12-28 1995-12-28 Semiconductor device Pending JPH09186287A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7352992A JPH09186287A (en) 1995-12-28 1995-12-28 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7352992A JPH09186287A (en) 1995-12-28 1995-12-28 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH09186287A true JPH09186287A (en) 1997-07-15

Family

ID=18427839

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7352992A Pending JPH09186287A (en) 1995-12-28 1995-12-28 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH09186287A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010107556A (en) * 2000-05-23 2001-12-07 가나이 쓰토무 A Semiconductor Device and A Method of Manufacturing the Same
JP2007116012A (en) * 2005-10-24 2007-05-10 Renesas Technology Corp Semiconductor device and power supply using same
US9299628B2 (en) 2011-07-11 2016-03-29 Mitsubishi Electric Corporation Power semiconductor module

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010107556A (en) * 2000-05-23 2001-12-07 가나이 쓰토무 A Semiconductor Device and A Method of Manufacturing the Same
JP2007116012A (en) * 2005-10-24 2007-05-10 Renesas Technology Corp Semiconductor device and power supply using same
US9299628B2 (en) 2011-07-11 2016-03-29 Mitsubishi Electric Corporation Power semiconductor module

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