JPH09186178A - Manufacture of compound semiconductor device - Google Patents
Manufacture of compound semiconductor deviceInfo
- Publication number
- JPH09186178A JPH09186178A JP7343402A JP34340295A JPH09186178A JP H09186178 A JPH09186178 A JP H09186178A JP 7343402 A JP7343402 A JP 7343402A JP 34340295 A JP34340295 A JP 34340295A JP H09186178 A JPH09186178 A JP H09186178A
- Authority
- JP
- Japan
- Prior art keywords
- compound semiconductor
- layer
- opening
- gate electrode
- etched
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 43
- 150000001875 compounds Chemical class 0.000 title claims abstract description 37
- 238000004519 manufacturing process Methods 0.000 title claims description 18
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 150000004767 nitrides Chemical class 0.000 claims abstract description 19
- 238000000034 method Methods 0.000 claims description 2
- 238000002161 passivation Methods 0.000 abstract description 28
- 230000002633 protecting effect Effects 0.000 abstract description 3
- 230000008020 evaporation Effects 0.000 abstract 1
- 238000001704 evaporation Methods 0.000 abstract 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 44
- 238000005530 etching Methods 0.000 description 15
- 239000012071 phase Substances 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000007740 vapor deposition Methods 0.000 description 3
- 238000005275 alloying Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000000927 vapour-phase epitaxy Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0891—Source or drain regions of field-effect devices of field-effect transistors with Schottky gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66848—Unipolar field-effect transistors with a Schottky gate, i.e. MESFET
- H01L29/66856—Unipolar field-effect transistors with a Schottky gate, i.e. MESFET with an active layer made of a group 13/15 material
- H01L29/66863—Lateral single gate transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
- H01L29/812—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a Schottky gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
- H01L29/812—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a Schottky gate
- H01L29/8128—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a Schottky gate with recessed gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Junction Field-Effect Transistors (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、化合物半導体装置
に係り、特にＧａＡｓ ＭＥＳＦＥＴ（Metal Semicond
uctor Field Effect Transistor）、ＨＥＭＴ（High El
ectron MobilityTransistor)等のデバイスの製造方法に
関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a compound semiconductor device, and more particularly to a GaAs MESFET (Metal Semiconductor).
uctor Field Effect Transistor), HEMT (High El
ectron Mobility Transistor) and other devices.
【０００２】[0002]
【従来の技術】ＧａＡｓ ＭＥＳＦＥＴ、ＨＥＭＴ等の
デバイスは、電子の移動度が高く、超高速・超高周波用
途のデバイスとして好適であり、近年携帯電話等の用途
に広く用いられている。しかしながら、このＧａＡｓデ
バイスは、パッシベーション（表面保護）がシリコンデ
バイスと比較して難しく、発振用の素子として用いる場
合には、位相雑音の改善、高出力用の素子として用いる
場合には、高出力化、高利得化、高効率化、直線性の改
善等が要請されている。2. Description of the Related Art Devices such as GaAs MESFETs and HEMTs have high electron mobility and are suitable as devices for ultra high speed and ultra high frequency applications, and have been widely used in applications such as mobile phones in recent years. However, this GaAs device is more difficult to passivate (surface protection) than a silicon device, and when used as an element for oscillation, phase noise is improved, and when used as an element for high output, high output is achieved. There is a demand for higher gain, higher efficiency, and improved linearity.
【０００３】図９は、従来のＧａＡｓパワーＭＥＳＦＥ
Ｔの構造の一例を示す。半絶縁性ＧａＡｓ基板１０上に
バッファ層を介してチャネル領域となるｎ型ＧａＡｓ層
１１を備え、ソース電極１４とドレイン電極１５間に流
れる電流が、ゲート電極１３によってチャネル領域１１
内に形成される空乏層の広がりで制御されるようになっ
ている。ゲート電極１３は、ｎ型ＧａＡｓ層のリセスエ
ッチ部１８に形成され、直接ｎ型ＧａＡｓ層１１と接触
することにより、ショットキ接合を形成している。FIG. 9 shows a conventional GaAs power MESFE.
An example of the structure of T is shown. An n-type GaAs layer 11 serving as a channel region is provided on a semi-insulating GaAs substrate 10 via a buffer layer, and a current flowing between the source electrode 14 and the drain electrode 15 is applied to the channel region 11 by the gate electrode 13.
It is controlled by the spread of the depletion layer formed inside. The gate electrode 13 is formed in the recessed etching portion 18 of the n-type GaAs layer and directly contacts the n-type GaAs layer 11 to form a Schottky junction.
【０００４】チャネル領域となるｎ型ＧａＡｓ層１１の
表面上のソース・ドレイン電極１４、１５とゲート電極
１３間には、アンドープＧａＡｓ層２０がパッシベーシ
ョン（保護）層として設けられている。ｎ型ＧａＡｓ層
１１の表面には、パッシベーション層がないと表面準位
が多く存在して、このため厚い自然空乏層が形成され、
その部分はキャリアが存在できず、電流が流れにくくな
るという、いわゆるチャネルの狭窄現象が大きくなるこ
とが知られている。係るチャネルの狭窄現象は、ＧａＡ
ｓデバイスの高出力化、高効率化等の妨げとなり、又、
入出力の直線性を劣化させる。又、表面準位は前述した
発振素子としてのＧａＡｓデバイスにおいては、位相雑
音の原因にもなる。An undoped GaAs layer 20 is provided as a passivation layer between the source / drain electrodes 14 and 15 and the gate electrode 13 on the surface of the n-type GaAs layer 11 serving as a channel region. If there is no passivation layer on the surface of the n-type GaAs layer 11, many surface states exist, and thus a thick natural depletion layer is formed,
It is known that a so-called channel constriction phenomenon, in which carriers cannot exist in that portion and a current hardly flows, becomes large. The constriction phenomenon of the channel is GaA.
hinders higher output and higher efficiency of s devices, and
I / O linearity is degraded. Further, the surface level also causes phase noise in the above-mentioned GaAs device as an oscillating element.
【０００５】このため、従来、アンドープ（Undoped）
ＧａＡｓ層２０を、パッシベーション層としてエピタキ
シャル成長等によりｎ型ＧａＡｓ層（チャネル領域）１
１上に連続して形成することが広く行われており、上述
した表面準位によるいろいろな問題を防止することがで
きる。尚、電気的には、アンドープＧａＡｓ層１１は絶
縁体として働く。Therefore, conventionally, undoped
The n-type GaAs layer (channel region) 1 is formed by epitaxial growth using the GaAs layer 20 as a passivation layer.
It is widely practiced to continuously form on the first layer, and it is possible to prevent various problems due to the above surface states. Incidentally, electrically, the undoped GaAs layer 11 acts as an insulator.
【０００６】[0006]
【発明が解決しようとする課題】しかしながら、図９に
示すように、ソース・ドレイン間の抵抗値を調整し、ゲ
ート・ドレイン間耐圧を上げるためｎ型ＧａＡｓ層１１
を少しリセスエッチングすると、ゲート電極近傍のリセ
スエッチ部１８にパッシベーション層２０に覆われてい
ないｎ型ＧａＡｓ層１１の表面が露出した部分である隙
間Ｓが形成される。この隙間Ｓは、ＧａＡｓ ＭＥＳＦ
ＥＴのゲート電極１３の近傍に形成されるため、パッシ
ベーション層の欠落により、十分な表面保護効果が得ら
れなくなるという問題がある。又、このような問題があ
るため、リセスエッチング深さが制限され、ソース・ド
レイン間の抵抗値調整を十分に行えず、又、ゲート・ド
レイン間の耐圧を十分に上げられないという問題が生じ
る。However, as shown in FIG. 9, the n-type GaAs layer 11 is used to adjust the resistance value between the source and drain and increase the breakdown voltage between the gate and drain.
Is slightly etched to form a gap S, which is a portion where the surface of the n-type GaAs layer 11 that is not covered with the passivation layer 20 is exposed, in the recessed etching portion 18 near the gate electrode. This gap S is GaAs MESF
Since it is formed in the vicinity of the ET gate electrode 13, there is a problem that a sufficient surface protection effect cannot be obtained due to the lack of the passivation layer. Further, due to such a problem, the recess etching depth is limited, the resistance value between the source and the drain cannot be adjusted sufficiently, and the breakdown voltage between the gate and the drain cannot be increased sufficiently. .
【０００７】本発明は上述した事情に鑑みて為されたも
ので、パッシベーション膜をゲート電極近傍に隙間なく
形成できると共に、リセスエッチ部にゲート電極を自己
整合した化合物半導体装置の製造方法を提供することを
目的とする。The present invention has been made in view of the above-mentioned circumstances, and provides a method of manufacturing a compound semiconductor device in which a passivation film can be formed in the vicinity of a gate electrode without a gap and a gate electrode is self-aligned with a recessed etch portion. With the goal.
【０００８】[0008]
【課題を解決するための手段】本発明の化合物半導体装
置は、化合物半導体基板上に酸化膜又は窒化膜を配設
し、該酸化膜又は窒化膜に開口を設け、該開口より化合
物半導体基板をリセスエッチし、該リセスエッチした部
分にアンドープ化合物半導体層を選択的にエピ成長し、
前記開口より該アンドープ半導体層をエッチングして前
記半導体基板表面を露出させ、更に前記開口より前記化
合物半導体とショットキ接合を形成するゲート電極を設
けたことを特徴とする。In a compound semiconductor device of the present invention, an oxide film or a nitride film is provided on a compound semiconductor substrate, an opening is provided in the oxide film or the nitride film, and the compound semiconductor substrate is opened from the opening. Recess etching, selectively epitaxially growing an undoped compound semiconductor layer on the recess-etched portion,
The undoped semiconductor layer is etched through the opening to expose the surface of the semiconductor substrate, and a gate electrode for forming a Schottky junction with the compound semiconductor is further provided through the opening.
【０００９】本発明は、化合物半導体基板上に被着した
酸化膜又は窒化膜に開口を設け、その開口より化合物半
導体基板をリセスエッチし、リセスエッチした部分に埋
込パッシベーション層となる化合物半導体膜を選択的に
エピ成長する。そして、同じ酸化膜又は窒化膜の開口か
ら埋込パッシベーション層をエッチングして、ゲート電
極を形成するものである。従って、リセスエッチした部
分には埋込パッシベーション層が充填され、同じ酸化膜
又は窒化膜の開口からリセスエッチ部に自己整合したゲ
ート電極が形成される。それ故、係る化合物半導体装置
の製造方法によれば、ゲート電極の近傍の化合物半導体
基板の表面が隙間なくパッシベーション層で覆われ、且
つゲート電極がリセスエッチ部に自己整合したデバイス
を製造することができる。According to the present invention, an opening is provided in an oxide film or a nitride film deposited on a compound semiconductor substrate, the compound semiconductor substrate is recess-etched through the opening, and a compound semiconductor film to be a buried passivation layer is selected in the recess-etched portion. To grow epitaxially. Then, the buried passivation layer is etched through the opening of the same oxide film or nitride film to form the gate electrode. Therefore, the recessed etched portion is filled with the buried passivation layer, and a gate electrode self-aligned with the recessed etched portion is formed from the opening of the same oxide film or nitride film. Therefore, according to the method for manufacturing a compound semiconductor device, it is possible to manufacture a device in which the surface of the compound semiconductor substrate in the vicinity of the gate electrode is covered with the passivation layer without any gap, and the gate electrode is self-aligned with the recessed etch portion. .
【００１０】[0010]
【発明の実施の形態】以下、図１乃至図８を参照しなが
ら、本発明の化合物半導体装置の構造及びその製造方法
について説明する。尚、各図中、同一符号は同一又は相
当部分を示す。BEST MODE FOR CARRYING OUT THE INVENTION The structure of a compound semiconductor device of the present invention and its manufacturing method will be described below with reference to FIGS. In the drawings, the same reference numerals indicate the same or corresponding parts.
【００１１】図１は本発明の一実施の形態の化合物半導
体装置の完成段階の断面図である。このＧａＡｓデバイ
スの構造は、図９に示した従来技術のデバイスと異な
り、ゲート電極１３が配設されたリセスエッチ部分１８
が埋込パッシベーション層であるＧａＩｎＰ層２１によ
って完全に埋まっている。そして、ゲート電極１３が埋
込パッシベーション層２１の中に配設されているので、
リセスエッチ部分１８のｎ型又はｎ＋型ＧａＡｓ層１
１、１１Ａの表面が隙間なくパッシベーション層１８に
より覆われている。このため、従来のデバイスがリセス
エッチ部１８でパッシベーション層２０に覆われていな
い隙間Ｓを有する構造と比較して、パッシベーション層
の効果を完全に発揮できる構造となっている。FIG. 1 is a sectional view of a compound semiconductor device according to an embodiment of the present invention at the completion stage. The structure of this GaAs device is different from that of the prior art device shown in FIG.
Are completely buried by the GaInP layer 21 which is a buried passivation layer. Since the gate electrode 13 is provided in the buried passivation layer 21,
N-type or n + -type GaAs layer 1 of recessed etched portion 18
The surfaces of 1 and 11A are covered with the passivation layer 18 without any gap. For this reason, the structure of the conventional device can fully exert the effect of the passivation layer as compared with the structure of the conventional device having the gap S not covered with the passivation layer 20 in the recessed etch portion 18.
【００１２】そして、ゲート電極１３はリセスエッチ部
１８に対して自己整合している。即ち、リセスエッチ部
１８は酸化膜又は窒化膜１７の開口１７Ｈからエッチン
グが行われる。又、ゲート電極１３も酸化膜又は窒化膜
１７の開口１７Ｈから同様に蒸着により形成される。こ
のため、ゲート電極１３は、リセスエッチ部１８の中央
部分に自己整合で位置決めされる。The gate electrode 13 is self-aligned with the recess etching portion 18. That is, the recess etching portion 18 is etched from the opening 17H of the oxide film or the nitride film 17. Further, the gate electrode 13 is similarly formed by vapor deposition from the opening 17H of the oxide film or the nitride film 17. Therefore, the gate electrode 13 is self-aligned with the central portion of the recess etching portion 18.
【００１３】ゲート電極のリセスエッチ部１８に対する
位置合わせは、ゲート電極幅が例えば１２ＧＨｚ帯では
０．３〜０．８μｍ程度であり、１〜２ＧＨｚ帯では
０．８〜１．５μｍ程度と微細であるため、この位置合
わせ精度の製造歩留まりに及ぼす影響は大変大きい。従
って、ステッパーを使用しない通常の光学式のマスク合
わせ装置ではマスクずれにより製造歩留まりが大変悪く
なるという問題がある。従って、ゲート電極を自己整合
（セルフアライン）とすることにより容易に製造歩留ま
りを向上させることができる。The alignment of the gate electrode with respect to the recessed etching portion 18 is as fine as about 0.3 to 0.8 μm in the 12 GHz band and about 0.8 to 1.5 μm in the 1 to 2 GHz band. Therefore, the effect of this alignment accuracy on the manufacturing yield is very large. Therefore, in a normal optical mask aligner that does not use a stepper, there is a problem in that the manufacturing yield is greatly deteriorated due to the mask shift. Therefore, the manufacturing yield can be easily improved by making the gate electrodes self-aligned.
【００１４】その他の構造は、従来の構造と基本的に同
様である。リセスエッチ部分のｎ型ＧａＡｓ層１１上に
は、Ｔｉ／Ａｌ等のゲート電極１３が直接接触すること
により、ショットキ接合が形成されている。また、ｎ型
ＧａＡｓ層１１上には、ＡｕＧｅ／Ｎｉ／Ａｕ等からな
るソース電極１４及びドレイン電極１５が直接接触する
ことにより、オーミック接触が形成されている。The other structure is basically the same as the conventional structure. A Schottky junction is formed on the n-type GaAs layer 11 in the recessed etching portion by direct contact with the gate electrode 13 such as Ti / Al. In addition, ohmic contact is formed on the n-type GaAs layer 11 by directly contacting the source electrode 14 and the drain electrode 15 made of AuGe / Ni / Au or the like.
【００１５】又、このＧａＡｓデバイスは、ｎ型ＧａＡ
ｓ層１１を保護するパッシベーション層として、ＧａＡ
ｓ層１１に格子整合したアンドープＧａＩｎＰ層２０、
２１を備えている。ＧａｘＩｎＹＰのＸとＹの成分比を
概略０．５と０．５程度とすることにより、ＧａＩｎＰ
層２０，２１はＧａＡｓ層１１に格子整合することがで
きる。アンドープＧａＩｎＰ層２０，２１は、ｎ型Ｇａ
Ａｓ層１１に対してパッシベーション（保護）層として
機能する。そして、結晶としてはＧａＡｓ層１１と格子
整合しているため、ＧａＡｓ層１１内での表面準位の生
成を減少させることができる。このため、自然空乏層の
厚みを薄くでき、チャネルの狭窄現象を軽減でき、パワ
ーデバイスの出力特性、入出力の直線性等を改善するこ
とができる。又、発振素子においては、位相雑音を低減
できる。Further, this GaAs device is an n-type GaA
GaA is used as a passivation layer for protecting the s layer 11.
an undoped GaInP layer 20 lattice-matched to the s layer 11,
21. By setting the component ratio of X and Y of GaxInYP to about 0.5 and 0.5, GaInP
Layers 20 and 21 can be lattice matched to GaAs layer 11. The undoped GaInP layers 20 and 21 are made of n-type Ga.
It functions as a passivation (protection) layer for the As layer 11. Since the crystal is lattice-matched with the GaAs layer 11, the generation of surface states in the GaAs layer 11 can be reduced. Therefore, the thickness of the natural depletion layer can be reduced, the channel confinement phenomenon can be reduced, and the output characteristics of the power device, the linearity of input / output, and the like can be improved. Moreover, in the oscillator, phase noise can be reduced.
【００１６】図２から図８は本発明の一実施の形態の化
合物半導体装置の製造工程の断面図である。図２は、本
実施の形態のＧａＡｓ ＭＥＳＦＥＴの製造に使用する
基板を示す。この基板は半絶縁性のＧａＡｓ基板１０上
にバッファ層を介してチャネル領域となるｎ型ＧａＡｓ
層１１をエピタキシャル成長により形成したものであ
る。そして、さらにその上に、高不純物濃度（ｎ＋型）
ＧａＡｓ層１１Ａをエピタキシャル成長により形成した
ものである。そして、さらにその上層にはパッシベーシ
ョン膜となる、ＧａＡｓ層に格子整合したＧａＩｎＰ層
２０がエピタキシャル成長により形成されている。2 to 8 are cross-sectional views of a manufacturing process of a compound semiconductor device according to one embodiment of the present invention. FIG. 2 shows a substrate used for manufacturing the GaAs MESFET of this embodiment. This substrate is an n-type GaAs substrate which is a channel region on a semi-insulating GaAs substrate 10 via a buffer layer.
The layer 11 is formed by epitaxial growth. And on top of that, high impurity concentration (n + type)
The GaAs layer 11A is formed by epitaxial growth. Further, a GaInP layer 20, which is a passivation film and is lattice-matched with the GaAs layer, is further formed thereon by epitaxial growth.
【００１７】図３は、上述した基板に酸化膜又は窒化膜
１７を気相成長により被着したものである。図３に示す
酸化膜又は窒化膜１７上にホトレジストを全面に塗布す
る。そして、ホトレジスト膜を現像、露光して開口を形
成する。次に、そのレジスト膜をマスクとして窒化膜又
は酸化膜１７の開口１７Ｈを形成する。そして、パッシ
ベーション膜となるＧａＩｎＰ層２０を、塩酸系エッチ
ャントを用いてエッチングする。そして、次に、酸化膜
又は窒化膜の開口１７Ｈ及びＧａＩｎＰ層の開口からｎ
＋型ＧａＡｓ層１１Ａ及びｎ型ＧａＡｓ層１１をリセス
エッチングする。FIG. 3 shows an oxide film or a nitride film 17 deposited on the above-mentioned substrate by vapor phase epitaxy. A photoresist is coated on the entire surface of the oxide film or nitride film 17 shown in FIG. Then, the photoresist film is developed and exposed to form an opening. Next, using the resist film as a mask, an opening 17H of the nitride film or the oxide film 17 is formed. Then, the GaInP layer 20 to be the passivation film is etched using a hydrochloric acid-based etchant. Then, from the opening 17H of the oxide film or the nitride film and the opening of the GaInP layer,
The + type GaAs layer 11A and the n type GaAs layer 11 are recess-etched.
【００１８】図４は、リセスエッチ部１８を形成した段
階を示す。上述したリセスエッチングは、ドライ又はウ
ェットで、ソース・ドレイン間電流ＩＤＤＳ 及びコン
ダクタンスｇｍが適当な所望値となるようにエッチング
する。FIG. 4 shows a step in which the recessed etching portion 18 is formed. The above-described recess etching is dry or wet so that the source-drain current IDDS and the conductance gm have appropriate desired values.
【００１９】図５は、ｎ型ＧａＡｓ層１１のリセスエッ
チ部１８にパッシベーション膜となるＧａＩｎＰ層２１
を選択エピタキシャル成長して埋め込んだ段階を示す。
このＧａＩｎＰ層２１は、有機金属（ＭＯ）ＣＶＤ又は
分子線エピタキシャルにより形成する。下地のＧａＡｓ
層と格子整合したＧａＩｎＰのエピタキシャル成長層
は、酸化膜又は窒化膜１７上には、堆積せずリセスエッ
チしたＧａＡｓ層の表面が露出した部分にのみ成長す
る。このため、図示するようにリセスエッチ部１８を埋
めることができる。FIG. 5 shows a GaInP layer 21 serving as a passivation film in the recessed etching portion 18 of the n-type GaAs layer 11.
This shows a stage in which is selectively epitaxially grown and embedded.
This GaInP layer 21 is formed by metal organic (MO) CVD or molecular beam epitaxy. Underlayer GaAs
The GaInP epitaxial growth layer lattice-matched with the layer grows only on the oxide film or the nitride film 17 where the surface of the recess-etched GaAs layer is exposed without being deposited. Therefore, as shown in the figure, the recessed etching portion 18 can be filled.
【００２０】図６は、リフトオフによりソース及びドレ
イン電極を形成した段階を示す。まずホトレジスト膜２
３を図５に示す酸化膜又は窒化膜１７上の全面に塗布す
る。そして、ソース・ドレイン電極パターンのマスク合
わせを行い、露光して現像し、ソース・ドレイン電極が
形成される部分にレジスト膜の開口２３Ｈを設ける。そ
して開口２３Ｈからレジスト膜をマスクとして塩酸系の
エッチャントを用いてＧａＩｎＰ層２０を選択的にエッ
チングする。FIG. 6 shows a stage in which the source and drain electrodes are formed by lift-off. First, photoresist film 2
3 is applied to the entire surface of the oxide film or nitride film 17 shown in FIG. Then, masking of the source / drain electrode pattern is performed, exposure and development are performed, and openings 23H of the resist film are provided in portions where the source / drain electrodes are formed. Then, the GaInP layer 20 is selectively etched from the opening 23H using a resist film as a mask and using a hydrochloric acid-based etchant.
【００２１】次に、オーミック電極金属であるＡｕＧｅ
／Ｎｉ／Ａｕ膜２４を蒸着により基板全面に被着する。
そしてリフトオフにより、レジスト膜２３上の不要なＡ
ｕＧｅ／Ｎｉ／Ａｕ膜２４をレジスト膜と共に除去する
ことにより、ソース電極１４及びドレイン電極１５が形
成される。ＡｕＧｅ／Ｎｉ／Ａｕ膜からなるソース及び
ドレイン電極１４，１５は、ｎ＋型ＧａＡｓ層１１Ａの
表面が完全に露出した状態で形成される。アロイ（合金
化）することにより、確実なオーミック接触をチャネル
領域であるＧａＡｓ層１１，１１Ａに対して取ることが
できる。Next, AuGe which is an ohmic electrode metal
The / Ni / Au film 24 is deposited on the entire surface of the substrate by vapor deposition.
Then, by lift-off, unnecessary A on the resist film 23
The source electrode 14 and the drain electrode 15 are formed by removing the uGe / Ni / Au film 24 together with the resist film. The source and drain electrodes 14 and 15 made of AuGe / Ni / Au film are formed with the surface of the n + type GaAs layer 11A completely exposed. By alloying (alloying), a reliable ohmic contact can be made to the GaAs layers 11 and 11A which are the channel regions.
【００２２】次に、ゲート電極の形成について図７及び
図８を参照して説明する。まず、基板全面にホトレジス
ト膜２５を塗布する。そして、マスク合わせ、露光、現
像でゲート電極が形成される部分に、ホトレジスト膜の
開口２５Ｈを形成する。この開口は、寸法精度を必要と
しないのでラフなものでよい。次に、この開口２５Ｈ及
び酸化膜又は窒化膜の開口１７Ｈを介して埋込パッシベ
ーション層であるＧａＩｎＰ層２１をＲＩＥなどで異方
性エッチングする。ＧａＩｎＰ層２１のエッチングが完
了すると、ｎ型ＧａＡｓ層１１の表面が露出する。この
段階を図７に示す。Next, formation of the gate electrode will be described with reference to FIGS. 7 and 8. First, the photoresist film 25 is applied to the entire surface of the substrate. Then, the opening 25H of the photoresist film is formed in the portion where the gate electrode is formed by mask alignment, exposure, and development. This opening may be rough because it does not require dimensional accuracy. Next, the GaInP layer 21 which is the buried passivation layer is anisotropically etched by RIE or the like through the opening 25H and the opening 17H of the oxide film or the nitride film. When the etching of the GaInP layer 21 is completed, the surface of the n-type GaAs layer 11 is exposed. This stage is shown in FIG.
【００２３】そして、ＧａＡｓ層１１に対してショット
キ接合を形成する金属である、例えばＴｉ／Ａｌ膜２６
を蒸着により被着する。この段階を示したものが図８で
ある。次に、リフトオフによりレジスト膜２５を除去す
ると共に、レジスト膜２５上の余分なＴｉ／Ａｌ膜２６
を除去して、ゲート電極１３を形成することにより、図
１に示す埋込パッシベーション層としてＧａＩｎＰ層２
１をリセスエッチ部１８に隙間なく備えたＧａＡｓデバ
イスが完成する。Then, for example, a Ti / Al film 26 which is a metal forming a Schottky junction with the GaAs layer 11.
Are deposited by vapor deposition. FIG. 8 shows this stage. Next, the resist film 25 is removed by lift-off, and an extra Ti / Al film 26 on the resist film 25 is removed.
Are removed to form the gate electrode 13 to form the GaInP layer 2 as the buried passivation layer shown in FIG.
Thus, a GaAs device having the recessed etched portion 1 without gaps is completed.
【００２４】尚、上述した実施の形態の説明では、パッ
シベーション層として、アンドープＧａＩｎＰ層を用い
た例について説明したが、アンドープＧａＡｓ層を用い
てもよいことは、勿論のことである。パッシベーション
層としてアンドープＧａＡｓ層を用いることは、広く行
われており、表面準位の形成を減少させ、自然空乏層を
薄くでき、発振素子としての位相雑音の低減に、ＧａＩ
ｎＰ層と同様に有効である。In the above description of the embodiment, an example of using an undoped GaInP layer as the passivation layer has been described, but it goes without saying that an undoped GaAs layer may be used. The use of an undoped GaAs layer as a passivation layer is widely used, and it is possible to reduce the formation of surface states, thin the natural depletion layer, and reduce the phase noise as an oscillating element.
It is as effective as the nP layer.
【００２５】[0025]
【発明の効果】以上に詳細に説明したように、本発明
は、ゲート電極とソース電極及びドレイン電極間に化合
物半導体層の表面を保護するパッシベーション層を隙間
なく形成すると共に、ゲート電極をリセスエッチ部に自
己整合で配置することができる。これにより、化合物半
導体層の表面準位の生成を更に低減することができると
共に、ステッパー等の高精度のマスク合わせ装置を用い
ることなく、ゲート電極をリセスエッチ部に位置合せす
ることができる。従って、発振素子としては位相雑音を
更に低減したデバイスを、又、高出力素子としてはチャ
ネルの狭搾現象を減少でき、出力特性が更に改善された
デバイスを良好な歩留で量産することができる。As described above in detail, according to the present invention, a passivation layer for protecting the surface of the compound semiconductor layer is formed between the gate electrode and the source electrode and the drain electrode without any gap, and the gate electrode is recess-etched. Can be self-aligned to. Thereby, the generation of the surface level of the compound semiconductor layer can be further reduced, and the gate electrode can be aligned with the recess etching portion without using a highly accurate mask aligning device such as a stepper. Therefore, it is possible to mass-produce a device having a further reduced phase noise as an oscillating element, and a channel narrowing phenomenon as a high-output element, and a device having further improved output characteristics with a good yield. .
【図１】本発明の一実施の形態の化合物半導体装置の断
面図である。FIG. 1 is a sectional view of a compound semiconductor device according to an embodiment of the present invention.
【図２】本発明の一実施の形態の化合物半導体装置の製
造工程の断面図で、使用するＧａＡｓ基板の構成を示
す。FIG. 2 is a sectional view of a manufacturing process of a compound semiconductor device according to an embodiment of the present invention, showing the configuration of a GaAs substrate used.
【図３】本発明の一実施の形態の化合物半導体装置の製
造工程の断面図で、酸化膜又は窒化膜を形成した段階を
示す。FIG. 3 is a cross-sectional view of a manufacturing process of a compound semiconductor device according to an embodiment of the present invention, showing a stage in which an oxide film or a nitride film is formed.
【図４】本発明の一実施の形態の化合物半導体装置の製
造工程の断面図で、リセスエッチ部を形成した段階を示
す。FIG. 4 is a cross-sectional view of a manufacturing process of a compound semiconductor device according to an embodiment of the present invention, showing a stage in which a recess etch portion is formed.
【図５】本発明の一実施の形態の化合物半導体装置の製
造工程の断面図で、埋込パッシベーション膜をエピタキ
シャル成長した段階を示す。FIG. 5 is a cross-sectional view of a manufacturing process of a compound semiconductor device according to an embodiment of the present invention, showing a stage in which a buried passivation film is epitaxially grown.
【図６】本発明の第一実施の形態の化合物半導体装置の
製造工程の断面図で、リフトオフによりソース・ドレイ
ン電極を形成した段階を示す。FIG. 6 is a cross-sectional view of the manufacturing process of the compound semiconductor device according to the first embodiment of the present invention, showing a stage in which source / drain electrodes are formed by lift-off.
【図７】本発明の第一実施の形態の化合物半導体装置の
製造工程の断面図で、埋込パッシベーション膜に開口を
形成した段階を示す。FIG. 7 is a cross-sectional view of the manufacturing process of the compound semiconductor device according to the first embodiment of the present invention, showing a stage in which an opening is formed in a buried passivation film.
【図８】本発明の第一実施の形態の化合物半導体装置の
製造工程の断面図で、リフトオフによりゲート電極を形
成した段階を示す。FIG. 8 is a sectional view of a manufacturing process of the compound semiconductor device according to the first embodiment of the present invention, showing a stage in which a gate electrode is formed by lift-off.
【図９】従来の化合物半導体装置の断面図である。FIG. 9 is a cross-sectional view of a conventional compound semiconductor device.
Claims (1)
を配設し、該酸化膜又は窒化膜に開口を設け、該開口よ
り化合物半導体基板をリセスエッチし、該リセスエッチ
した部分にアンドープ化合物半導体層を選択的にエピ成
長し、前記開口より該アンドープ半導体層をエッチング
して前記半導体基板表面を露出させ、更に前記開口より
前記化合物半導体とショットキ接合を形成するゲート電
極を設けたことを特徴とする化合物半導体装置の製造方
法。1. An oxide film or a nitride film is provided on a compound semiconductor substrate, an opening is provided in the oxide film or the nitride film, the compound semiconductor substrate is recess-etched through the opening, and the unetched compound semiconductor layer is formed in the recess-etched portion. Is selectively epitaxially grown, the undoped semiconductor layer is etched through the opening to expose the surface of the semiconductor substrate, and a gate electrode is formed through the opening to form a Schottky junction with the compound semiconductor. Method for manufacturing compound semiconductor device.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7343402A JPH09186178A (en) | 1995-12-28 | 1995-12-28 | Manufacture of compound semiconductor device |
| US08/773,347 US5837570A (en) | 1995-12-28 | 1996-12-26 | Heterostructure semiconductor device and method of fabricating same |
| KR1019960073954A KR100220870B1 (en) | 1995-12-28 | 1996-12-27 | Manufacturing method of the compound semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7343402A JPH09186178A (en) | 1995-12-28 | 1995-12-28 | Manufacture of compound semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH09186178A true JPH09186178A (en) | 1997-07-15 |
Family
ID=18361240
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7343402A Pending JPH09186178A (en) | 1995-12-28 | 1995-12-28 | Manufacture of compound semiconductor device |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JPH09186178A (en) |
| KR (1) | KR100220870B1 (en) |
-
1995
- 1995-12-28 JP JP7343402A patent/JPH09186178A/en active Pending
-
1996
- 1996-12-27 KR KR1019960073954A patent/KR100220870B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR970054443A (en) | 1997-07-31 |
| KR100220870B1 (en) | 1999-09-15 |
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