JPH09186169A - Manufacturing method of bipolar transistor - Google Patents

Abstract

(57) Abstract: Dry etching is required at the time of forming a sidewall, and a semiconductor surface to be an emitter region is exposed to dry etching, and damage, defects, and the like due to dry etching are caused in a semiconductor substrate. May be introduced to. A thermal oxide film and a first oxide film are formed on the surface of a base region. Next, an opening for introducing impurities for forming an emitter region is formed in the oxide films 5 and 6, and a polysilicon film is formed so as to cover at least the opening. Next, an oxide film is formed at least on the polysilicon film and etched back to form the sidewall 10 at the step portion in the peripheral region of the opening. Next, impurities are ion-implanted into the polysilicon film to diffuse the impurities into the base region 7 to simultaneously form the high-emitter region 12 and the low-concentration emitter region 13.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a bipolar transistor.

[0002]

2. Description of the Related Art A normal npn bipolar transistor has a withstand voltage between the emitter and the base of about 5 to 10 V, and since a high concentration of the emitter diffusion and the base diffusion are close to each other, a reverse bias is applied between the emitter and the base. If
There has been a problem that a zener leak current is generated and the current amplification factor (h _FE ) is deteriorated by hot carriers. As a method of improving this problem, a method of forming a low concentration emitter region around the emitter diffusion has been proposed.

Generally, a film containing impurities is formed on the surface of a base region layer serving as an emitter region, and the impurities are thermally diffused from the film to perform the emitter diffusion. For example, as shown in FIG. Japanese Patent Laid-Open No. 4-305934
In the publication, after forming the base region 28, the insulating film 30
After forming the, a window is opened for diffusion of the emitter (see FIG. 6).
(A)) Then, an insulator containing a high concentration of n-type impurities is formed, and the entire surface is etched to form a sidewall 33 on the side surface of the window opening (FIG. 6B).

Next, an n ⁺ emitter electrode 34 is formed so as to cover the window opening, impurities are diffused from the emitter electrode 34 and the sidewall portion 33, respectively, and a low concentration emitter region 36 and a high concentration emitter region 35 are formed. Are formed (FIG. 6C). The impurities may be introduced into the emitter electrode by either vapor phase diffusion using a diffusion furnace or ion implantation using an ion implantation device.

FIG. 6 is a diagram showing a manufacturing process of a conventional bipolar transistor. Further, in FIG. 6, 21 is p
Silicon substrate, 22 is an n ⁺ buried layer, 23 is an n ⁻ epitaxial layer, 24 is an element isolation insulating film, 25 is an n ⁺ diffusion layer, 26 is a p ⁺ external base region, 28 is a p ⁻ intrinsic base region, 29 Is a p ⁺ polysilicon film, 30 is an insulating layer, 33
Is a sidewall, and 34 is an emitter electrode.

In the above method, since the emitter region having a higher concentration than the emitter electrode portion is formed and the emitter region having a lower concentration than the sidewall portion is formed around the high concentration emitter region, the emitter-base breakdown voltage is increased. It is possible to keep it high.

[0007]

However, in the above-described method of manufacturing a bipolar transistor, dry etching is required when forming the sidewalls, and the semiconductor surface to be the emitter region is exposed to dry etching. . Therefore, there is a possibility that damage, defects, and contamination due to dry etching may be introduced into the semiconductor substrate, and these may cause a transistor characteristic defect such as a collector-emitter breakdown voltage defect and h _FE deterioration.

An object of the present invention is to provide a bipolar transistor in which a low-concentration emitter region is formed around a high-concentration emitter region without dry etching the surface of an epitaxial layer which will be the emitter region.

[0009]

According to a first aspect of the present invention, there is provided a method of manufacturing a bipolar transistor, comprising the steps of forming a buried diffusion layer and an epitaxial layer on a semiconductor substrate, and forming a base region in the epitaxial layer. Forming a first insulating film having a predetermined thickness on the surface of the base region;
A step of forming an opening for introducing an impurity for forming an emitter region in the first insulating film, and forming a conductive film for diffusing and supplying the impurity so as to cover at least the opening;
Forming an insulating film on at least the conductive film and etching back to form a sidewall in the step portion of the opening peripheral region; a step of ion-implanting impurities into the conductive film; And diffusing impurities from the film into the base region to simultaneously form a high-concentration emitter region and a low-concentration emitter region.

According to a second aspect of the present invention, there is provided a method of manufacturing a bipolar transistor in which a buried diffusion layer and an epitaxial layer are formed on a semiconductor substrate, a base region is formed in the epitaxial layer, and a surface of the base region. A step of forming a first insulating film having a predetermined thickness, an opening for introducing an impurity for forming an emitter region is formed in the first insulating film, and a conductive film for diffusing the impurity is formed over the entire surface. After that, a step of ion-implanting impurities into the conductive film formed on the entire surface with energy such that the impurity concentration peak comes to approximately the interface between the base region and the conductive film,
A step of diffusing impurities from the conductive film into the base region to simultaneously form a high concentration emitter region and a low concentration emitter region.

Further, a method of manufacturing a bipolar transistor according to the present invention is the step of forming a buried diffusion layer and an epitaxial layer on a semiconductor substrate, forming a base region in the epitaxial layer, and the surface of the base region. A step of forming a first insulating film having a predetermined thickness, an opening for introducing an impurity for forming an emitter region is formed in the first insulating film, and a conductive film for diffusing the impurity is formed over the entire surface. After that, a second insulating film is formed on at least the conductive film,
By etching back, a step of forming a sidewall in the step portion of the peripheral region of the opening, and an impurity in the conductive film so that an impurity concentration peak is at a substantially interface between the base region and the conductive film. It is characterized by including a step of implanting ions by energy and a step of diffusing impurities from the conductive film into the base region to simultaneously form a high concentration emitter region and a low concentration emitter region.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, the present invention will be described in detail based on the embodiments.

FIG. 1 is a first (first half) manufacturing process diagram of a bipolar transistor of a first embodiment of the present invention, and FIG. 2 is a second (second half) of a bipolar transistor of the first embodiment of the present invention. FIG. 3 is a manufacturing process diagram, FIG. 3 is a partially enlarged view of the bipolar transistor formed in the process shown in FIGS. 1 and 2, and FIG. 4A shows an emitter profile in the AA cross section in FIG. FIG. 4B is a diagram showing an emitter profile in the BB cross section of FIG. 3, and FIG. 5 is a partial manufacturing process diagram of the bipolar transistor of the second embodiment of the present invention.

In FIGS. 1 to 3 and 5, 1 is p
Type silicon substrate, 2 n ⁺ buried layer, 3 epitaxial layer, 4 p type isolation region, 5 thermal oxide film, 6 CVD
First oxide film formed by the method, 7 is a base region, 8 is a polysilicon emitter electrode, 9 is a polysilicon collector electrode, 10 is a sidewall made of an insulating film, and 11 is C.
A second oxide film formed by the VD method, 12 is a high concentration emitter region, 13 is a low concentration emitter region, 14 is a high concentration collector extraction region, 15 is a low concentration collector extraction region, 16a is a collector metal electrode, and 16b is an emitter. Metal electrodes, 16c are base metal electrodes, and 17 is a polysilicon film.

The manufacturing process of the bipolar transistor according to the embodiment of the present invention will be described below with reference to FIGS. First, the n ⁺ buried layer 2, the epitaxial layer 3, and the p-type isolation region 4 are formed on the p-type silicon substrate 1 by using a well-known technique (FIG. 1A). After that, a thermal oxide film 5 having a thickness of about 50 nm is formed on the epitaxial layer 3 by a thermal oxidation method, and subsequently, a well-known photolithography technique and an ion implantation technique are used for the base region.
In this embodiment, the acceleration energy of boron is set to 40 Ke.
V and a dose amount of 5 × 10 ¹³ ions / cm ² are introduced into the epitaxial layer 3 with p-type impurities. Then, the first oxide film 6 having a thickness of about 250 nm is formed on the entire surface by the CVD method (FIG. 1B).

Next, using a well-known photoetching technique, the thermal oxide film 5 and the first oxide film 6 in the regions which will be the collector take-out portion and the emitter region are selectively removed, and a polysilicon film of about 200 nm is formed on the entire surface. After the deposition, the polysilicon film is patterned to form a polysilicon emitter electrode 8 and a polysilicon collector electrode 9 (FIG. 1).
(C)). Here, although the polysilicon film is used as the conductive layer serving as the impurity diffusion source, amorphous silicon is also applicable, and the present invention is applicable to the conductive layer serving as the impurity diffusion source such as polysilicon. It is not limited to.

After the above steps, the thickness of the polysilicon film near the side walls of the openings of the first oxide film 5 and the thermal oxide film 4 is the thickness of the oxide films 5 and 6 (250 nm + 50 nm) + polysilicon. The film thickness (200 nm) is about 500 nm, and the thickness of the polysilicon film at the bottom of the opening is 20 nm.
It becomes 0 nm.

Next, an oxide film of about 4 is formed on the entire surface by the CVD method.
The sidewalls 10 are formed on the step portions of the polysilicon emitter electrode 8 and the polysilicon collector electrode 9 by depositing 50 nm and then by anisotropic etching on the entire surface (FIG. 2A).

Next, for example, arsenic (As) has an acceleration energy of 50 KeV and a dose of 7 × 10 ¹⁵ ions / cm.
Ion implantation under the conditions of ² and polysilicon emitter electrode 8
Then, impurities are introduced into the polysilicon collector electrode 9. At this time, as shown in FIGS. 4 (a) and 4 (b),
The thin region (A-A cross section of FIG. 3) and the thick region (BB cross-section of FIG. 3) of the polysilicon film are doped with the same dose amount, but the thickness of the polysilicon film is different. Therefore, the impurity concentration is different. The vertical axis of FIG. 4 represents the impurity concentration, and the unit is arbitrary.

After that, a second oxide film 11 is deposited on the entire surface by the CVD method to a thickness of about 400 nm, and then in a nitrogen atmosphere,
A heat treatment is performed at 920 ° C. for 100 minutes to activate the impurities and diffuse the impurities from the polysilicon emitter electrode 8 and the polysilicon collector electrode 9 to form the emitter region 12.
13 and collector extraction regions 14 and 15 are formed.
At this time, the low-concentration emitter region 13 and the low-concentration collector lead-out region 15 are formed by the impurities injected into the step portion of the polysilicon emitter electrode 8 and the polysilicon collector electrode 9, and the polysilicon emitter electrode 8 and the polysilicon collector electrode 9 are formed. The high-concentration emitter region 13 and the collector extraction region 15 are formed by the impurities injected into the flat portion of 9.

Next, the collector metal electrode 16a, the emitter metal electrode 16b and the base metal electrode 16c are formed by contact hole formation and metallization by a well-known technique to complete the npn bipolar transistor (FIG. 2 (c)).

In the above process, the die wall forming process is performed. However, instead of the side wall forming process, the film thickness of the polysilicon film to be the polysilicon emitter electrode 8 and the polysilicon collector electrode 9 is increased. ,
The low concentration impurity region in the polysilicon may be enlarged.

However, since the diffusion of impurities in polysilicon is very fast, the polysilicon emitter electrode 8
Since the impurity concentration distribution in the inside tends to be uniform, ion implantation is performed using this sidewall as a mask, and the boundary region between the thick and thin parts of the polysilicon film has a region not doped with impurities. By forming the impurity concentration distribution, it is possible to prevent the impurity concentration distribution from becoming uniform, and the low concentration emitter region 1 is formed.
3 and the high-concentration emitter region 12 can have a larger impurity concentration difference, so that it is preferable to use the sidewall formation step.

Next, the manufacturing process of the bipolar transistor according to the second embodiment of the present invention will be described with reference to FIG. First, the n ⁺ buried layer 2, the epitaxial layer 3 and the p-type isolation region 4 are formed on the p-type silicon substrate 1 using a well-known technique. After that, a thermal oxide film 5 having a thickness of about 50 nm is formed on the epitaxial layer 3 by a thermal oxidation method, and subsequently, a well-known photolithography technique and an ion implantation technique are used for a portion of the base region in the present embodiment. Then, the acceleration energy of boron is set to 120 KeV, the dose amount is set to 5 × 10 ¹³ ions / cm ² , and p-type impurities are introduced into the epitaxial layer 3. After that, by the CVD method,
A first oxide film 6 of about 250 nm is formed on the entire surface. The above steps are the same as those in the first embodiment (FIG. 1A, FIG.
It is the same as (b)).

Next, using a well-known photo-etching technique, the thermal oxide film 5 and the first oxide film 6 in the region serving as the collector extraction portion and the emitter region are selectively removed, and the polysilicon film 17 is formed on the entire surface. 200 nm is deposited (FIG. 5)
(A)).

Next, an oxide film of about 4 is formed on the entire surface by the CVD method.
After depositing 50 nm, the sidewalls 10 are formed on the step portion at the peripheral edge of the opening by anisotropic etching on the entire surface.

Next, the polysilicon film 17 and the base region 7 are formed.
Ion implantation of phosphorus (P) under conditions of an acceleration energy of about 80 KeV and a dose of 7 × 10 ¹⁵ ions / cm ² so that a peak of the impurity concentration comes to the approximate interface with
Impurities are introduced into the polysilicon film 17 (FIG. 5).
(B)).

Then, the polysilicon film 17 is patterned to form a polysilicon emitter electrode 8 and a polysilicon collector electrode 9. Then, the first aspect of the present invention described above.
In the same manner as in the above embodiment, the second oxide film 11 is deposited on the entire surface by the CVD method to a thickness of about 400 nm, and then heat treatment is performed at 920 ° C. for 100 minutes in a nitrogen atmosphere to activate the impurities and the polysilicon emitter electrode. 8 and the emitter region 1 by diffusion of impurities from the polysilicon collector electrode 9.
2, 13 and collector extraction regions 14, 15 are formed (FIG. 5C).

Next, a collector metal electrode 16a, an emitter metal electrode 16b and a base metal electrode 16c are formed by contact hole formation and metallization by a well-known technique to complete an npn bipolar transistor (FIG. 5 (d)).

Although the sidewall forming step is performed in the above steps, the sidewall forming step can be omitted.

[0031]

As described in detail above, claim 1 is as follows.
By using the present invention according to claim 2 and the present invention according to claim 2, it is possible to form a low-concentration emitter region around the high-concentration emitter region by self-alignment, and further, a surface of an epitaxial layer to be an emitter. Since the bipolar transistor can be formed without exposing it to dry etching, it is possible to provide a bipolar transistor having a good yield and capable of suppressing the generation of hot carriers even when a reverse bias is applied to the base-emitter without deterioration of characteristics.

By using the present invention according to claim 3, the low concentration emitter region and the high concentration emitter region can be formed more reliably.

[Brief description of the drawings]

FIG. 1 is a first manufacturing process diagram of a bipolar transistor according to a first embodiment of the present invention.

FIG. 2 is a second manufacturing process drawing of the bipolar transistor according to the first embodiment of the present invention.

FIG. 3 is a partially enlarged sectional view of a bipolar transistor of the present invention.

4A is a diagram showing an emitter profile of a section AA of FIG. 3, and FIG. 4B is a diagram showing an emitter profile of a section BB of FIG.

FIG. 5 is a partial manufacturing process drawing of the bipolar transistor according to the second embodiment of the present invention.

FIG. 6 is a manufacturing process diagram of a conventional bipolar transistor.

[Explanation of symbols]

1 p-type silicon substrate 2 n ⁺ buried layer 3 epitaxial layer 4 p-type isolation region 5 thermal oxide film 6 first oxide film 7 base region 8 polysilicon emitter electrode 9 polysilicon collector electrode 10 sidewall 11 second oxide film 12 high Concentration emitter region 13 Low concentration emitter region 14 High concentration collector extraction region 15 Low concentration collector extraction region 16a Collector metal electrode 16b Emitter metal electrode 16c Base metal electrode 17 Polysilicon film

Claims (3)

[Claims] 1. A step of forming a buried diffusion layer and an epitaxial layer on a semiconductor substrate, forming a base region in the epitaxial layer, and a step of forming a first insulating film having a predetermined thickness on the surface of the base region. A step of forming an opening for introducing an impurity for forming an emitter region in the first insulating film and forming a conductive film for diffusing and supplying the impurity so as to cover at least the opening; Forming a sidewall on the step portion of the opening peripheral region by forming it on the conductive film and etching back; ion-implanting impurities into the conductive film; and removing impurities from the conductive film. And a step of forming a high-concentration emitter region and a low-concentration emitter region at the same time by diffusing into the base region. Law. 2. A step of forming a buried diffusion layer and an epitaxial layer on a semiconductor substrate, forming a base region in the epitaxial layer, and a step of forming a first insulating film having a predetermined thickness on the surface of the base region. After forming an opening for introducing an impurity for forming an emitter region in the first insulating film and forming a conductive film for diffusing the impurity over the entire surface, an impurity is introduced into the conductive film formed over the entire surface. A step of ion-implanting with an energy such that an impurity concentration peak is located substantially at the interface between the base region and the conductive film; and a process of diffusing impurities from the conductive film into the base region to form a high-concentration emitter region and a low-concentration emitter region. And a step of forming the same at the same time. 3. A step of forming a buried diffusion layer and an epitaxial layer on a semiconductor substrate, forming a base region in the epitaxial layer, and a step of forming a first insulating film having a predetermined thickness on the surface of the base region. An opening for introducing an impurity for forming an emitter region is formed in the first insulating film, a conductive film for diffusing the impurity is formed over the entire surface, and then a second insulating film is formed at least on the conductive film. , A step of forming a sidewall in the step portion of the peripheral region of the opening by etching back, and impurities in the conductive film so that the impurity concentration peak is substantially at the interface between the base region and the conductive film. Ion implantation with various energies and a step of diffusing impurities from the conductive film into the base region to simultaneously form a high-concentration emitter region and a low-concentration emitter region. Characterized by method of the bipolar transistor.