JPH09181970A - Image signal processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To execute a compression/expansion processing through the use of only a sampling frequency and to execute the conversion processing of the sampling frequency through the use of the sampling frequency and the sampling frequency after the conversion processing by executing the compression or expansion processing on a digitized picture signal in a horizontal direction. SOLUTION: The digital image signal supplied to an input terminal 26 is supplied to an image signal processing circuit 27. Thus, the prescribed processing of the compression/expansion processing and the conversion processing of the sampling frequency is executed and the signal is outputted from an output terminal 28. The image signal processing circuit 27 is controlled by a controller 29. The controller 29 transmits the expansion rate of the picture and the values of a starting point and a final point in the horizontal direction in an area where the image is compression/expansion-processed to a former remote controller 37, transmits the value of an interpolation coefficient to a coefficient register 41 and transmits the values of the starting point and the final point, which show the display position of the image that is compressed/expanded in the horizontal direction, to a memory controller 47.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement of an image signal processing apparatus for subjecting a plurality of digital image signals to horizontal / vertical compression / expansion processing or sampling frequency conversion processing.

[0002]

2. Description of the Related Art As is well known, at present, an image signal processing apparatus has been developed which synthesizes a plurality of digital image signals and displays the images so as to be superimposed on one screen. FIG. 22 shows an example in which three images a, b and c are combined and displayed on one screen. In this example, it is necessary to compress and decompress the three images a, b, and c in the horizontal direction and the vertical direction, respectively, before combining them.

Here, the image is multiplied by E / C in the horizontal direction (E,
Consider that C is a positive integer). In this case, a method is known in which an image is expanded in the horizontal direction by E times and then compressed by 1 / C times. FIG. 23 shows an example in which an image is expanded 2/3 times in the horizontal direction. FIG.
(A) shows the original image, (b) shows the image expanded twice in the horizontal direction, and (c) shows the image further compressed by 1/3 in the horizontal direction. The 2/3 time expansion image is shown.

FIG. 24A shows horizontal addresses when reproducing the original image shown in FIG.
FIG. 24B shows a horizontal address when the 2 × expanded image shown in FIG. 23B is reproduced, and FIG.
The horizontal address in the case of reproducing the 2/3 times expanded image shown in (c) is shown. That is, the double-expanded image is obtained by sampling the pixels indicated by ◯ in the original image for each address and interpolating between the pixels by the pixels indicated by X in the figure. Further, the 2/3 time expanded image is obtained by sampling the pixels of the 2 times expanded image for every 3 addresses.

Next, the image signal sampled at the sampling frequency f1 is sampled at the sampling frequency f2 [= (N / M) f1.
] To consider. FIG. 25 (a) shows an image at the sampling frequency f1, and FIG. 25 (b) shows an image at the sampling frequency f2. In this case, a method is known in which an image signal with a sampling frequency f1 is converted into an image signal with a sampling frequency Nf1 and then the sampling frequency is reduced to 1 / M. It is synonymous with multiplying N / M times.

FIG. 26 shows the sampling frequency of the image signal as N /
The sampling frequency conversion circuit for converting into M times is shown. That is, the image signal of the sampling frequency f1 supplied to the input terminal 11 is the frequency f1 supplied to the input terminal 12.
After being latched by the register 13 which is operated based on the sampling clock of 1, the data is output to the shift register 14. The shift register 14 sequentially latches the input image signal on the basis of the clock obtained by converting the sampling clock supplied to the input terminal 12 into the frequency of N times in the frequency multiplication circuit 15.

The outputs of the respective stages of the shift register 14 are multiplied by the coefficient 1 by the weighted addition circuit 16 and then added. The output of the weighted addition circuit 16 is supplied to the register 19 after being multiplied by the coefficient 1 / N supplied to the input terminal 18 by the multiplication circuit 17.
This register 19 is an input signal based on a clock obtained by converting the output clock of the frequency multiplication circuit 15 into a frequency of 1 / M times by the frequency multiplication circuit 20, that is, a clock having a frequency of (N / M) f1 = f2. Are sequentially latched. Therefore, from the register 19, the sampling frequency is f
The image signal converted from 1 to f2 is output and taken out from the output terminal 21.

On the other hand, in FIG. 27, the image signal is horizontally shifted by E.
A decompression processing circuit for decompressing / C times is shown with the same symbols as in FIG. That is, FIG.
The difference from the sampling frequency conversion circuit shown in 6 is after the image signal is converted to the sampling frequency f2. The image signal converted to the sampling frequency f2 is written into the line memories 23 and 24 alternately line by line by the changeover switch 22. The write addresses of the line memories 23 and 24 are updated based on the clock frequency f2 output from the frequency multiplication circuit 20.

The image signals written in the line memories 23 and 24 are held for one line period, and then,
The data is alternately read out line by line by the changeover switch 25 and taken out from the output terminal 21. In this case, the read addresses given to the line memories 23 and 24 are updated based on the sampling clock of the frequency f1 so that the sampling frequency f expanded by E / C times in the horizontal direction.
One image signal can be generated.

However, in the conventional image signal processing means for subjecting the image signal of the sampling frequency f1 to the compression / expansion processing and the conversion of the sampling frequency as described above, N times the sampling clock of the frequency f1 is used. Alternatively, since a circuit portion that operates at a clock frequency of E times is required, a circuit that can operate at high speed becomes necessary as the value of N or E increases, which causes a problem of difficulty in realization. .

[0011]

As described above, the conventional image signal processing means operates at a high clock frequency in performing compression / expansion processing, sampling frequency conversion processing, etc. on a digital image signal. That is, a circuit capable of high-speed operation is required, which is difficult to realize.

Therefore, the present invention has been made in consideration of the above circumstances, and it is possible to perform compression / expansion processing on a digital image signal using only the sampling frequency of the digital image signal. It is an object of the present invention to provide an extremely good image signal processing device that can perform sampling frequency conversion processing using the sampling frequency and the sampling frequency after conversion processing.

[0013]

The image signal processing apparatus according to the present invention is intended for subjecting a digitized image signal to horizontal compression or expansion processing.

Information indicating the horizontal compression or expansion ratio of the image signal, information indicating the position of the horizontal region on which the image signal is compressed or expanded, and the horizontal direction of the compressed or expanded image signal. Setting information for indicating the display position of the area and a plurality of coefficients for performing the filtering calculation processing on the image signal, and a write address is generated at the cycle of the sampling clock of the image signal to compress the image signal. Alternatively, by using the information indicating the expansion rate and the information indicating the position of the area in the horizontal direction where the image signal is compressed or expanded, the read address is generated by performing the arithmetic processing in the cycle unit of the sampling clock. A first control means for selecting a necessary coefficient from a plurality of coefficients for performing a filtering calculation process on an image signal, and the first control means. An image signal is written on a line-by-line basis based on the created write address, and a first line memory is read based on the read address generated by the first control means, and is read from the first line memory. Means for inputting the image signal to the storage means for updating the data based on the information generated by the first control means, and the first control means for the image signal output from the storage means. Based on the calculation means for performing the filtering calculation processing based on the coefficient selected in step 1, the information indicating the display position of the horizontal region of the compressed or expanded image signal, and the information generated by the first control means. Second control means for generating a write address and generating a read address at a cycle of an image signal sampling clock,
Based on the write address generated by the second control means, the image signal is written line by line only for the period of the sampling clock in which the write address is updated by 1, and the read address generated by the second control means. And a second line memory which is read out based on the above.

The image signal processing apparatus according to the present invention is intended for subjecting a digitized image signal of progressive scanning to vertical compression or expansion processing.

Then, information indicating the vertical compression or expansion ratio of the image signal, information indicating the position of the vertical region in which the image signal is compressed or expanded, and the vertical direction of the compressed or expanded image signal. Setting information for indicating the display position of the area and a plurality of coefficients for performing the filtering calculation processing on the image signal, horizontal writing address is generated at the cycle of the sampling clock of the image signal, The vertical write address is generated in the line cycle, the horizontal read address is generated in the cycle of the image signal sampling clock, and information indicating the compression or expansion rate of the image signal,
By using the information indicating the position of the vertical region to which the image signal is compressed or expanded, the vertical read address is generated by performing the arithmetic process in the line cycle, and the filtering arithmetic process is performed on the image signal. First control means for selecting a necessary coefficient from a plurality of coefficients and an image signal is written in frame units based on the horizontal and vertical write addresses generated by the first control means, and the first control A first frame memory read based on the horizontal and vertical read addresses generated by the means, and an image signal read from the first frame memory based on the information generated by the first control means. Means for inputting the data to the storage means for updating the data and the image signal output from the storage means, and selected by the first control means. Calculating means for performing a filtering calculation process based on the coefficient, information for indicating a display position of a vertical area of the compressed or expanded image signal, which generates a horizontal write address in the cycle of the sampling clock of the image signal, Using the information generated by the first control means, a vertical write address is generated by performing an arithmetic process in a line cycle, and a horizontal read address is generated in a cycle of a sampling clock of the image signal. The second control means for generating the vertical read address in the line cycle, and the image signal only in the line cycle in which the vertical write address is updated by 1 based on the horizontal and vertical write addresses generated by the second control means. A second one written in a frame unit and read based on the horizontal and vertical read addresses generated by the second control means. It is obtained so as to include a frame memory.

[0017]

Embodiments of the present invention will be described below in detail with reference to the drawings. First, FIG. 1 shows the overall configuration of an image signal processing apparatus according to a first embodiment of the present invention. That is, the digital image signal supplied to the input terminal 26 is supplied to the image signal processing circuit 27 to be subjected to predetermined signal processing such as compression / expansion processing and sampling frequency conversion processing, and the output terminal. Two
8 is output. The operation of the image signal processing circuit 27 is controlled by the controller 29.

The controller 29 controls the image signal processing circuit 27 by receiving and decoding a command output from a CPU (central processing unit) 31 connected via a system bus 30. There is. The CPU 31 receives a command stored in the memory 32 via the system bus 30,
The command output to the controller 29 is generated.

Here, in the image signal processing circuit 27, the image signal supplied to the input terminal 26 is alternately changed line by line by the changeover switch 33.
After being written in the line memory 35, the lines are alternately read from the line memories 34 and 35 line by line by the changeover switch 36. The writing and reading operations for the line memories 34 and 35 and the switching operations of the changeover switches 33 and 36 are controlled by the pre-memory controller 37 which receives an instruction from the controller 29.

The image signals read from the line memories 34 and 35 and selected by the changeover switch 36 are sequentially latched in each stage of the shift register 38.
The image signals output from the respective stages of the shift register 38 are supplied to the coefficient register 4 by the multiplication circuits 39 and 40, respectively.
The interpolation coefficients a and b stored in 1 are multiplied and then added by the adder circuit 42.

The image signals added by the adder circuit 42 are alternately written into the line memories 44 and 45 for each line by the changeover switch 43, and then the changeover switch 4 is used.
6 line memory 44, 45 alternately for each line
Read out from the output terminal 28 and led to the output terminal 28. The write and read operations for the line memories 44 and 45 and the switching operation of the changeover switches 43 and 46 are controlled by the post-memory controller 47 which receives an instruction from the controller 29.

Here, the above-mentioned front memory controller 3
7, the shift register 38, the coefficient register 41, the adder circuit 42, and the rear memory controller 47 are driven based on the clock of the frequency f1 supplied to the input terminals 37a, 38a, 41a, 42a, and 47a, respectively. Also,
Front memory controller 37 and rear memory controller 4
A signal of horizontal synchronizing frequency fh is supplied to 7 via input terminals 37b and 47b, respectively.

When the image signal supplied to the input terminal 26 is subjected to horizontal compression / expansion processing, the CPU 31
The image expansion ratio, the horizontal start and end values of the area to which the image is compressed and expanded, and the start and end values that indicate the horizontal display position of the compressed and expanded image, A command including the value of the interpolation coefficient is sent to the controller 29. Then, the controller 29 classifies the input commands, sends the expansion rate of the image, and the values of the horizontal start point and end point of the area to be subjected to the image compression / expansion processing to the previous memory controller 37 for interpolation. The coefficient value is sent to the coefficient register 41, and the start point and end point values indicating the horizontal display position of the compressed / decompressed image are sent to the rear memory controller 47.

Here, an operation example and a configuration example of the previous memory controller 37 will be described with reference to FIGS. That is, when performing compression / expansion processing on a certain area in the original image in the horizontal direction, the expansion rate is E / C, the address of the start point of the area is Ast, the address of the compressed / expanded image is x, and If the address of the image is y, the address y of the original image corresponding to the address of the compressed / decompressed image as x is given by y = (C / E) x + Ast (1).

For example, if the horizontal address of the original image is 1
For the area from 00 to 300, the original image is 5/3
Consider the case of doubling. FIG. 2 shows the address of the original image corresponding to the address of the compressed / decompressed image under this condition. Here, for example, when the address value x of the compressed / decompressed image is 2, the address value of the original image is 101 and the remainder is 1. At this time, since there is no original image signal corresponding to the address value 101 remainder 1, an image signal corresponding to the address value 101 remainder 1 is generated based on the original image signal of the address in the vicinity thereof.

When the image signal corresponding to the remainder 1 of the address value 101 is linearly interpolated, the original image signal of the address value 101 is 4/5 and the original image signal of the address value 102 is 1/5. It is obtained by multiplying each and adding the multiplication results. As is clear from this, in order to obtain a compressed / decompressed image, it is necessary to solve the equation (1) and calculate the integer part and the remainder part of the solution.

By the way, in order to solve the above equation (1),
It is necessary to perform multiplication or division, and as the value of C or E increases, the scale of the circuit for executing multiplication or division increases significantly. Therefore, in the first embodiment described here, it is considered that multiplication or division is performed by addition or subtraction.

That is, FIG. 3 shows a flowchart for solving the above equation (1) when E ≧ C (expansion), and FIG. 4 shows an operation when E = 5, C = 3, Ast = 100. An example is explained. In the figure, x indicates the address of the compressed / decompressed image, y indicates the address of the original image corresponding to the address of the compressed / decompressed image, E / C indicates the expansion rate, p indicates the remainder, Ast and Aend indicates the address of the original image corresponding to the start point and end point of the area to be compressed / decompressed.

As shown in FIGS. 3 and 4, when the address of the compressed / decompressed image is incremented, compression / decompression is performed.
The address of the original image corresponding to the address of the decompressed image may be incremented or held. When incremented, Flag = 1, and when held, Flag = 0.

Next, FIG. 5 shows a flowchart for solving the above equation (1) when E <C (compression), and FIG.
Describes an operation example when E = 3, C = 5, and Ast = 100. As shown in FIGS. 5 and 6, when the address of the compressed / decompressed image is incremented,
The address of the original image corresponding to the address of the decompressed image is always incremented, but if it is incremented by one, the value may or may not correspond to the solution of the equation (1). So, if it corresponds to a solution,
Skip = 0, and Skip = 1 when it does not correspond to a solution.

FIG. 7 shows the configuration of the pre-memory controller 48 for realizing the arithmetic processing of the flowchart shown in FIG. 3 with one kind of clock. That is, the input terminal 4
The value "0" supplied to 81 is added to the value "C" supplied to the input terminal 484 by the adder circuit 483 after passing through the switch 482.

The output of the adder circuit 484 is the MSB (most significant bit) of the output of the subtractor circuit 485 as it is and the value obtained by subtracting the value "E" supplied to the input terminal 486 by the subtractor circuit 485. It is selected by the multiplexer 487 and controlled by the register 488. The output of this register 488 is the addition circuit 4
It is fed back to the output terminal 8 3
(Remainder) It is taken out as a signal.

Further, the value indicating the horizontal starting point of the area to be subjected to the expansion processing supplied to the input terminal 4810 is set to the switch 4
After passing through 811, the value as it is and the value obtained by adding the value "1" supplied to the input terminal 4813 by the adding circuit 4812 are selected by the multiplexer 4814 controlled by the MSB of the output of the subtracting circuit 485. , Register 4815
Latched. The output of the register 4815 is fed back to the adder circuit 4812 and the multiplexer 4814 and taken out from the output terminal 4816 as a read address.

Further, the value "0" supplied to the input terminal 4817 and the value "1" supplied to the input terminal 4818 are selected by the multiplexer 4819 controlled by the MSB of the output of the subtraction circuit 485, and are registered. Latched at 4820. Then, the output of this register 4820 is taken out from the output terminal 4821 as a Flag signal. The value "0" supplied to the input terminal 4822 is directly output from the output terminal 4823 as the Skip signal.

The value "0" supplied to the input terminal 4824 is passed through the switch 4825 and then added by the adder circuit 4826.
Then, the value "1" supplied to the input terminal 4827 is added and latched by the register 4828. Then, the output of the register 4828 is fed back to the adder circuit 4826, and is output as a write address from the output terminal 4829.

Next, FIG. 8 shows a configuration of the pre-memory controller 49 for realizing the arithmetic processing of the flow chart shown in FIG. 5 with one kind of clock. That is, the value "0" supplied to the input terminal 491 is added to the value "C" supplied to the input terminal 494 by the adder circuit 493 after passing through the switch 492, and the subtraction circuit 495 is added.
By this, the value "E" supplied to the input terminal 496 is subtracted. The value "E" supplied to the input terminal 496 by the subtraction circuit 497 is subtracted from the output of the addition circuit 493, and the value "E" supplied to the input terminal 496 by the subtraction circuit 498 is output from the output of the subtraction circuit 497. "Is subtracted.

Thereafter, the outputs of the subtraction circuits 495 and 497 are selected by the multiplexer 499 controlled by the MSB of the output of the subtraction circuit 498, and the register 4
It is latched to 910. The output of the register 4910 is fed back to the adder circuit 493 and taken out from the output terminal 4911 as a Phase signal. The value “0” supplied to the input terminal 4912 and the value “1” supplied to the input terminal 4913 are selected by the multiplexer 4914 controlled by the MSB of the output of the subtraction circuit 498 and stored in the register 4915. Latched. Then, the output of the register 4915 is taken out from the output terminal 4916 as a Skip signal.

The value indicating the horizontal starting point of the area to be compressed supplied to the input terminal 4917 is set to the switch 4
After passing through 918, adder circuit 4919 inputs terminal 4920
The value “1” supplied to is added and latched by the register 4921. The output of the register 4921 is fed back to the adder circuit 4919 and output terminal 49
It is fetched from 22 as a read address.

Furthermore, the value "1" supplied to the input terminal 4923 is directly output from the output terminal 4924 as the Flag signal. Further, the value “0” supplied to the input terminal 4925 is passed through the switch 4926 and then added by the adder circuit 4927.
Then, the value "1" supplied to the input terminal 4928 is added and latched by the register 4929. The output of the register 4929 is fed back to the adder circuit 4927 and taken out from the output terminal 4930 as a write address.

Here, the front memory controller 37 shown in FIG. 1 determines whether the image is expanded or compressed, and executes the above-described arithmetic processing accordingly to control the line memories 23 and 24. ing. Actually, when writing to the line memories 23 and 24, the write address is incremented every one clock, and at the time of reading, the read address is controlled by performing the arithmetic processing described above every one clock, and at the same time, Phase, Flag and Skip signals are being output. Further, the changeover switches 22 and 25 are controlled for each line so that the above operation is toggled by the two line memories 23 and 24.

The image signals read from the line memories 23 and 24 are input to the shift register 38. The shift register 38 performs a data shift operation when Flag = 1. The image signals output from the respective stages of the shift register 38 are multiplied by the multiplication circuits 39 and 40, respectively.
Is multiplied by the coefficients a and b stored in the coefficient register 41 to be interpolated. The coefficients a and b stored in the coefficient register 41 are sent from the controller 29.

That is, for example, when E = 8, when the linear multiplication processing is performed by the two multiplying circuits 39 and 40, the coefficient values possessed by the coefficient register 41 are as shown in FIG. Then, the coefficient register 41 outputs the interpolation coefficients a and b selected based on the value of the input Phase signal to the multiplication circuits 39 and 40. The respective outputs of the multiplying circuits 39 and 40 are added by an adding circuit 42 to be interpolated.

The output of the adder circuit 42 is written in the line memories 44 and 45 by a toggle operation via the changeover switch 43 which switches the input for each line. The image signal written in these line memories 44 and 45 is 1
It is read from the line memories 44 and 45 by a toggle operation via a changeover switch 46 that switches the output for each line. The operations of the line memories 44 and 45 and the operations of the changeover switches 43 and 46 are controlled by the rear memory controller 47.

FIG. 10 is a flow chart showing the operation of the rear memory controller 47 for generating the write address. In the figure, Dst and Dend respectively indicate the start point and the end point of the horizontal display position of the compressed / decompressed image. Further, Skip is the above-mentioned Skip signal to which delay adjustment corresponding to multiplication is applied. In FIG. 10, when Skip = 0, the image signal is determined to be valid and the write address is incremented to cause the line memories 44 and 45 to perform the write operation. Further, when Skip = 1, the image signal is judged to be invalid and the write address is held so that the write operation to the line memories 44 and 45 is not performed.

FIG. 11 shows the configuration of the rear memory controller 50 which realizes the arithmetic processing of the flowchart shown in FIG. 10 with one kind of clock. That is, the value "0" supplied to the input terminal 501 is added to the value "1" supplied to the input terminal 504 by the adder circuit 503 after passing through the switch 502 and latched by the register 505. The output of the register 505 is fed back to the adder circuit 503 and taken out from the output terminal 506 as a read address.

In addition, the compression signal supplied to the input terminal 507
The value indicating the starting point of the horizontal display position of the decompressed image, after passing through the switch 508, is unchanged and the addition circuit 50
The value obtained by adding the value “1” supplied to the input terminal 5010 by 9 is selected by the multiplexer 5012 controlled by the Skip signal supplied to the input terminal 5011 and latched by the register 5013. And this register 5013
Is fed back to the adder circuit 509 and the multiplexer 5012 and taken out from the output terminal 5014 as a write address.

In reality, the rear memory controller 47
The above-described control is performed when writing to the line memories 44 and 45, and the read address is incremented every clock when reading from the line memories 44 and 45. In addition, the above-described operation is toggled by the two line memories 44 and 45 for each line, and the changeover switches 43 and 46 are controlled so as not to capture an invalid image signal. Then, the image signal subjected to the compression / expansion processing comes to be taken out from the output terminal 28.

By the series of operations described above, an arbitrary region can be compressed / expanded at an arbitrary compression / expansion rate in the horizontal direction of the image and displayed at an arbitrary position.

FIG. 12 shows a second embodiment of the present invention. 12, the same parts as those in FIG. 1 are designated by the same reference numerals, and the memory 51 is connected to the front memory controller 37. A part of the addition / subtraction result described above is stored in the memory 51, and the stored value is sequentially read every clock.

The values of p, Flag, and Skip shown in the flowcharts of FIGS. 3 and 5 are the period E when E ≧ C, and E
In the case of <C, the value is stored in the memory 51 because it is repeated in the cycle C. 13A shows the stored contents of the memory 51 when E / C = 5/3, and FIG. 13B shows E / C.
The storage contents of the memory 51 when C = 3/5 are shown.

The front memory controller 37 has a memory 51.
The values of p, Flag, and Skip are read from and output to the required circuits. At the same time, the read address is incremented when Flag = 1 within the range between the horizontal start point and end point of the image area to be compressed / decompressed.

FIG. 14 shows a third embodiment of the present invention. 14, when the same parts as those in FIG. 1 are denoted by the same reference numerals, the image signal supplied to the input terminal 26 is passed through an LPF (Low Pass Filter) 52 in the horizontal direction, and then the image signal processing circuit 27. By supplying
Aliasing that occurs during compression can be eliminated.

FIG. 15 shows the details of the LPF 52. That is, the image signal supplied to the input terminal 521 is supplied to the three 1-pixel delay circuits 5 connected in cascade.
22 to 524, adder circuit 525 and multiplexer 526
A first filter 52a composed of four 1-pixel delay circuits 527 to 5210, an addition circuit 5211 and a multiplexer 5212, and a second filter 52b composed of eight 1-pixel delay circuits 5213 to 5220, an addition circuit 5221 and a multiplexer 5222. It is taken out from the output terminal 5223 via the third filter 52c.

In this case, the LPF 52 has input terminals 5 to the multiplexers 526, 5212 and 5222 of the first to third filters 52a, 52b and 52c, respectively.
224, 5225, 5226 to the controller 2 supplied
The frequency characteristic is switched by switching the output based on the switching control signal output from 9. In the configuration shown in FIG. 15, the image is set to 1 horizontally.
Aliasing can be almost eliminated by compressing to / 8.

In the third embodiment, the high frequency component is removed before the image signal is input to the image signal processing circuit 27. However, even if this is not done, when the interpolation calculation is performed, the coefficient The frequency characteristic can be changed by changing the coefficient value of the register 41. However, in order to use this method, it is necessary to increase the number of multiplication circuits and the scale of the coefficient register 41, the shift register 38, and the addition circuit 42 as the compression rate increases. If the LPF 52 shown in FIG. 15 is used, the coefficient is 1
It is / 2 and 1/4, and since the bit shift of the image signal is used, it is not necessary to increase the multiplication circuits 39 and 40.

Next, FIGS. 16 and 17 show a fourth embodiment of the present invention. The fourth embodiment shown in FIGS. 16 and 17 is an application of the third and first embodiments shown in FIGS. 14 and 1 to the conversion processing of the image sampling frequency, respectively. 16 and 17
14, the same parts as those in FIGS. 14 and 1 are denoted by the same reference numerals. That is, considering conversion of the image signal of the sampling frequency f1 into the sampling frequency f2, f2
= (N / M) f1 and N <M, that is, f
The configuration in the case of 2 <f1 is as shown in FIG.

In this case, the image is compressed / expanded in the horizontal direction at the expansion ratio N / M times by the same operation as that of the third embodiment. The difference from the third embodiment is that only the rear memory controller 47 is supplied with the clock of frequency f2 via the input terminal 47c, and the rear memory controller 47 is operated with two clocks of frequencies f1 and f2. Is. At this time, the rear memory controller 47 determines that the frequency f
The processing after the control of the read addresses for the line memories 44 and 45 is executed based on the clock 2 and the processing before that is executed based on the clock of the frequency f1. Thereby, the image signal of the sampling frequency f1 can be converted into the sampling frequency f2.

When f2 = (N / M) f1,
FIG. 17 shows the configuration when N ≧ M, that is, when f2 ≧ f1.
It becomes what is shown in. In this case, the image is compressed / expanded in the horizontal direction at the expansion rate N / M times by the same operation as that of the first embodiment. The difference from the first embodiment is that only the front memory controller 37 is supplied with a clock of frequency f2 via the input terminal 37c, and the front memory controller 37 is operated by two clocks of frequencies f1 and f2. Is. At this time, the previous memory controller 37 uses the line memories 34 and 35 based on the clock of frequency f2.
Read address control for
The processing before that is executed based on the clock of frequency f1. Thereby, the image signal of the sampling frequency f1 can be converted into the sampling frequency f2.

FIG. 18 shows a fifth embodiment of the present invention. In the fifth embodiment, a vertically scanned image is subjected to vertical compression / expansion processing. 18, the same parts as those in FIG. 1 are designated by the same reference numerals. The difference from FIG. 1 is that the line memory 23,
24, 44, 45 are used instead of the frame memories 53 to 56, and a signal of the frame synchronization frequency fv is supplied to the front memory controller 37 and the rear memory controller 47 via the input terminals 37d, 47d. Is.

Upon performing vertical compression / expansion processing on the image, the CPU 31 causes the controller 29 via the system bus 30 to specify the expansion ratio of the image and the vertical start point of the area of the image to be compressed / expanded. End point value, start point and end point value indicating the vertical display position of the compressed / decompressed image,
Send commands such as interpolation coefficient values. Controller 2
9 classifies these commands and sends the expansion rate of the image and the values of the start and end points in the vertical direction of the area of the image to be expanded to the previous memory controller 37, and the interpolation register After sending the value, the memory controller 47
The start and end values indicating the vertical display position of the compressed / decompressed image are sent to.

The progressive scan image signal supplied to the input terminal 26 is written in the frame memories 53 and 54 by a toggle operation via the changeover switch 33 which switches the input for each frame. The image signals stored in the frame memories 53 and 54 are passed through the changeover switch 36 that switches the output for each frame,
4 is read. Such a frame memory 53,
The operation of 54 and the operations of the changeover switches 33 and 36 are controlled by the front memory controller 37.

However, in the front memory controller 37 shown in FIG. 18, the front memory controller 3 shown in FIG.
The difference from 7 is that the calculation of the above formula (1) is applied to the vertical address control of the image. The calculation method of the above formula (1) can be described in the same manner as in the first embodiment. Actually, the frame memories 53, 5
When writing to 4, the horizontal address is incremented every clock, and the vertical address is incremented every line. When reading from the frame memories 53 and 54, the horizontal address is incremented every clock. The address is incremented, the calculation of equation (1) is performed for each line, the address in the vertical direction is incremented, and the Phase (remainder), Flag, and Skip signals are output.

Further, the changeover switches 33 and 36 are controlled for each frame so that the above operation is toggled by the two frame memories 53 and 54. In addition, in the fourth embodiment, As shown in FIGS.
t and Aend respectively indicate the vertical start point and end point of the area of the image to be compressed / decompressed. The image signals read from the frame memories 53 and 54 are
It is input to the shift register 38.

FIG. 19 shows the details of the shift register 38. That is, the image signal supplied to the input terminal 381 is supplied via the multiplexer 382 to the shift register 383 which has a register for one line and shifts data for each clock. This shift register 3
The output of 8 3 is output through the output terminal 384 to the multiplication circuit 4
It is supplied to 0 and fed back to the multiplexer 382. This multiplexer 382 has an input terminal 385
Is controlled to output the image signal supplied to the input terminal 381 when the Flag signal supplied to the input terminal is "1", and to output the image signal output from the shift register 383 when the Flag signal is "0". .

The image signal output from the shift register 383 is supplied via a multiplexer 386 to a shift register 387 which has a register for one line and shifts data every clock. The output of the shift register 387 is supplied to the multiplication circuit 39 through the output terminal 388 and the multiplexer 3
Returned to 86. The multiplexer 386 outputs the image signal output from the shift register 383 when the Flag signal supplied to the input terminal 389 is "1", and the Flag signal
When the signal is "0", it is controlled to output the image signal output from the shift register 387.

The outputs of the multiplying circuits 39 and 40 are added in the adding circuit 42 to be interpolated. The output of the adder circuit 42 is written in the frame memories 55 and 56 by a toggle operation via the changeover switch 43 that switches the input for each frame. The image signals written in the frame memories 55 and 56 are changeover switches 46 for switching the output for each frame.
Is read from the frame memories 55 and 56 by a toggle operation. Such frame memories 55, 56
And the operation of the changeover switches 43 and 46 are controlled by the rear memory controller 47.

Rear memory controller 47 in FIG.
The difference from the first embodiment is that the operation shown in FIG. 10 is performed for each line. Actually, the post-memory controller 47 increments the horizontal address every clock when writing to the frame memories 55 and 56, and performs the operation shown in FIG. 10 for each line to calculate the vertical address. ing. Also,
The rear memory controller 47 includes the frame memories 55 and 5
When reading from 6, the horizontal address is incremented every clock and the vertical address is incremented every line.

Then, the rear memory controller 47 causes the two frame memories 55 and 56 to toggle the above operation for each frame, and also the changeover switches 43 and 43 so as not to write an invalid image signal.
46 is controlled. In the fourth embodiment, Dst and Dend shown in FIG. 10 indicate the vertical start point and end point of the position where the compressed / expanded image is displayed. Then, the image signal subjected to the compression / expansion processing comes to be taken out from the output terminal 28.

By the series of operations described above, an arbitrary region can be compressed / expanded at an arbitrary compression / expansion rate in the vertical direction of an image and displayed at an arbitrary position.

FIG. 20 shows a sixth embodiment of the present invention. 20, when the same parts as those in FIG. 18 are designated by the same reference numerals, the image signal supplied to the input terminal 26 is passed through the LPF 57 in the vertical direction and then supplied to the image signal processing circuit 27. Aliasing that occurs during compression can be eliminated.

FIG. 21 shows the details of the LPF 57. That is, the image signal supplied to the input terminal 571 is connected to the three 1-line delay circuits 572 to 574, the adding circuit 575 and the multiplexer 5 in a cascade.
Second filter 52b including four 1-line delay circuits 577-5710, adder circuit 5711 and multiplexer 5712, eight 1-line delay circuits 5713-5720, adder circuit 5721 and multiplexer It is taken out from the output terminal 5723 via the third filter 57c composed of 5722.

In this case, the LPF 57 inputs the input terminals 5 to the multiplexers 576, 5712 and 5722 of the first to third filters 57a, 57b and 57c, respectively.
724, 5725, 5726 said controller 2 supplied
The frequency characteristic is switched by switching the output based on the switching control signal output from 9. In the configuration shown in FIG. 21, the image is vertically set to 1
Aliasing can be almost eliminated by compressing to / 8.

The present invention is not limited to the above-described embodiments, but can be variously modified and implemented without departing from the scope of the invention.

[0074]

As described in detail above, according to the present invention,
The digital image signal can be subjected to compression / expansion processing using only its sampling frequency, and the digital image signal can be sampled using its sampling frequency and the sampling frequency after conversion processing. It is possible to provide an extremely good image signal processing device capable of performing frequency conversion processing.

[Brief description of the drawings]

FIG. 1 is a block configuration diagram showing a first embodiment of an image signal processing device according to the present invention.

FIG. 2 is a diagram for explaining a relationship between an address of a compressed / decompressed image and an address of an original image corresponding to the address of the compressed / decompressed image in the first embodiment.

FIG. 3 is a flowchart shown for explaining a calculation process for calculating an address of an original image corresponding to an address of a decompressed image according to the first embodiment.

FIG. 4 is a diagram specifically shown for explaining the same arithmetic processing according to the first embodiment.

FIG. 5 is a flowchart shown for explaining a calculation process for calculating an address of an original image corresponding to an address of a compressed image according to the first embodiment.

FIG. 6 is a diagram specifically shown for explaining the same arithmetic processing according to the first embodiment.

FIG. 7 is a block configuration diagram for realizing the arithmetic processing of the flowchart shown in FIG. 3 in the first embodiment.

FIG. 8 is a block configuration diagram for realizing the arithmetic processing of the flowchart shown in FIG. 5 in the first embodiment.

FIG. 9 is a diagram shown for explaining a specific example of a coefficient value of a coefficient register according to the first embodiment.

FIG. 10 is a flowchart shown to explain the arithmetic processing of the rear memory controller according to the first embodiment.

FIG. 11 is a block configuration diagram for implementing the arithmetic processing of the flowchart shown in FIG. 10 in the first embodiment.

FIG. 12 is a block configuration diagram showing a second embodiment of the present invention.

FIG. 13 is a diagram for explaining a specific example of a memory value at the time of expansion and compression in the second embodiment.

FIG. 14 is a block configuration diagram showing a third embodiment of the present invention.

FIG. 15 is a block configuration diagram showing details of an LPF according to the third embodiment.

FIG. 16 shows a fourth embodiment of the present invention,
The block block diagram which shows the case where the sampling frequency after conversion is lower than the original frequency.

FIG. 17 shows a fourth embodiment of the present invention,
The block block diagram which shows the case where the sampling frequency after conversion is higher than the original frequency.

FIG. 18 is a block configuration diagram showing a fifth embodiment of the present invention.

FIG. 19 is a block configuration diagram showing details of a shift register in the fifth embodiment.

FIG. 20 is a block diagram showing a sixth embodiment of the present invention.

FIG. 21 is a block configuration diagram showing details of an LPF in the sixth embodiment.

FIG. 22 is a diagram shown for explaining composition of a plurality of images.

FIG. 23 is a diagram shown for explaining horizontal compression / expansion of an image.

FIG. 24 is a diagram shown for explaining a change in horizontal address at the time of horizontal compression / expansion of an image.

FIG. 25 is a diagram shown for explaining a change in an image when a sampling frequency is converted.

FIG. 26 is a block diagram showing a conventional sampling frequency conversion circuit for converting the sampling frequency of an image signal to N / M times.

FIG. 27 is a block diagram showing a conventional expansion processing circuit for expanding an image signal by E / C times in the horizontal direction.

[Explanation of symbols]

11, 12 ... Input terminal, 13 ... Register, 14 ... Shift register, 15 ... Frequency multiplication circuit, 16 ... Weighted addition circuit, 17 ... Multiplication circuit, 18 ... Input terminal, 19 ... Register, 20 ... Frequency multiplication circuit, 21 ... Output terminal, 22 ... Changeover switch, 23, 24 ... Line memory, 25 ... Changeover switch, 26 ... Input terminal, 27 ... Image signal processing circuit, 2
8 ... Output terminal, 29 ... Controller, 30 ... System bus, 31 ... CPU, 32 ... Memory, 33 ... Changeover switch, 34, 35 ... Line memory, 36 ... Changeover switch,
37 ... Front memory controller, 38 ... Shift register,
39, 40 ... Multiplication circuit, 41 ... Coefficient register, 42 ... Addition circuit, 43 ... Changeover switch, 44, 45 ... Line memory, 46 ... Changeover switch, 47 ... Rear memory controller, 48, 49 ... Front memory controller, 50 ... Rear memory controller, 51 ... Memory, 52 ... LPF, 53-
56 ... Frame memory, 57 ... LPF.

Claims (4)

[Claims] 1. An image signal processing apparatus for horizontally compressing or expanding a digitized image signal, comprising: information indicating a horizontal compression or expansion ratio of the image signal; and compression of the image signal. Alternatively, information indicating the position of a horizontal region to be subjected to decompression processing, information indicating the display position of the horizontal region of the compressed or decompressed image signal, and a plurality of information for performing filtering calculation processing on the image signal. Setting means for setting a coefficient, information for indicating a compression or expansion rate of the image signal by generating a write address in the cycle of the sampling clock of the image signal, and a horizontal direction for performing the compression or expansion processing of the image signal And the information indicating the position of the area of the area, the read address is generated by performing the arithmetic processing in the cycle unit of the sampling clock, and First control means for selecting a necessary coefficient from a plurality of coefficients for performing filtering calculation processing on the image signal, and the image signal is line-based on the basis of the write address generated by the first control means. A first line memory written by the first control means and read based on the read address generated by the first control means; and an image signal read from the first line memory,
Means for inputting to the storage means for updating data based on the information generated by the first control means, and a coefficient selected by the first control means for the image signal output from the storage means. And a write address based on information indicating a display position of a horizontal region of the compressed or expanded image signal, and information generated by the first control means. To generate a read address at the cycle of the sampling clock of the image signal, and a sample in which the write address is updated by 1 based on the write address generated by the second control means. The image signal is written line by line only during the cycle of the digitized clock and is read based on the read address generated by the second control means. Image signal processing apparatus characterized by comprising; and a-memory. 2. The first and second control means determine a coefficient for performing the filtering operation when the expansion rate of the image signal is a fraction using a positive integer and the numerator is larger than the denominator. Value and the denominator of the expansion rate are added, and when the value is smaller than the numerator of the expansion rate, the read address of the first line memory holds the previous value and the data in the storage means is updated. First, the value of the write address of the second line memory is updated by 1, and the value for determining the coefficient for performing the filtering operation is a value obtained by adding the previous value and the value of the denominator of the expansion rate. The value for determining the coefficient to be performed is added to the denominator of the expansion rate, and when the value is larger than the numerator of the expansion rate, the read address of the first line memory is updated by 1, and the data of the storage means is updated. The value of the write address of the second line memory is updated by 1, and the value that determines the coefficient for performing the filtering operation is the value obtained by adding the previous value and the value of the denominator of the expansion rate to the numerator value. When the numerator of the expansion ratio is smaller than the denominator, the value for determining the coefficient for performing the filtering operation and the denominator of the expansion ratio are added to subtract the numerator, and the value is the numerator of the expansion ratio. If it is smaller, the value of the read address of the first line memory is updated by 1, the data of the storage means is updated, the value of the write address of the second line memory is updated by 1, and the filtering operation is performed. The value that determines the coefficient for performing the calculation is the value obtained by adding the previous value and the value of the denominator of the expansion rate and subtracting the value of the numerator. And is added to subtract the numerator, and when the value is larger than the numerator of the expansion rate, the read address of the first line memory is updated by 1 and the data of the storage means is updated. 3. The write address of the line memory of No. 2 holds the previous value, and the value for determining the coefficient for performing the filtering operation is the value obtained by subtracting the numerator value of the expansion rate from the previous value. The image signal processing device described. 3. The first and second control means, when performing sampling frequency conversion of the image signal, when the frequency after conversion is lower than the frequency before conversion, the second line memory. The processing after the control of the read address of is controlled by the frequency after conversion, the processing before that is controlled by the frequency before conversion, and when the frequency after conversion is higher than the frequency before conversion, the first line 2. The image signal processing apparatus according to claim 1, wherein the processing after the control of the read address of the memory is controlled by the frequency after conversion, and the processing before that is controlled by the frequency before conversion. 4. An image signal processing apparatus for vertically compressing or decompressing a digitized image signal of progressive scanning, comprising: information indicating a vertical compression or decompression rate of the image signal; Information for indicating the position of a vertical region on which the signal is compressed or expanded, information for indicating the display position of the compressed or expanded vertical region of the image signal, and for performing a filtering calculation process on the image signal Setting means for setting a plurality of coefficients of the image signal, horizontal writing address is generated in the cycle of the sampling clock of the image signal, vertical writing address is generated in the line cycle of the image signal, sampling clock of the image signal A horizontal read address is generated in a cycle of, and information indicating the compression or expansion rate of the image signal and compression or expansion processing of the image signal are performed. Necessary among a plurality of coefficients for generating a vertical read address by performing arithmetic processing at the line cycle by using the information indicating the position of the area in the direct direction and performing filtering arithmetic processing on the image signal. A first control means for selecting an appropriate coefficient, and the image signal is written in frame units on the basis of the horizontal and vertical write addresses generated by the first control means, and is generated by the first control means. A first frame memory read based on the horizontal and vertical read addresses, and an image signal read from the first frame memory are updated based on information generated by the first control means. Means for inputting to the storage means, and for the image signal output from the storage means, based on the coefficient selected by the first control means Calculating means for performing a filtering calculation process; information for indicating a display position of a vertical area of the compressed or expanded image signal, which generates a horizontal write address at a cycle of a sampling clock of the image signal; By using the information generated by the control means, the vertical write address is generated by performing the arithmetic processing in the line cycle, and the horizontal read address is generated in the cycle of the sampling clock of the image signal. A second control means for generating a vertical read address in a line cycle of, and a line cycle in which the vertical write address is updated by 1 based on the horizontal and vertical write addresses generated by the second control means. The signal is written in frame units, and based on the horizontal and vertical read addresses generated by the second control means. Image signal processing apparatus characterized by comprising and a second frame memory Desa seen.