JP4728744B2 - Image processing device - Google Patents

Description

  The present invention relates to an image processing apparatus for enlarging or reducing a digital image.

  In recent years, a dot matrix type image display device such as a liquid crystal display has been widely used including small portable devices. In such a dot matrix type display device, the resolution is generally fixed, but it is desired that various video inputs having different sizes can be displayed when applied to video equipment or the like. For this purpose, it is necessary to enlarge or reduce the video input as the original image in accordance with the resolution of the output device.

  A conventional image processing apparatus for realizing this will be described with reference to FIG. The image processing apparatus uses an original image memory 1 storing an original image written from a data bus connected to a CPU or the like, and bitmap image data read from the original image memory 1 as an enlargement / reduction ratio. An image processing unit 6 that performs enlargement / reduction processing using a dedicated circuit or software, an output memory 7 that stores the enlarged or reduced image data, and a reading unit 8 that extracts image data from the output memory 7. It is configured.

  When there is an image output request from an external device (not shown) such as an external CPU or a display device, the image processing apparatus first reads the original image data from the original image memory 1 and stores the read original image data. The image processing unit 6 performs enlargement or reduction processing of the original image in accordance with the output resolution. When the image is enlarged, enlargement processing and interpolation processing of the original image are performed, and at the time of reduction, only necessary pixels are read out by pixel thinning processing. The image data of the enlarged image or reduced image is once taken into the output memory 7, and the image data of the enlarged image or reduced image is then thinned by the display data read enable signal output from the thinning readout unit 8 and the address thinned out. Are read from the output memory 7 and sent to an external device such as a display device.

For the processing at the time of image reduction used at this time, in order to perform fine reduction in dot units, a technique has been proposed in which image data is enlarged by interpolation in advance and then thinned out for each dot unit. No. 2-174463. In this technique, when image data to be enlarged is input to the interpolation circuit, pixel data for each three points is set in the latch circuit, and the interpolation data is read out by the address signal so as to obtain a desired enlargement / reduction ratio. The image is enlarged. Then, when thinning out the enlarged image data in the thinning circuit, by giving a clock pulse thinned out to the shift register, the reduced image data thinned out in dot units is set in the shift register of the next stage, This is a technique for reducing an image stored in an image memory.
JP-A-2-174463

  However, since the conventional image processing apparatus requires an output memory having a size corresponding to the resolution of the display device, the hardware scale increases, causing problems such as an increase in equipment cost and power consumption. In addition, there are pixels that are not referred to among the pixels of the original image only by thinning out the pixels of the original image when the image is reduced. Therefore, for example, when there is a thin line in the original image, there is a problem that the line disappears after reduction or does not become a smooth line.

  Further, in the invention of Japanese Patent Laid-Open No. 2-174463, since interpolation is performed up to the pixel to be thinned out at the stage of enlarging the original image, unnecessary extra processing is performed. There was a problem directly related to an increase in power consumption.

  The image processing apparatus according to the present invention calculates an original image memory for storing an original image, an enlargement / reduction ratio of the original image in the horizontal direction and the vertical direction based on the original image resolution and the display image resolution, and each of the enlargement / reduction ratios. An output magnification setting unit; a virtual address generation unit that generates a virtual address by using a resolution of a display device, an enlargement / reduction magnification of the original image obtained from the magnification setting unit, and a base address serving as a reference for a virtual address; Converting the virtual address into a real address and outputting an interpolation coefficient for performing interpolation of pixel data; reading out the pixel data of the original image from the original image memory based on the real address; And an image interpolation unit that generates and outputs display image data using the interpolation coefficient from the real address conversion unit. It is.

  With such a configuration, the original image can be enlarged or reduced to an arbitrary resolution of the display image without requiring an image output memory.

  At this time, the magnification setting unit calculates the magnification of the original image with respect to the display image resolution in the horizontal direction and the vertical direction, expresses the magnification as a fractional value, and outputs the denominator value and the numerator value of the fraction. It is desirable to make it. With this configuration, even if the magnification of the original image is a non-integer multiple, the numerator and denominator are integers, so the denominator is used for virtual address formation, and the numerator is used for virtual address to real address conversion. The value for calculation to do is obtained as an integer value.

  Further, the magnification setting unit may output a magnification in which the numerator value is fixed and only the denominator value is variable. Further, the value of the fixed numerator may be set to a power of 2 as necessary. By adopting such a configuration, multiplication and division required when converting from a virtual address to a real address in the real address conversion unit can be realized by a shift operation, so it can be realized by a general multi-stage shift register, and a circuit configuration Becomes easier.

  The virtual address generation unit may be configured to generate a virtual address including orthogonal coordinates with the denominator value as an increment value from the base address when the denominator value of the scaling factor is a positive integer. . With this configuration, the orthogonal coordinates of the virtual address for performing pixel interpolation can be easily obtained.

  In addition, when the denominator value of the magnification is expressed as a fraction, the numerator value of the fraction is decomposed so that the fractional denominator value is the number of positive integer values, and those positive integers are calculated from the base address. It is preferable to generate a virtual address including orthogonal coordinates with numerical value intervals as increments. With this configuration, a virtual address including integer coordinates can be generated even if the denominator of the enlargement / reduction ratio is not an integer.

  In addition, the real address conversion unit calculates the quotient of the division value obtained by dividing the orthogonal coordinates of the virtual address by the numerator values of the horizontal and vertical magnifications, and the orthogonal coordinates of the pixels on the real address of the original image memory. Good. By adopting such a configuration, it is possible to obtain the orthogonal coordinates of the pixels on the real address of the original image as the origin from which the pixels on the orthogonal coordinates of the virtual address are interpolated with integer coordinates. Will be easy.

  Further, the remainder value obtained by dividing the orthogonal coordinates of the virtual address by the numerator values of the horizontal and vertical magnifications may be used as the respective interpolation coefficients in the horizontal and vertical directions used for image interpolation. With such a configuration, the interpolation coefficient can be obtained as an integer value.

  In addition, the image interpolation unit reads the pixel data of the orthogonal coordinates in the real address space and the plurality of pixel data in the vicinity thereof, and interpolates the image from the plurality of pixels using the interpolation coefficient as the distance from the orthogonal coordinates of the plurality of pixels in the virtual address. And the image-interpolated image data may be output as display image data. By adopting such a configuration, it is possible to realize image interpolation with high accuracy calculation using the orthogonal coordinates of the real address space and the pixel data of the orthogonal coordinates.

  According to the present invention, an enlarged or reduced display image with better image quality can be obtained with a small circuit.

  FIG. 1 shows a basic configuration of an image processing apparatus according to this embodiment. The image processing apparatus according to the present embodiment includes an original image memory 1 that stores an original image written from a data bus, and an original image enlargement / reduction ratio according to the resolution of the original image and the resolution of the display image. The magnification setting unit 2 that outputs the numerator value and the denominator value after the scaling magnification is expressed in fractions, and the image readout start signal output from the display device (not shown) is activated. Then, a virtual address is generated using the resolution of the display device and the enlargement / reduction ratio of the original image obtained from the magnification setting unit 2, and a virtual address generation unit 3 that generates an enable signal for reading out pixel data of the display image; Based on the real address, a real address conversion unit 4 that converts the virtual address into a real address to be output to the original image memory and outputs an interpolation coefficient for interpolating the pixel data. Reading out pixel data of the original image from the image memory, it performs the generation of the interpolation pixel by using the interpolation coefficients from the real address conversion unit, and a picture interpolation unit 5 and outputs the interpolated pixel as the display image data.

  The resolution of the original image and the display image input to the magnification setting unit 2 is given by an external CPU. Signals MX and MY shown in FIG. 1 are numerator values obtained by calculation in the horizontal and vertical directions output from the magnification setting unit 2. The signals JX and JY are denominator values obtained by calculation in the horizontal direction and the vertical direction, respectively. Signals SX and SY are horizontal and vertical interpolation coefficients used to interpolate image data. A method for generating these signals will be described later. The address generated by the virtual address generation unit 3 is handled as a virtual address because it does not directly correspond to the address of a storage device such as a memory or a register. Image reduction means enlargement of an image at a magnification smaller than 1.

  Next, the operation flow of the image reading apparatus of the present invention will be described based on the flowchart shown in FIG. First, the original image resolution and the display image resolution are input to the magnification setting unit 2. This is performed by a method in which the CPU outside the apparatus writes the resolution in a register provided in the magnification setting unit 2 (S1).

Next, a pixel readout start signal is enabled from the display device as the display device is scanned (S2). Then, after referring to the base address indicating the first pixel read out in the virtual address in the virtual address generation unit 3, the virtual address corresponding to the display image is generated using the base address as the origin. (S3)
Next, the virtual address of the pixel is converted into a real address for reading out the original image memory 1 by the real address conversion unit 4 (S4). Then, the pixel data at the corresponding real address and the pixel data of a plurality of original images in the vicinity of the address are read from the original image memory 1 (S5), and the image interpolating unit 5 reads out the pixels of the plurality of original images. Interpolated pixels are generated (S6), and the pixels in each case are output (S7). Next, it is determined whether or not the virtual address indicates the final pixel of the pixels to be output (S8). If the virtual address does not indicate the final pixel, the virtual address is incremented (S9) and S5 is performed. The process is repeated until the virtual address indicates the last pixel, that is, until all the pixels of the display image are output.

  Next, the operation of the image processing apparatus of the present invention will be described in detail.

  First, the magnification setting operation in the magnification setting unit 2 will be described. The enlargement / reduction ratio of the original image is calculated by the magnification setting unit 2. The calculation is performed using the resolution of the original image and the display image resolution, and the enlargement / reduction ratio is obtained by (resolution of the display image) / (resolution of the original image) in each of the horizontal direction and the vertical direction. Here, the respective enlargement / reduction ratios in the horizontal direction and the vertical direction can be expressed by fractions of MX / JX and MY / JY. MX / JX and MY / JY may be obtained by dividing the value of the numerator and the value of the denominator. However, as will be described later, the values of numerators JX and JY are raised to the power of 2 as much as possible. It is desirable that the fraction be such that MX, JX, MY, and JY are all integers of 1 or more.

  Next, an example of calculating the enlargement / reduction ratio of the original image with respect to the resolution of the display image according to the above-described method will be described. It is assumed that 800 dots × 600 dots and 1280 dots × 960 dots are input to the magnification setting unit 2 as the resolutions of the original image and the display device. Then, the enlargement / reduction ratio is 8/5 in both the horizontal and vertical directions, and MX = MY = 8 and JX = JY = 5 are calculated.

  As another example, when the resolutions of the original image and the display device are 800 dots × 600 dots and 1600 dots × 1200 dots, respectively, are input to the magnification setting unit 2, the enlargement / reduction magnification is 2 in both the horizontal and vertical directions. Doubled, MX = MY = 2 and JX = JY = 1 are calculated.

  As yet another example, when the resolution of the original image and the display device is 1600 dots × 1200 dots and 800 dots × 600 dots are input to the magnification setting unit 2, the enlargement / reduction magnification is 1 in both the horizontal and vertical directions. / 2 times, numerator value and denominator value are doubled to calculate MX = MY = 2 and JX = JY = 4.

Next, generation of a virtual address performed by the virtual address generation unit 3 will be described. Here, description will be made using orthogonal coordinates corresponding to the virtual address. If the orthogonal coordinates of the virtual address are (VX, VY) and the orthogonal coordinates corresponding to the read start address (base address) are (BX, BY), the orthogonal coordinates (VX, VY) of the virtual address are the base address (BX , BY) as a reference, the denominators JX, JY of the enlargement / reduction ratios in the horizontal direction and the vertical direction can be expressed as increment values,
VX = BX + JX × x
VY = BY + JY × y
It becomes. Here, (0, 0) is given as the base address, but an arbitrary address may be given as the base address. However, it is desirable to fix the address value.

  In the above formula, x is a coordinate variable in the horizontal direction, and its range is an integer that satisfies 0 ≦ x ≦ (resolution in the horizontal direction of the display image−1). Further, y is a vertical coordinate variable, and its range is an integer variable such that 0 ≦ y ≦ (resolution of the display image in the vertical direction−1). Thus, the orthogonal coordinates of the virtual address can be obtained for all integers in the range with this variable (x, y).

  Various methods for incrementing the coordinate variables x and y are conceivable, but there are the following methods as general methods. If the base address is (x, y) = (0, 0), start from the virtual address (VX, VY) = (BX, BY) from the above formula, and increment x by 1 until x reaches the maximum value. I will do it. Each time x reaches the maximum value, that is, x = (resolution in the horizontal direction of the display image−1), x is reset to 0, and at the same time, y is incremented by 1, and x is incremented by 1 again. Thereafter, the same x and y increments are performed, and both x and y become maximum values, that is, x = (horizontal resolution-1 of the display image) and y = (vertical resolution-1 of the display image). Coordinates that repeat until are generated. As described above, it is possible to obtain the coordinates of the virtual address that form the pixels having the number of dots of the resolution of the display image.

As an example of generating a virtual address, when the resolution of the original image and the display image is 6 dots × 4 dots and 12 dots × 8 dots as shown in FIG. 3, the enlargement / reduction ratio is double in both the horizontal and vertical directions. And JX = JY = 1 is obtained. If the base address is (0, 0), the virtual address (VX, VY) is
VX = 0 + 1 × x = x (where 0 ≦ x ≦ 11)
VY = 0 + 1 × y = y (where 0 ≦ y ≦ 7)
It becomes.

As another example, when the resolution of the original image and the display image is 6 dots × 4 dots and 8 dots × 6 dots as shown in FIG. 4, the enlargement / reduction ratio is 4/3 in the horizontal and vertical directions, respectively. Double and 3/2 times to obtain JX = 3 and JY = 2. If the base address is (1, 0), the virtual address (VX, VY) is VX = 1 + 3 × x (where 0 ≦ x ≦ 7).
VY = 0 + 2 × y = 2 × y (where 0 ≦ y ≦ 5)
It becomes.

Here, a method of mutual conversion between general addresses and orthogonal coordinates will be described. First, this mutual conversion method can be easily realized if the base address in the read coordinate space and the horizontal resolution of the image are known. For example, if X and Y are the orthogonal coordinates of an arbitrary dot in the image, P is the address of the dot, B is the base address, and W is the horizontal resolution (width) of the image,
P = B + Y × W + X
Conversely, from address to Cartesian coordinates Y = (P−B) / W
X = (P−B)% W
Can be converted. Here, / represents the quotient of integer division, and% represents the remainder in integer division. When addresses and coordinates are expressed in binary numbers and W is a power of 2, multiplication and division can be realized by a shift operation. Therefore, it can be realized by a general multi-stage shift register, and the circuit configuration is simplified and the mounting area is reduced. It is effective in reducing the size of If W is not a power of 2, it is preferable to define the horizontal method resolution as a new W that is a power of 2 greater than W. However, an unnecessary space generated between the original W and the new W is not used for image processing. By using the above conversion method, the mutual conversion method of addresses and orthogonal coordinates can be applied to the original image and the virtual address space.

Next, processing of the address conversion unit 4 that converts the generated virtual address into a real address for reading the original image from the image memory 1 will be described. The orthogonal coordinates in the real address space are obtained by the quotient of division obtained by dividing the orthogonal coordinates (VX, VY) of the virtual address by MX and MY in the horizontal and vertical directions, respectively. That is, the orthogonal coordinates in the real address space can be expressed by a quotient of (VX / MX, VY / MY). The address conversion unit 4 converts the quotient of this division into an address, outputs it as a real address, and simultaneously generates the remainder of the division as an interpolation coefficient. If this interpolation coefficient is SX and SY with respect to the horizontal direction and the vertical direction, respectively,
SX = VX% MX
SY = VY% MY
It becomes. Further, the orthogonal coordinates (VX / MX, VY / MY) in the real address space are converted into real addresses by the mutual conversion method between the general address and the orthogonal coordinates described above. With this real address, the pixel data of the original image is read from the original image memory 1. The pixel data and the interpolation coefficient (SX, SY) are input to the image processing unit 5.

  The image processing unit 5 generates pixel data interpolated according to the interpolation coefficients (SX, SY) based on the pixel data read from the original image memory 1, and uses the pixel data in the orthogonal coordinates (VX, VY) of the virtual address. Output as. The pixel data becomes display image data.

There are various image interpolation means. In the case of linear interpolation using 4 points (2 horizontal points × 2 vertical points) as an example, the image processing unit 5 activates the original image memory when the original image read enable is activated. 1 to a pixel of orthogonal coordinates (VX / MX, VY / MY) in the real address space, and three orthogonal coordinates ((VX / MX) +1, VY / MY), (VX / MX, (VY / (MY) +1), ((VX / MX) +1, (VY / MY) +1) pixels, a total of four pixel data are read. Assuming that these pixel data are P00, P10, P01, and P11, respectively, the pixel data P at the virtual address (VX, VY) is converted into P = ((P00 × (MX−SX) + P10 × SX) × (MY-SY)
+ (P01 × (MX−SX) + P11 × SX) × SY) / (MX × MY)
Output as. Note that there may be no pixel to be interpolated in the vicinity of the edge of the enlarged image. In this case, the neighboring pixel data is copied as it is.

  In this example, an enlargement / reduction ratio of 1/2 or more is ideal in order to perform processing that uses all the pixels of the original image. When the magnification is smaller than ½, since there are pixels of the original image that are not used at all for output, information held in the original image is lost. For this reason, in general, when using interpolation means using pixels of N points (N is an integer value of 1 or more) in the vertical (horizontal) direction, the vertical (horizontal) direction magnification is set to 1 in order to prevent missing information. / N or more is necessary. In this case, the orthogonal coordinates of the base address at the minimum magnification of 1 / N are the center coordinates of N points in the vertical (horizontal) direction. However, when the center coordinate is a fraction, it is necessary to make the coordinate space by multiplying the numerator and denominator of the fraction by the same power of two. For example, when the horizontal direction and the vertical direction are both ½ times, two-point × two-point four-point interpolation ((0,0), (1,0), (0,1), (1,1) Since the center coordinates of (interpolation used) are normally (1/2, 1/2), the numerator and denominator are each multiplied by 2 to give (1, 1). In this case, the magnification in the horizontal (vertical) direction is 2/4.

  For example, when the horizontal and vertical magnifications are 1/3 and 1/5, respectively, the orthogonal coordinates of the base address are the coordinates of the center of 3 points in the horizontal direction and the center of 5 points in the vertical direction, That is, the coordinates are the center of 15 points.

  When the above-described interpolation means is used, the output P is always equal to P00 when SX = SY = 0. Therefore, in this case, only the pixel P00 corresponding to (VX / MX, VY / MY) is read from the original image memory 1 and output as it is, and the above-described interpolation means is used only when SX ≠ 0 or SY ≠ 0. It may be.

  As a specific example of using such an interpolation means, the case where the enlargement / reduction ratio of the original image is an integer multiple will be described with reference to FIG. 5, and the case where it is a non-integer multiple will be described with reference to FIG. 6.

  FIG. 5 shows a case where the resolutions of the original image and the display device are 6 dots × 4 dots and 18 dots × 12 dots, respectively. At this time, JX = JY = 1. The virtual address is as shown in FIG. When the X component and Y component of the orthogonal coordinates of all dots on the virtual address are each divided by 3, and the remainder of each division is SX = SY = 0, the division result and the original image data of the image memory 1 Pixel data matching the coordinates is output as it is without image interpolation. When the remainder of division SX ≠ 0 or SY ≠ 0, the pixel of the coordinates of the original image that matches the division result and the pixel data in the vicinity thereof are read out, and after the image interpolation is performed using the interpolation means, the interpolation is performed. Output the pixel data.

For example, in the case of generating the data of the pixel a at the orthogonal coordinate (6, 3) of the virtual address shown in FIG. 5B, the orthogonal coordinate is the virtual enlargement / reduction ratio in each of the horizontal direction and the vertical direction. When dividing by 3, since the quotient of the division result is (2, 1) and the remainder result is (0, 0), that is, the interpolation coefficient is (0, 0), the orthogonal coordinates (2, 1) on the real address The pixel I data is read out as it is and becomes the pixel data of the display image without interpolation. Further, taking as an example the generation of the pixel b at the orthogonal coordinate (5, 7) of the virtual address shown in FIG. 5B, the orthogonal coordinate is set to 3 which is the virtual enlargement / reduction magnification in each of the horizontal direction and the vertical direction. When dividing, the quotient of the division result is (1,2) and the remainder result is (2,1). The quotient (1, 2) of the division result corresponds to the pixel N in the orthogonal coordinates of the original image, and interpolation is performed using pixel data in the vicinity of the pixel N with reference to the pixel data of the pixel N. When the above-described linear interpolation is used as the interpolation unit, a total of four pieces of pixel data of the pixel N and its neighboring pixels, the pixel O, the pixel T, and the pixel U, are read. If the pixel data of the pixels N, O, T, and U are PN, PO, PT, and PU, respectively, the pixel data P of the pixel b is
P = ((PN × 1 + PO × 2) × 2 + (PT × 1 + PU × 2) × 1) / (3 × 3)
Output as.

  Next, enlargement control of a display image that is a non-integer multiple of the original image will be described with reference to FIG. When the resolutions of the original image and the display image are 6 dots × 4 dots and 8 dots × 6 dots, the enlargement / reduction ratios are 4/3 times and 3/2 times respectively in the horizontal direction and the vertical direction, and JX = 3, JY = 2. When the orthogonal coordinate of the base address is (1, 0), and the dot used for display in the virtual address space is displayed in the orthogonal coordinate of the virtual address, the portion surrounded by the bold square in FIG. Become. The display image is an output of the portion surrounded by the thick square, and the pixel without interpolation indicated by the uppercase alphabet in FIG. 6C and the pixel indicated by the lowercase alphabet are: Interpolated pixels.

  Next, with reference to FIG. 7, the reduction control of the display image that is ½ times the original image will be described. When the resolution of the original image and the display device is 8 dots × 6 dots, 4 dots × 3 dots, the enlargement / reduction ratio is 1/2 times in both the horizontal direction and the vertical direction, and this magnification is 2 horizontal points × vertical This is the minimum magnification for four-point interpolation that is two points. If MX = MY = 1 and JX = JY = 2 at this magnification, the orthogonal coordinates of the base address that achieves the best resolution are (1/2, 1/2), which are non-integer coordinates. Therefore, if a virtual address such that MX = MY = 2 and JX = JY = 4 is formed, the pixels surrounded by the bold squares are displayed as shown in FIG. 7B. Here, in order to use all the pixels of the original image for interpolation, the center (1, 1) of the four pixels used for interpolation is used as the base coordinates. As shown in FIG. 7C, the display image is all interpolated pixels because all the pixels are indicated by lowercase alphabets.

  By the way, in the linear interpolation using a total of four points in the above-mentioned two points in the vertical and horizontal directions, division is necessary at the time of interpolation. In general, a division circuit that can arbitrarily designate a divisor is very complicated. In order to suppress the circuit scale, it is effective to use the divisors, ie, MX and MY as constants, especially powers of 2. In this case, JX and JY should not be less than 1 in order not to cause degradation of image quality due to one pixel being output multiple times, so the maximum magnification is MX times in the vertical and horizontal directions, Limited to MY times. For example, when MX = MY = 4 is fixed by design, a virtual address where JX = 2 and JY = 1 is assumed when image processing is performed with vertical and horizontal enlargement / reduction ratios of 2 × and 4 ×, respectively. To do.

  When MX and MY are constants, depending on the enlargement / reduction ratio, JX or JY may be not only an integer of 1 or more, but may be a non-integer, and this non-integer is expressed as a fraction. Here, the generation method of the virtual address at the time of this non-integer will be described by taking the horizontal coordinate as an example.

  If JX becomes a non-integer, it can be expressed as JX = AX / BX. Here, both AX and BX are positive integer values, which are a numerator value of JX and a denominator value of JX, respectively, and satisfy AX ≧ BX. The virtual address generation method in this case is as follows. AX is decomposed into BX positive integer values, and the decomposed positive integer values are used as the increment value of the orthogonal coordinates of the virtual address until the total in each direction corresponds to the resolution of the display image. Virtual addresses are repeatedly generated until these intervals are reached. Ideally, this positive integer value decomposition should be as uniform as possible. Although the above description is about the horizontal direction, the same applies to the vertical direction, and it is better to replace “X” with “Y” in the above description.

  For example, when MX = MY = 4 is fixed by design, JX = 8/3, JY = 12 when image processing is performed with the enlargement / reduction ratio in the vertical direction and the horizontal direction being 3/2 times and 5/3 times, respectively. / 5. In this case, when 8 is divided into positive integer values that are as uniform as possible into three numbers, it becomes 3, 3, 2 (of course, 3, 2, 3 may be used, or 2, 3, 3 may be used). If 12 is divided into positive integer values that are as uniform as possible in 5 numbers, 3, 3, 2, 2, 2 (of course, other combinations may be used as long as 3 is 2, 2 and 3 are combined. )become. Therefore, the coordinate interval for obtaining the orthogonal coordinates of the virtual address is 3, 3, 2, in the horizontal direction, and 3, 3, 2, 2, 2 in the vertical direction as increments. The virtual address interval may be generated repeatedly until the resolution is reached.

  As described above, according to the present invention, an enlarged or reduced image with better image quality can be obtained with a small circuit.

It is a block diagram of the image processing apparatus of this invention. 3 is an operation flowchart of the image processing apparatus of the present invention. It is a figure explaining the virtual address used as the integral multiple expansion of an original image. It is a figure explaining the virtual address used as non-integer multiple expansion of an original image. It is a figure explaining the case where an original image is expanded by integer times using an interpolation means. It is a figure explaining the case where an original image is expanded by non-integer times using an interpolation means. It is a figure explaining the example in the case of producing the display image which becomes 1/2 time of an original image. It is a block diagram of the conventional image processing apparatus.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Original image memory 2 Magnification setting part 3 Virtual address generation part 4 Real address generation part 5 Image processing part 6 Output memory 7 Reading circuit 21 Original image resolution register 22 Display image resolution register 23 Magnification setting part 51 Original image reading part 52 Image Interpolator

Claims (7)

An original image memory for storing the original image;
A magnification setting unit that calculates an enlargement / reduction ratio of the original image in a horizontal direction and a vertical direction according to an original image resolution and a display image resolution, and outputs the enlargement / reduction ratio, respectively;
A virtual address generation unit that generates a virtual address based on the resolution of the display device, the enlargement / reduction ratio of the original image obtained from the magnification setting unit, and the base address serving as a reference for the virtual address;
A real address conversion unit that converts the virtual address into a real address and outputs an interpolation coefficient for performing interpolation of pixel data;
An image interpolation unit that reads out pixel data of the original image from the original image memory based on a real address, generates display image data using the interpolation coefficient from the real address conversion unit, and outputs the display image data ;
The magnification setting unit calculates the magnification of the original image with respect to the display image resolution in the horizontal direction and the vertical direction, respectively, and represents the denominator value and the numerator value of the fraction when the enlargement / reduction ratio is expressed in fractions. Output configuration,
An image processing apparatus, wherein the magnification setting unit outputs a magnification in which the numerator value is fixed and only the denominator value is variable. The image processing apparatus according to claim 1 , wherein the magnification setting unit sets the value of the numerator to a power of two. The virtual address generation unit, when the denominator value of the enlargement / reduction ratio is a positive integer, includes virtual coordinates including orthogonal coordinates that are rows or value columns of values obtained by incrementing the denominator value from the base address. the image processing apparatus according to claim 1 or 2, characterized in that to produce a specific address. When the denominator value of the scaling factor is expressed as a fraction (hereinafter referred to as a second fraction), the virtual address generation unit uses the denominator value of the second fraction as a decomposition number, and the second fraction virtual address of the value of the numerator is decomposed as the sum of positive integer values consisting of the number of the decomposition number includes a row or orthogonal coordinate for the row of values and increment the positive integer value from said base address The image processing apparatus according to claim 1 , wherein the image processing apparatus generates an image. The real address conversion unit includes a process of outputting a quotient of a division value obtained by dividing orthogonal coordinates of the virtual address by a numerator value of the enlargement / reduction ratio in each of a horizontal direction and a vertical direction. Item 5. The image processing apparatus according to Item 3 or 4 . The real address conversion unit according to claim characterized in that it comprises a process of outputting a remainder value obtained by dividing the orthogonal coordinates of the virtual address in the horizontal and vertical values of each of the scaling factor molecules 5 An image processing apparatus according to 1. The image interpolation unit reads out the pixel data of the orthogonal coordinates in the real address space and a plurality of pixel data in the vicinity thereof, and sets the interpolation coefficient as the distance from the pixel data of the orthogonal coordinates in the real address space in the virtual address. The image processing apparatus according to claim 5 , further comprising a process of performing interpolation of