JP2010033406A - Image processing device, image device, and image processing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain interpolation values of given two values of an interplation subject with a high degree of accuracy using simple circuitry and a simple processing method. <P>SOLUTION: The method sets up an interpolation coefficient α (α is greater than or equal to 0 and is less than or equal to 1) and an output pixel number n (n is a positive integer). During n times calculation processes, an initial position β is set such that a value of a decimal part of ζ, i.e. point(ζ) is not zero. Then the method identifies coordinates of given two pixels for interpolation according to a formula ζ=k*α+β (k=1, ..., n). Then the method calculates a pixel value C of the interpolated pixel position based on the two given pixel values A, B to be interpolated, the interpolating coefficient α, and the output pixel number n using a similar formula as that of a general linear interpolation. The circuitry size and calculation process steps are simple since the method is based on a linear interpolation. Since the initial position β is set such that a value of a decimal part of ζ, i.e. point(ζ) is not zero, case analysis in calculation process is not needed. Accordingly, additional circuitry and process steps for dealing with a case analysis are not needed. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an image processing apparatus, an image device, and an image processing method. More specifically, the present invention relates to a linear interpolation calculation, and more particularly to a technique for realizing a simple processing method capable of calculating an interpolation value with high accuracy.

  Digital graphics represented by discrete digital data may be resampled at a sampling rate different from the original in various graphics processing such as enlargement / reduction processing such as resolution conversion and aspect conversion (patent) Literatures 1-3).

Japanese Patent Laid-Open No. 11-353473 Japanese Patent Laid-Open No. 07-200869 JP 2007-226422 A

  When resampling processing is realized by hardware (H / W: HardWare) or software (S / W: SoftWare), it is desired to obtain a calculation result with as high accuracy as possible. In addition, simplification of processing steps is also desired. In general, it is difficult to satisfy both of them at the same time, and the trade-off between the calculation accuracy affecting the discretization error, the circuit scale, and the processing scale becomes a problem. For this reason, it is required to realize a simple processing method that can calculate an interpolation value with high accuracy.

  As a mechanism for obtaining a calculation result with high accuracy, for example, a method of performing data interpolation using a sampling function such as a sinc function is known as a data interpolation method for obtaining a value between given discrete values ( (See Patent Document 1). When the sinc function is used as a sampling function, an accurate interpolated value can be obtained by theoretically adding the values of the sampling functions corresponding to the pixel values from −∞ to + ∞ by convolution. . However, since a convolution operation is required, the circuit scale increases.

  On the other hand, as a simple interpolation calculation method, linear interpolation for obtaining an intermediate value between two values by interpolation is known. In linear interpolation, when calculating a pixel value of one point (C) from two (A, B) points adjacent to each other in a digital image, an interpolation coefficient α is used to obtain a ratio of α: (1-α) (0 ≦ The pixel value at the interpolation position is synthesized with α ≦ 1). Expressed by the equation, a linear interpolation value C represented by C = (1−α) · A + α · B is obtained.

  Patent Documents 2 and 3 disclose a mechanism for performing calculations according to this linear interpolation. In the linear interpolation calculator described in Patent Document 2, a highly accurate calculation result can be obtained, but on the other hand, the division is performed and the structure is complicated.

  On the other hand, in the linear interpolation calculator described in Patent Document 3, the denominator of the decimal part of the interpolation coefficient α is set to 2 ^ n-1 (power of 2-1) instead of 2 ^ n (power of 2). We are trying to reduce the scale of the circuit while suppressing the drop. At this time, in order to deal with a calculation in a finite range, the (n + 1) digit after the decimal point (1/2 ^ (n + 1) digit) of the value of the interpolation coefficient α is rounded off to the nearest zero. An approximate value α ′ having up to n significant digits (1/2 ^ n digits) is obtained. Then, instead of performing the division of α = D / (2 ^ n−1), an approximate value α ′ is obtained by addition, thereby realizing a simple circuit that does not include division.

  However, the mechanism of Patent Document 3 involves a process of rounding off (n + 1) digits (1/2 ^ (n + 1) digits) after the decimal point of the value of the interpolation coefficient α. In other words, a mechanism for dealing with cases in the calculation process is required. For example, when the decimal part is handled with 8 bits, it is necessary to provide an extra circuit for discriminating whether the 9th bit (1/2 ^ 9 digit) is “rounded down” or “1”. The circuit configuration becomes complicated.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a mechanism that can obtain an interpolation value for two interpolation target values with high accuracy by a simple circuit configuration and a simple processing method. And

  In one embodiment of the present invention, an interpolation coefficient α (0 ≦ α ≦ 1) and an output pixel number n (n is a positive integer equal to or greater than 1) are set. In the interpolation calculation, the coordinates of the two pixels to be interpolated are specified according to the equation ζ = k · α + β (k is 1 to n) as the initial position β, and the values A, B, Based on the interpolation coefficient α and the number of output pixels n, the pixel value C at the interpolation position is obtained according to the equation (X), as in general linear interpolation.

  Here, in the present invention, the initial position β is set so that the value of the fractional part point (ζ) of ζ does not become zero in the calculation process of n times by the calculation unit.

  Since it is based on linear interpolation processing, the circuit scale and arithmetic processing steps are basically simple. In addition, since the initial position β is set so that the value of the decimal part point (ζ) of ζ does not become zero, a mechanism for dealing with cases in the calculation process is not required. It is not necessary to provide an extra circuit or processing step for dealing with cases.

  According to one aspect of the present invention, interpolation values for two interpolation target values can be obtained with high accuracy by a simple circuit configuration and a simple processing method.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a diagram showing a configuration example of an image processing apparatus (image processing system) to which an image processing method according to the present invention is applied.

<Overall configuration of image processing apparatus>
The image processing apparatus 1 according to the present embodiment includes a data storage unit 10 (image storage memory) that stores (stores) image data, an interpolation calculation processing unit 20 that executes interpolation calculation processing, and data to be interpolated from the data storage unit 10. Is input to the interpolation calculation processing unit 20 and input to the interpolation calculation processing unit 20 (input control circuit), and a calculation value output unit that outputs (stores) the interpolation data acquired by the interpolation calculation processing unit 20 to the data storage unit 10 40 (output control circuit).

  The interpolation calculation processing unit 20 includes an interpolation coefficient setting unit 22 that sets a sampling rate (interpolation coefficient) α, an initial position setting unit 24 that sets a sampling initial position β, and an output pixel number setting unit that sets the number n of output pixels. 26, and a resampling unit 28 (calculation unit) for obtaining a pixel value at the interpolation position based on the two pixels A and B to be interpolated, the sampling rate α, the sampling initial position β, and the output pixel number n.

  The resampling unit 28 includes an interpolation target data position calculation unit 29. The interpolation target data position calculation unit 29 divides the sampling rate α into a fixed fraction part of p bits and an integer part of q bits, and sets the sampling rate α as one step, k · α (2 · α, 3 · α, 4・ Calculate and hold α, 5 ・ α, ...) and repeated addition values.

  In the resampling unit 28, the sampling rate α is set by the interpolation coefficient setting unit 22, the initial sampling position β is set by the initial position setting unit 24, and the output pixel number n is set by the output pixel number setting unit 26. The resampling unit 28 performs linear interpolation to obtain pixel values from one point (C) to two (A, B) points adjacent (neighboring) in the digital image input from the interpolation target value input unit 30. To do.

  The interpolation target value input unit 30 acquires n-bit data (pixel values A and B) at the horizontal or vertical pixel position designated by the resampling unit 28 from the data storage unit 10 in a one-dimensional direction, and resampling unit 28. The calculation value output unit 40 repeats the operation of storing the calculation result at the designated address of the data storage unit 10 for the set number of pixels n, and finally the m obtained by the resampling unit 28. A pixel value C composed of bits is output to the data storage unit 10.

  At this time, the resampling unit 28 specifies the pixel positions of the input pixels A and B by the integer part of the calculation result of the interpolation target data position calculation unit 29 and notifies the interpolation target value input unit 30 of the coordinate data of the pixel positions. To do. Upon receiving this notification, the interpolation target value input unit 30 acquires the pixel data A and B of the coordinate data from the data storage unit 10 and passes them to the resampling unit 28.

  The resampling unit 28 obtains a calculation value C of the interpolation position by two-point interpolation processing based on the pixel data A and B of the coordinate data and the decimal part point (α) of the calculation result of the interpolation target data position calculation unit 29, and calculates The data is stored in the data storage unit 10 via the value output unit 40. As a result, digital images having different resolutions are stored in the data storage unit 10.

  Here, the interpolation calculation processing unit 20 uses point (α) which is a fixed decimal part of the sampling rate α, and performs linear interpolation by “C = (1−point (α)) · A + point (α) · B”. Do. At this time, an initial value is set so that the value of the decimal part point (α) does not become “0” in the minimum step unit of the fixed decimals in the decimal part point (α). In addition, when performing calculations according to linear interpolation, unlike Patent Document 3, the denominator of the decimal part point (α) of the interpolation coefficient α is set to 2 ^ n (power of 2), and division processing is executed by bit shift processing. To do.

<Basic concept of interpolation calculation>
FIG. 2 is a diagram for explaining the basic concept of the interpolation calculation performed by the interpolation calculation processing unit 20 (particularly the resampling unit 28). As an example of basic resampling, there is linear interpolation using two neighboring points. The resampling unit 28 of this embodiment also basically employs this method. When the sampling rate is α, the integer part is expressed as int (α) and the decimal part is expressed as point (α). The resampling value Resamp [i] by linear interpolation for the data string D [i] (i = 0, 1,..., N) is expressed by Expression (1).

  Resamp [i] = (1−point (α)) × D [int (α)] + point (α) × D [int (α) +1] (1)

   The wider the bit width of the decimal part point (α), the smaller the error from the ideal value and the better (high accuracy) signal processing can be realized. In the present embodiment, resampling processing that maintains accuracy is realized with a circuit-saving configuration. The precision means a fractional point (α) of the sampling rate α, and is, for example, 2 bits (1/4 = 0.25) or 5 bits (1/32 = 0.03125).

  In order to suppress the discretization error, the bit range should be large so that the fractional point (α) of the sampling rate α can be expressed as accurately as possible. When expressed in a binary number, for example, the sampling rate α can be expressed with 8 times the accuracy of 5 bits (1/32 = 0.03125) than 2 bits (1/4 = 0.25). The re-sampling with higher accuracy can be realized by using more bit ranges even with one bit.

  The step of the fractional point (α) of the sampling rate α is 1 / (power of 2), and the actual division processing is realized by the bit shift processing, so that a general divider is not required for the calculation at the subsequent stage. And The calculation accuracy increases as the bit width of the decimal part is increased. The calculation accuracy leads to a reduction in discretization error, and good resampling is realized.

<2-point linear interpolation calculation>
3-6 is a figure explaining the mechanism of the 2-point neighborhood linear interpolation calculation by the interpolation calculation process part 20 of this embodiment. Here, FIG. 3 is a diagram illustrating a configuration example of the resampling unit 28 of the present embodiment. FIG. 3A is a diagram illustrating a configuration example of a resampling unit 28Z of a comparative example that does not apply the two-point neighborhood linear interpolation calculation of the present embodiment. 4-5 is a figure explaining the method of specifying an interpolation position in the resampling units 28 and 26Z. FIG. 6 is a diagram for explaining a calculation method of the resampling value Resamp [i] in the resampling unit 28 of the present embodiment.

  The resampling unit 28 uses linear interpolation with two neighboring points as shown in FIG. 2 as the resampling method. When the integer part int (α) and the fractional part point (α) of the sampling rate α are used, the calculation is performed according to equation (2).

C = (1-point (α)) · A + point (α) · B (2)
In order to generate n pixels of output, the calculation of Expression (2) is repeatedly performed in cooperation with the calculation value output unit 40. At this time, using the interpolation target data position calculation unit 29 shown in FIG. 4 (1), the interpolation according to the equation (3) is performed based on the sampling rate α and the sampling initial position β as shown in FIG. 5 (1). The target coordinate ζ is obtained. The resampling unit 28 specifies the pixel positions of the input pixels A and B from the integer part of the calculation result. For example, when an integer part is int (ζ) and an arithmetic operator k (k is 1 to n), a two-point expression (a pixel A [int (ζ)] and a pixel B [int (ζ) +1] ( The pixel value C is specified by linear interpolation according to 2).

ζ = k · α + β (3)
As shown in Expression (3), the present embodiment is characterized in that, in acquiring the interpolation target coordinate ζ, the interpolation target coordinate ζ can be adjusted by using the sampling initial position β instead of ζ = k · α. There is. The purpose of setting the sampling initial position β is to adjust so that the value of the decimal point point (α) does not become “0” (zero). Even when Expression (3) is used, the pixel positions of the two points A and B to be interpolated are easily specified from the integer part int (ζ).

  For the data string D [i] (i = 0, 1,..., M) from the input control circuit, the resampling value Resamp [i] is expressed by Expression (4) (see FIG. 6).

  Resamp [i] = (1−point (ζ)) × D [int (ζ)] + point (ζ) × D [int (ζ) +1] (4)

  The sampling rate α and the initial sampling position β are 1 / (power of 2) in the fractional step, and a practical division process is realized by the bit shift process. Make it unnecessary. The larger the decimal bit width, the higher the calculation accuracy. The calculation accuracy leads to a reduction in discretization error, and good resampling is realized.

  However, the decimal bit width affects the scale of the two multipliers and the subsequent adder. For example, the interpolation calculation processing unit 20Z (ordinary resampling circuit) of the comparative example shown in FIG. 3A repeats sampling with “ζ = k · α” as shown in FIG. ), The decimal point point (ζ) can take the value “0”. Since point (α) can take the value “0”, it is necessary to expand “1-point (α)” to “the bit width of the fractional part + 1”, and a correspondingly useless circuit is required. For example, when the fractional bit width is 5 bits, “1-point (α)” is 6 bits.

  On the other hand, in the interpolation calculation processing unit 20 of the present embodiment, the resampling start position according to the equation (3) using the sampling initial position β so that the value of the decimal point point (ζ) does not become “0”. The point (ζ) is adjusted. By controlling the resampling start position point (ζ), the calculation result can be calculated with p bits with an accuracy equivalent to p + 1 bits without extending the bit width of “1-point (ζ)”. .

  That is, in the mechanism of the present embodiment, the decimal part point (α) is expressed by a real number that is a power of 2 (for example, 5/8 for 3 bits) in the circuit. Then, the resampling is repeated at step α, and the calculation is performed up to the necessary resampling value Resamp [n]. At this time, the start position of the fractional part point (α) is determined by using the sampling initial position β so that the value of the fractional part point (ζ) does not become “0” (zero). The bit width (decimal bit width: for example, 3 bits) is set to an integral multiple of the minimum step (1/8 for 3 bits). The set value of the sampling initial position β is within a finite range as a general concept in the field, that is, as long as the calculation is performed up to the necessary resampling value Resamp [n], excluding “0”, for example, 1/8 to 7 / 8 is set.

  When resampling is performed, there is a trade-off between the calculation accuracy that affects the discretization error, the circuit scale, and the processing scale. By taking the measures described above, resampling processing that maintains accuracy can be performed. Realized with reduced circuit configuration and reduced processing scale. For example, in a resampling process that is frequently used for scaling of video signal processing, an arithmetic processing method is realized that realizes a small area while maintaining the arithmetic accuracy. By the above-described countermeasures by the initial position setting unit 24, the sampling initial position β (sampling start point) can be arbitrarily set, and highly versatile sampling processing is realized. For example, a highly versatile interpolation operation function is realized, such as being suitable for applications such as high-precision center zoom.

<Example>
FIG. 7 is a diagram illustrating an embodiment. Here, the interpolation target data is 10 bits, and the decimal part point (α) is an example of 8 bits precision.

  As shown in FIG. 7A, in the case of the interpolation calculation processing unit 20Z of the comparative example, since sampling is repeated with “ζ = k · α”, point (ζ) can take a value “0”. To deal with this, when point (ζ) is a p-bit decimal, 1-point (ζ) needs to be expanded to a decimal p + 1 bit, and when the decimal bit width = 8 bits, “1-point ( α) "is 9 bits. 1-point (ζ) needs to be extended by 1 bit than point (ζ).

  Further, since the decimal bit width differs between point (ζ) and “1-point (α)” (there is a difference of 1 bit), the circuit layout cannot be made symmetric. Since arithmetic units having different bit widths are used, the symmetry of the circuit cannot be maintained, and the difficulty of layout becomes obvious. The same applies to the adder circuit after multiplication, and the input bit width is different, so that the layout disadvantages become apparent as in the multiplier.

  On the other hand, as shown in FIG. 7 (2), in the interpolation calculation processing unit 20 of the present embodiment, the resampling start position point (ζ) is set so that the value of the decimal part point (α) does not become “0”. It is controlled by the sampling initial position β. As a result, the fractional bit width = 8 bits is sufficient for both point (ζ) and “1-point (α)”. Resampling with high calculation accuracy is realized without extending the number of bits of the multiplier.

  In addition, since the same fractional bit width is sufficient for both point (ζ) and “1-point (α)”, an arithmetic unit having the same bit width can be used, and the symmetry of the circuit is maintained. As a result, the ease of layout is improved, and the circuit filling ratio with respect to the area is increased. Furthermore, the bit width of the adder circuit after multiplication is suppressed, and equivalent calculation accuracy can be obtained. In addition, since the input bit widths are uniform, a layout merit can be obtained as in the multiplier.

<Application to image equipment>
FIG. 8 is a diagram illustrating the image device of the present embodiment. The image device 7 of the present embodiment is obtained by applying the linear interpolation mechanism of the image processing apparatus 1 of the present embodiment described above to an image device. The image device 7 may be any device that performs various types of graphics processing such as enlargement / reduction processing such as resolution conversion and aspect conversion on a digital image represented by discretized digital data. An example is a solid-state imaging device, an imaging device, a copying device, or the like that uses a coupled device (CMOS) or a complementary metal-oxide semiconductor (CMOS) as an imaging device. In any case, the mechanism of the image processing apparatus 1 can be similarly applied to the image device 7 that performs resampling at a sampling rate different from the original.

  The illustrated image device 7 includes an image data acquisition unit 50 that acquires image data and stores the image data in the data storage unit 10 in addition to the components of the image processing apparatus 1. The basic operation of each functional unit of the image processing apparatus 1 is the same as that of the image processing apparatus 1 described above. For example, the interpolation coefficient setting unit 22 sets the sampling rate α (0 ≦ α ≦ 1), and the output pixel number setting unit 26 sets the output pixel number n (n is a positive integer of 1 or more).

  The resampling unit 28 specifies the coordinates of the two pixels to be interpolated according to ζ = k · α + β (k is 1 to n) as the initial position β, and the values A and B of the two pixels to be interpolated and the interpolation coefficient Based on α and the output pixel number n, the pixel value C at the interpolation position is obtained according to equations (1) to (4). Here, the initial position setting unit 24 uses the bits of the fractional part point (α) so that the value of the fractional part point (ζ) of ζ does not become zero in n computation steps in the computation process in the resampling unit 28. The sampling initial position β is set by an integral multiple of the minimum step of the width.

  As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. Various changes or improvements can be added to the above-described embodiment without departing from the gist of the invention, and embodiments to which such changes or improvements are added are also included in the technical scope of the present invention.

  Further, the above embodiments do not limit the invention according to the claims (claims), and all combinations of features described in the embodiments are not necessarily essential to the solution means of the invention. Absent. The embodiments described above include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. Even if some constituent requirements are deleted from all the constituent requirements shown in the embodiment, as long as an effect is obtained, a configuration from which these some constituent requirements are deleted can be extracted as an invention.

  For example, each component of the embodiment is not limited to being in the same housing. Furthermore, the specific means of each unit (including functional blocks) for realizing the series of processes described in the above embodiment is hardware or software or a combination of both, a combination using a network, and any other arbitrary These methods can be used, and this is obvious to those skilled in the art. Further, the functional blocks may be combined to form one functional block.

  When executing processing by software, install a program that records the processing sequence in a memory in a computer built in dedicated hardware and execute it, or install the program on a general-purpose computer that can execute various types of processing. Or run it. Various processes may be executed not only in time series in accordance with the description of the above-described embodiment, but also in parallel or individually as required by the processing capability of the apparatus that executes the processes.

It is a figure which shows the structural example of the image processing apparatus (image processing system) to which the image processing method which concerns on this invention is applied. It is a figure explaining the basic concept of an interpolation calculation. It is a figure which shows the structural example of the resampling part of this embodiment. It is a figure which shows the structural example of the resampling part of a comparative example. It is FIG. (1) explaining the method of specifying an interpolation position. It is FIG. (2) explaining the method of specifying an interpolation position. It is a figure explaining the calculation method of a resampling value. It is a figure which shows an Example. It is a figure explaining the imaging device of this embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Image processing apparatus, 10 ... Data storage part, 20 ... Interpolation calculation process part, 22 ... Interpolation coefficient setting part, 24 ... Initial position setting part, 26 ... Output pixel number setting part, 28 ... Resampling part (calculation part) 29 ... Interpolation target data position calculation unit, 30 ... Interpolation target value input unit, 40 ... Calculation value output unit, 50 ... Image data acquisition unit, 7 ... Image equipment

Claims (7)

An interpolation coefficient setting unit for setting the interpolation coefficient α (0 ≦ α ≦ 1);
An output pixel number setting unit for setting the output pixel number n (n is a positive integer of 1 or more);
Specify the coordinates of the two pixels to be interpolated according to the equation ζ = k · α + β (k is 1 to n) as the initial position β, the values A and B of the two pixels to be interpolated, the interpolation coefficient α, and A calculation unit for obtaining a pixel value C at an interpolation position based on the number n of output pixels according to the formula (X);
An initial position setting unit that sets the initial position β so that the value of the decimal part point (ζ) of the ζ does not become zero in the n number of calculation processes by the calculation unit;
An image processing apparatus.
C = (1-point (α)) · A + point (α) · B (X) The calculation unit sets the bit width of the decimal part point (ζ) to p bits,
The image processing apparatus according to claim 1, wherein the initial position setting unit sets an integer multiple of the p-bit minimum step unit as the initial position β. The calculation unit specifies the coordinates of the two pixels to be interpolated by int (ζ) and int (ζ) +1 based on the integer part int (ζ) of the ζ every time the n calculation processes are performed. The values A and B of two pixels to be interpolated are D [int (ζ)] and D [int (ζ) +1], and the pixel value C at the interpolation position [i] is obtained according to the equation (Y). 2. The image processing apparatus according to 2.
C = Resamp [i] = (1−point (ζ)) × D [int (ζ)] + point (ζ) × D [int (ζ) +1] (Y) The image processing apparatus according to any one of claims 1 to 3, wherein the arithmetic unit sets both the bit widths of the decimal parts point (ζ) and 1-point (ζ) to p bits. The interpolation coefficient α and the initial position β have a fractional step of 1 / (power of 2),
The image processing apparatus according to claim 1, wherein the arithmetic unit performs a division process by a bit shift process. A data storage unit for storing image data;
An image data acquisition unit for acquiring image data and storing the image data in the data storage unit;
An interpolation coefficient setting unit for setting the interpolation coefficient α (0 ≦ α ≦ 1);
An output pixel number setting unit for setting the output pixel number n (n is a positive integer of 1 or more);
As the initial position β, the coordinates of the two pixels to be interpolated are specified and read out from the data storage unit according to the formula ζ = k · α + β (k is 1 to n), and the values A and B of the two pixels to be interpolated are read out. A calculation unit that obtains a pixel value C at an interpolation position based on the interpolation coefficient α and the output pixel number n according to the equation (X) and stores the calculated value in the data storage unit;
An initial position setting unit that sets the initial position β so that the value of the decimal part point (ζ) of the ζ does not become zero in the n number of calculation processes by the calculation unit;
With imaging equipment.
C = (1-point (α)) · A + point (α) · B (X) An interpolation coefficient setting step for setting the interpolation coefficient α (0 ≦ α ≦ 1);
An output pixel number setting step for setting the output pixel number n (n is a positive integer of 1 or more);
An interpolation target coordinate specifying step of specifying the coordinates of two pixels to be interpolated according to the equation ζ = k · α + β (k is 1 to n) as the initial position β;
A calculation step of obtaining a pixel value C at an interpolation position according to the equation (X) based on the values A and B of the two pixels to be interpolated, the interpolation coefficient α, and the output pixel number n;
An initial position setting step of setting the initial position β so that the value of the fractional part point (ζ) of ζ does not become zero in n calculation steps in the calculation step;
An image processing method comprising:
C = (1-point (α)) · A + point (α) · B (X)

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