JP3475489B2 - Image printing device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image printing apparatus which performs image rotation, zigzag printing, and enlargement at an arbitrary enlargement ratio with a constant processing time with a simple circuit structure.

[0002]

2. Description of the Related Art Conventionally, when printing an image stored in an image memory, print data is created and print control is performed by an image processing apparatus as shown in the block diagram of FIG. To briefly explain this, the timing signal generating circuit 1 shown in the figure is a circuit which outputs a timing signal in an ON / OFF state and controls the operations of main scanning and sub scanning for creating print data. CPU (Central Proc
The essing unit 2 is a circuit that outputs information such as the enlargement ratio of the print image, the image cutout position, and the presence or absence of image rotation, and controls each unit. The address generation circuit 3 is a circuit that generates an address signal for sequentially reading a plurality of image data on the image memory 4 and supplies the address signal to the image memory 4. The image memory 4 is an image storage means 5 including a video signal processing circuit and the like.
Thus, it is a frame memory for storing digital image data converted from an analog video signal of a television, a video camera, a video deck, etc., and outputs the pixel data of the address supplied from the address generation circuit 3. The digital image data is composed of pixel data composed of a luminance signal Y and a color difference signal C. Synthesis processing circuit A (6)
Outputs a combined luminance signal Y ′ obtained by combining and calculating a plurality of pixel data (luminance signal Y) output from the image memory 4 based on a luminance combining parameter corresponding to the enlargement ratio output from the combining control circuit 7. The sharpness processing circuit 8
This is a circuit that reads a plurality of combined luminance signals Y ′, performs edge enhancement processing, and outputs a processed luminance signal Y ″. The combining processing circuit B (9) is a circuit for outputting a plurality of pixel data (color difference) output from the image memory 4. The signal C) is output as a composite color difference signal C'combined based on the color difference composition parameters corresponding to the enlargement ratio output from the composition control circuit 7. The image processing / printing control circuit inputs from the sharpness processing circuit 8. A circuit for performing print control by generating print data from the processed luminance signal Y ″ and the composite color difference signal C ′ input from the composite processing circuit B and outputting the print data to a printing unit (not shown).

[0003]

However, in the above-mentioned conventional configuration, various problems as described below occur during image printing.

That is, in order to enlarge and print an image, the address generating circuit and the synthesizing circuit each require a logic circuit for each enlargement ratio. These logic circuits have completely different configurations when the enlargement ratio is different, and when preparing a plurality of enlargement ratios, it becomes necessary to provide a plurality of circuits corresponding to the enlargement ratios for each of the address generation circuit and the synthesis circuit. . In addition, a control circuit for switching these circuits to operate becomes necessary. Therefore, there is a drawback that the circuit becomes complicated as a whole.

Further, in order to obtain a printed image that looks good, it is necessary to arrange the intervals between adjacent printed dots uniformly, that is, in a zigzag pattern. However, in order to perform such zigzag printing, the address generating circuit and the synthesizing circuit described above require separate address generating circuits and synthesizing circuits when the sub-scanning numbers are even and odd, respectively. Therefore, the circuit becomes more complicated, and problems increase in design, price, and size reduction.

Further, there is often a desire to print an image rotated by 90 degrees. By the way, since the image data has a large amount of data, a DRAM, which has a large storage capacity and is inexpensive as compared with the volume, is usually used for the image memory. In general, when reading data from a DRAM, a row address is designated, column addresses are sequentially shifted and read, and after reading one line of data, the row address is shifted and the next one line (row) is read, so-called first. Reading is typically done in page mode. This is a case where printing is performed without rotating the image data written in the DRAM, and high-speed reading is possible. However, when an image is rotated by 90 degrees for printing, the reading order from the DRAM must be different from that in the above method and the reading must be performed in a direction in which the image is rotated by 90 degrees. That is, first, the column address is designated, the row address is sequentially shifted, the first digit is read, and this is sequentially repeated for the second and third digits. This method is originally D
Since it is not suitable for reading the RAM, the print processing speed when rotated is significantly slower than when the rotation is not performed.

Next, the sharpness processing is performed after the synthesis processing. With this method, however, the range of the sharpness processing must be changed due to the difference in the enlargement ratio, and a separate memory for this is required. Need to.
This is because when the enlargement ratio is large, the data of the target dot after combining and the data of the surrounding dots are almost the same, so in order to perform effective sharpness processing, the data after combining of dots that are far from the target dot should be used. It depends on what needs to be used. That is, it is necessary to store a plurality of such data, and a memory is required accordingly. This causes not only the problem that the circuit is increased and the cost is increased, but also the problem that the processing time is not constant.

The object of the present invention is to solve the above-mentioned conventional problems.
An object of the present invention is to provide an image printing apparatus capable of performing image rotation, zigzag printing, and enlargement at an arbitrary enlargement ratio with a constant processing time with a simple circuit configuration.

[0009]

The structure of the image printing apparatus according to the present invention will be described below. First, the present invention is premised on an image printing apparatus that prints out image data.

The image printing apparatus of the present invention includes coordinate calculation means for calculating coordinates in a virtual coordinate space corresponding to the address space of the image memory, image data read from the image memory, and calculation results of coordinates by the coordinate calculation means. Image processing means for creating print data based on the virtual coordinate space
Is composed of virtual column coordinates and virtual row coordinates.
Is the virtual column initial value on the virtual coordinates, the virtual column interval, the virtual column
Line initial value, virtual line interval, read from the image memory
Image rotation when outputting image data as print data
Based on the presence / absence and the rotation angle when rotating the image
It is configured to perform coordinate calculations .

[0011]

Further, the coordinate calculation means is, for example, a request.
As described in Item 2 , at least the virtual column initial value and the virtual row initial value are used to determine the position of the print image on the image memory. Further, as described in claim 3 , for example, the enlargement ratio of the print image is determined by the virtual column interval and the virtual row interval. Furthermore, for example, as described in claim 4 , the initial value of the virtual coordinate in the main scanning direction is the initial value of the virtual coordinate in the main scanning direction between the main scanning in the even-numbered sub-scanning direction and the main scanning in the odd-numbered sub-scanning direction. It is configured to be set by shifting by 1/2.

Further, the image processing means is, for example, in the claims.
As described in 5, the pixel data of the image memory is configured to be printed out so as to be printed in the longitudinal direction or the lateral direction of the printing paper according to the presence or absence of image rotation. Also, for example
As described in claim 6, outline enhancement processing is performed on the output of the image memory to output a processed luminance signal, and the virtual column is output.
Based on the address and virtual row address
The print data is created by combining the frequency signals . Still further, for example, as described in claim 7 , the aspect ratio (vertical ratio) of one pixel of the image memory is represented by a ratio of a square root of an integer of one digit, and the virtual column interval and the virtual row by the image rotation are expressed. It is configured to set the ratio to the interval to be a one-digit integer ratio.

[0014]

According to the present invention, the coordinate calculation means calculates the coordinates in the virtual coordinate space corresponding to the address space of the image memory, and the image processing means reads the image data from the image memory and the coordinate calculation result by the coordinate calculation means. virtual line creates print data, the virtual coordinate space and the virtual column coordinates based on
The coordinates on the virtual coordinates.
Virtual column initial value, virtual column interval, virtual row initial value, virtual row interval
Image data read from the image memory.
Whether to rotate the image when outputting it as a data, and the image rotation
The coordinate calculation is performed based on the rotation angle when performing .

The coordinate calculating means determines the position of the print image on the image memory by at least the virtual column initial value and the virtual row initial value, and determines the enlargement ratio of the print image by the virtual column interval and the virtual row interval. Further, the initial value of the virtual coordinate in the main scanning direction is set to be shifted by ½ of the virtual coordinate interval in the main scanning direction between the even-numbered main scanning in the sub-scanning direction and the odd-numbered main scanning in the sub-scanning direction.

Further, the image processing means prints out the pixel data of the image memory so as to print in the longitudinal direction or the lateral direction of the printing paper according to the presence / absence of image rotation, and performs edge enhancement processing on the output of the image memory. Go and processed luminance signal
Based on the virtual column address and virtual row address
The print data is created by synthesizing the processed luminance signal, and the aspect ratio (vertical ratio) of one pixel in the image memory is represented by the ratio of the square root of a one-digit integer. And the virtual line spacing are set to be a one-digit integer ratio.

Thus, the rotation of the image, the zigzag printing, and the enlargement at an arbitrary enlargement ratio can be performed with a constant processing time with a simple circuit configuration.

[0018]

Embodiments of the present invention will be described in detail below with reference to the drawings. In the following description, printing and printing are used synonymously.

FIG. 1 is a block diagram of an image printing apparatus according to an embodiment. In the figure, a timing signal generation circuit 1
Reference numeral 1 outputs various state timing signals of ON or OFF to control the operation of main scanning and sub-scanning for creating print data.

The CPU 12 has a ROM (Read Only Memory) (not shown) storing a system program,
A sequence signal is output based on the system program read from the ROM to control the sequence of the mechanical portion. In addition, the user interface is controlled to input key input from an input panel (not shown), other operation signals, etc. and to notify the necessary information to the outside. The input information from the outside such as the presence or absence of rotation is recognized, and based on this recognition, the following virtual column generation circuit 13 and virtual row generation circuit 1
4, rotation instructions, initial values of virtual columns and virtual rows, intervals between virtual columns and virtual rows are set, and further, the number of main scans, the number of sub-scans, etc. are set in the timing signal generation circuit 11 described above. Then, each unit is instructed to start the printing operation. In addition, CP
U12 does not directly handle the processing of the image data itself by leaving it to each processing circuit described below.

The virtual column generation circuit 13 is a combinational circuit,
A virtual column coordinate value "b" composed of an adder, a 16-bit register, etc. and composed of the most significant bit b15 to the least significant bit b0.
15-b0 "is output. The virtual row generation circuit 14 is also composed of a combination circuit, an adder, a 15-bit register, etc., and outputs virtual row coordinate values “b14 to b0” composed of the most significant bit b14 to the least significant bit b0.

The address generation circuit 15 operates the image memory 1 of an address corresponding to the virtual column coordinate value and the virtual row coordinate value.
An address signal for sequentially reading a plurality of image data on 6 is generated and supplied to the image memory 16.

The image memory 16 has a frame memory composed of, for example, 2 MB (megabytes), and stores image data at the address designated by the address generation circuit 15 of this frame memory.

The image storage means 17 is composed of, for example, a video signal processing circuit, etc., and separates an analog video signal input from a television, a video camera, a video deck, etc. into a luminance signal and a color difference signal, for example, 8 bits per dot. Of the luminance signal Y and the color difference signal C of 6 bits per 2 dots, and the converted digital signal, that is, image data is output to the image memory 16.

The sharpness processing circuit 18 reads a plurality of luminance signals Y, performs edge enhancement processing, and outputs a processed luminance signal Y. The synthesis processing circuit A (19) converts the plurality of luminance signals Y input from the sharpness processing circuit 18 into
The composite luminance signal Y'composed of a composite operation signal based on the virtual column address input from the virtual column generation circuit 13 and the virtual row address input from the virtual row generation circuit 14 is output.

The synthesis processing circuit B (20) is used in the image memory 1
A composite color difference signal composed of signals obtained by performing a composite operation on a plurality of pixel data (color difference signal C) output from the reference numeral 6 based on a virtual column address input from the virtual column generation circuit 13 and a virtual row address input from the virtual row generation circuit 14. Output C '.

The image processing circuit of the image processing circuit / printing control circuit 21 includes a hue adjustment circuit for adjusting image quality, a contrast adjustment circuit, a brightness adjustment circuit, a color correction processing circuit for color printing, and a gamma correction processing circuit. , A color masking processing circuit for printing by color, etc., and generates print data based on the luminance signal Y ′ input from the combining processing circuit 19 and the combined color difference signal C ′ input from the combining processing circuit B. On the other hand, the print control circuit includes a data conversion circuit that repeatedly transmits print data, a clock, a strobe signal, etc. to a printing device (printing unit 22 described later), an environmental temperature correction circuit, a power supply voltage drop correction circuit, and the like. Part 2
2 controls image printing. These image processing circuit and print control circuit operate in synchronization with the mechanical section sequence control by the CPU 12.

The printing section 22 is provided with a print head (thermal head) composed of heating elements arranged in a line in the main scanning direction (lateral direction of paper). This thermal head is fixed to a support member of the main body device, and performs printing in the main scanning direction at one time while feeding the paper in the sub scanning direction (the longitudinal direction of the paper). The array pitch of the above heating elements is approximately 1
25 μm (microns), which corresponds to a pixel density of approximately 8 dots per mm (millimeter).

In the present embodiment, the image processing circuit / printing control circuit 21 selectively causes the even-numbered heating elements of the thermal head to generate heat when printing one line of main scanning in which the sub-scanning is even. On the other hand, in the printing of one line of main scanning in which the sub-scanning is odd, the odd-numbered heating elements are selectively heated. That is, the even-numbered and odd-numbered heating elements are alternately caused to generate heat corresponding to the main scanning in the even-numbered and odd-numbered sub-scans. Then, the ink of the ink ribbon is transferred to the paper by the thermal energy of the heating element that is heated while the ink ribbon having the width substantially the same as the width of the paper is overlapped on the paper and moved in the sub-scanning direction, and one-line main scanning is performed. At the same time (once). At this time, as will be described later in detail, the paper feed amount (one sub-scanning distance) is controlled so that the print pixels are arranged in a zigzag pattern on the paper.

When the print pixels are printed in a zigzag pattern in this manner, the heat generating elements alternately generate heat, so that the thermal history of the heat generating elements can be easily corrected, and all the adjacent pixels are evenly spaced. Since it is arranged in, a printed image with good color can be obtained.

The ink ribbon used for the above printing has three colors of subtractive primary colors of yellow (yellow), magenta (red dye) and cyan (blue with a greenish tint), and black dedicated to printing characters ( (Black) are sequentially arranged in the longitudinal direction of the base film, and an ink ribbon having a shape in which a set of four colors is repeatedly applied is used. Of course, when printing only the image without printing the characters, ribbons of three colors of yellow, magenta, and cyan may be used.

The density gradation of the print pixels is obtained by the area gradation method which controls the area of the ink occupied in one print dot.
Expressed in 8 gradations. This is performed by controlling the thermal energy of the heating element in 128 steps in time and changing the spread of the transfer ink within the maximum coloring range of one print dot in a concentric manner.

Although not particularly shown, the key input section is C
It is connected to the PU 12, and a power key for turning the power on / off, a memory key for loading a desired video image into the image memory 16, a print setting key for setting color, brightness, etc., and an instruction for enlarging (or reducing) the image. Enlarge key, rotate image (90
Various input keys such as a rotation key for instructing rotation start and a print start key for instructing printing start are provided. CPU1
2 performs processing based on the instruction of the input signal from these input keys.

2A and 2B show a logical address space (hereinafter referred to as a physical address space) corresponding to a physical real address of the image memory 16.
3 shows the relationship between the image memory address space) and the virtual coordinate space in this embodiment. The image memory address space shown in FIG. 9A has column addresses “0” to “2 ⁹ −1” (0 to 511) represented by 9-bit (b8 to b0) values with the upper left of the image data as the origin. Row address "0" represented by 8-bit value (b7 to b0)
"2 ⁸ -1" (0 to 255). That is, the column addresses 0 to 511 of the image memory address space
Increases from the left end to the right end of the image data, and the row addresses 0 to 255 increase from the upper end to the lower end of the image data. That is, if the scales of the address coordinate axes are the same vertically and horizontally, the address space is horizontally long.

Corresponding to this, the virtual coordinate space shown in FIG. 6B is a virtual column coordinate represented by a value of 16 bits (b15 to b0) "0" to "2 ¹⁶ -1" and 15 bits (b14 to b0).
virtual row coordinates “0” to “2 ¹⁵ − represented by the value of b0)
1 ”, and similarly, the upper left of the coordinate space is the origin. Therefore, also in this case, the virtual column coordinate value increases from the left end to the right end, and the virtual row coordinate value increases from the upper end to the lower end.

The above virtual coordinate space has 16 bits (b1
The upper 9 bits (b15 to b) of the virtual column coordinates of 5 to b0)
7) indicates the column address of the image memory address space, and the upper 8 bits of the virtual row coordinates of 15 bits (b14 to b0).
Bits (b14 to b7) indicate the row address of the image memory address space.

FIG. 3 shows the correspondence relationship between the image memory address space and the virtual coordinate space in more detail. In the figure, a part of the virtual coordinate space is enlarged and shown. The intersections of the thick solid lines shown by the black dots in the figure are the upper 9 bits (b15
To b7) column coordinates "X-1", "X", "X +"
1 ”,“ X + 2 ”, and the upper 8 bits (b1
Row coordinates "Y-1", "Y", and "Y" indicated by 4 to b7).
A virtual coordinate space composed of "+1" and "Y + 2" is shown. This virtual coordinate space corresponds to the image memory address space as described above, and the symbols a, b, c ... N, o, p assigned to the intersection coordinates (black points) in the figure are the image memory. Image data (luminance signal Y) in the address space is shown. Also, the thin solid line indicates the column coordinates indicated by the lower 6th to 4th 3 bits (b6 to 4b) of the virtual column coordinates and the lower 6th to 4th 3 bits (b6) of the virtual row coordinates.
4b) and the row coordinates shown in FIG. The image data corresponding to the virtual coordinate space indicated by the thin solid line, for example, Q is created by combining the dots in FIG.

FIGS. 4A and 4B show the synthesizing process and
It is a figure explaining the sharpness process performed before this synthetic | combination process. These processes are processed by the sharpness processing circuit 18 and the composition processing circuits A and B in FIG. FIG. 4 (a) is a part reprinted around the point Q in FIG. 3, and FIG. 4 (b) is the lower 4 bits of the virtual column (virtual column b3).
~ B0) and the lower 4 bits of the virtual row (virtual columns b3 to b3)
0) coordinate space (hereinafter referred to as range A).

In the figure (a), the point Q is inside the pixel data f, g, j, k of the image memory. In order to obtain the combined data of the point Q, first, for the combination, the sharpness processing calculation is performed at each position of the pixel data f, g, j, k of the image memory, and the sharpened data F, G, Get J and K. However, the positions of the data F, G, J, and K after the sharpness processing are the same as the positions of the pixel data f, g, j, and k of the image memory, respectively. The sharpness processing circuit 18 in FIG. 1 performs the following calculations to obtain the data F, G, J, K after the above sharpness processing.

F = f + α (4f-b-e-g-j) G = g + α (4g-c-f-h-k) J = j + α (4j-f-i-k-n) K = k + α (4k -G-j-l-o) where α is a variable representing the sharpness level, and 0 to
Take a value of 1.

Pixel data necessary for performing these series of calculations are b, c, e, and the like in the pixel data shown in FIG.
There are 12 pixels of f, g, h, i, j, k, l, n, and o. The address generation circuit in FIG. 1 is for sequentially supplying a plurality of address information for obtaining the data of these 12 pixels to the pixel memory. That is, when the upper 9 bits of the virtual column (virtual columns b15 to b7) are x and the upper 8 bits of the virtual row (virtual rows b14 to b7) are y, b
(Y-1, x), c (y-1, x + 1), e (y, x-
1), f (y, x), g (y, x + 1), h (y, x +
2), i (y + 1, x-1), j (y + 1, x), k
(Y + 1, x + 1), l (y + 1, x + 2), n (y +
2, x) and o (y + 2, x + 1) pixel data are sequentially read from the image memory. However, f here
(Y, x) represents pixel data f addressed by a row address y and a column address x.

After the above sharpness processing is performed, the synthesizing processing circuit A (19) in FIG. 1 receives the data of these four points F, G, J, and K after the sharpness processing as input,
The following composite calculation is performed to obtain the data of the point Q which is the composite luminance output Y '.

U = F (8-β) / 8 + J (β / 8) =
{F (8-β) + J · β} / 8 V = G (8-β) / 8 + K (β / 8) = {G (8-β)
+ K · β} / 8 Q = U (8−γ) / 8 + V (γ / 8) = {U (8−γ)
+ V · γ} / 8 where β is bit 6 to bit 4 of the virtual row (virtual row b6 to
b4) is a synthesis parameter in the virtual row direction that takes values from 0 to 7, and γ is a virtual column direction that takes values from 0 to 7 in bits 6 to 4 of the virtual column (virtual columns b6 to b4). Is a synthetic parameter of.

Virtual columns and rows of the virtual coordinate space are shown in FIG. 4 (b).
When pointing to the point X on the virtual coordinates (the coordinate point of the minimum unit in the virtual coordinate space) shown in, the synthetic data adopts the data of the point Q. This means that all the data in the range A of FIG. 4 (b) is replaced with the data of the point Q. The reason is that even if the data of the point Q is adopted as the data of all the points in the range A, the necessary and sufficient accuracy for the quality of the print output can be obtained.

In general, the composition is performed by the method shown in FIG. The synthesis will be further described with reference to FIG.
In the figure, image data a, b, and
The method for obtaining the data q at the point q when there are c and d is as follows. The image data a, b, c,
d and the composite data q correspond to the image data F, G, J, K after the sharpness processing and the composite data Q in FIG.

In FIG. 5, the point a and the point b are divided into n,
The X address between the points a and b is set to 0, 1, 2 to n, the point a to the point c is divided into m, and the Y address between the points a and c is set to 0, 1, 2 to m, and X is set. Data having an address of x and a Y address of y is represented by p [x, y].

First, when points i and j are placed as shown in the figure, the data i and j at those points are i = p [x, 0] = a (n-x) /n+b.x/n j = p [x, m] = c (n−x) / n + d · x / n, from which the data q at the point q is q = p [x, y] = i (m−y) / m + j · It is obtained in y / m 2. Here, n = 8, m = 8, 0 ≦ x ≦ 7, 0
If ≦ y ≦ 7 (where x and y are both integers), the data i, j, and q are i = p [x, 0] = {a (8−x) + b · x} / 8 j = p, respectively. [X, 8] = {c (8−x) + d · x} / 8 q = p [x, y] = {i (8−y) + j · y} / 8. The intermediate data i and j correspond to the data U and V in FIG. 4A (where the coordinates X and Y are the same as those in FIG. 5).
And in Fig. 4 (a) they are replaced). The formulas for calculating the data U, V, and Q in FIG. 4A described above are based on the above general formula.

Further, the above three expressions can be transformed into the following three expressions. That is, i = (a + i ₀ + 2i ₁ + 4i ₂ ) / 8 j = (c + j ₀ + 2j ₁ + 4j ₂ ) / 8 q = (i + q ₀ + 2q ₁ + 4q ₂ ) / 8 where i _n , j _n , and q _n (n = 0, 1, 2) takes the values shown in the charts of FIGS. 6 (a) and 6 (b) according to x and y.

FIG. 7 shows a sequential circuit of the synthesis processing circuit A (19) which performs an operation based on these expressions. In the figure, multiplexers 31, 32, and 33 are signals (data) input to input terminals 0, 1, and 2 based on a 2-bit control signal s input to a selection signal terminal s.
Is selected, and the selected data is output from the output terminal Y. The 8-bit image data a and c and the fed back 8-bit intermediate composite data v are input to the input terminals 0, 1 and 2 of the multiplexer 31, respectively. Also,
Similarly, 8-bit image data b and d and fed-back 8-bit intermediate synthetic data u are input to the input terminals 0, 1, and 2 of the multiplexer 32, respectively. Then, 3-bit address data x and y are input to the input terminals 0 and 1 of the multiplexer 33, respectively. The address data x and y correspond to the middle 3 bits (b6 to b4) of the virtual column and the middle 3 bits (b6 to b4) of the virtual row described in FIG. 4A, respectively.

The multiplexers 34, 35 and 3 described above
Reference numeral 6 denotes the multiplexer 3 based on the address data w input from the multiplexer 33 to the selection signal terminal s.
Data to be input to the input terminals 0 and 1 are selected from 1 and 32, and the selected data is output from the output terminal Y.

The bit shifter 37 includes a multiplexer 36.
1 under the least significant bit of 8-bit data input from
Bit "0" is added, that is, 9-bit data obtained by doubling the input data is output. The adder 38 adds the input data from the multiplexer 31 to the input data from the multiplexer 31 and outputs 9-bit data. The adder 39 adds the input data from the multiplexer 35 to the input data from the bit shifter 37 to obtain 10
Outputs bit data.

The bit shifter 40 outputs 11-bit data obtained by doubling the input data by adding 1-bit "0" under the least significant bit of the 10-bit data input from the adder 39. The adder 41 adds the input data from the adder 38 to the input data from the bit shifter 40 and outputs the result. The bit shifter 42 takes out the upper 8 bits of the 11-bit data input from the adder 41, that is, outputs the input data as ⅛. The output of the bit shifter 42 is input to the latch 43. Latch 4
3 is composed of eight DFFs, the output of which is input to the latch 44 and fed back to the input terminal 2 of the multiplexer 32. The latch 44 is also composed of eight DFFs, and its output is the multiplexer 3
1 input terminal 2 is fed back.

FIG. 8 is a timing chart for explaining the operation of the sequential circuit having the above configuration. In the figure, in the control signal s having the 2-bit configuration described above, the upper bits are s.
1, the lower bit is s0. This control signal s
Becomes "0" at timing T0, "1" at timing T1 and "2" at timing T2 (FIG. 8).
(See (b)). The clock signal ck is a synchronous clock, and the rising edge of this clock signal ck (see FIG. 8 (a)).
(See r1, r2, r3) of FIG. Below, referring to the time chart of FIG.
The operation of the sequential circuit of FIG. 7 will be described.

First, at timing T0, the control signal s = 0 (see FIGS. 8 (b), 8 (c) and 8 (d)). This signal s
= 0, the multiplexer 31 selects and outputs the data a, the multiplexer 32 selects and outputs the data b, and the multiplexer 33 selects the address data x and outputs it as the output w (FIG. 8 (e), (See (f) and (g)).

The 3-bit value "0" (000),
"1" (001), "2" (010), "3" (01
1), "4" (100), "5" (101), "6"
It is assumed that the most significant bit of the address data x taking (110) and “7” (111) is w2, the central bit is w1, and the least significant bit is w0. These bit data w0, w
1 and w2 are input to the selection signal terminals of the multiplexers 34, 35 and 36, respectively.

The multiplexer 34 selects the input data a, b according to the least significant bit w0 of the address data x input to the selection signal terminal. That is, when the bit w0 is "0", that is, the address data x is "0", "2",
When either "4" or "6", the data a is selected and output, and when the bit w0 is "1", that is, the address data x is "1", "3", "5", "7". In either case, the data b is selected and output. This is the data i ₀ in the chart (Table 1) shown in FIG. 6 (a) (see also FIG. 8 (h)).

Similarly, the multiplexer 35 selects the input data a, b according to the central bit w1 of the address data x input to the selection signal terminal. That is, the bit w1 is "0"
, That is, when the address data x is “0”, “1”,
When either "4" or "5", the data a is selected and output, and when the bit w1 is "1", that is, the address data x is "2", "3", "6", "7". In either case, the data b is selected and output. This is i ₁ in the chart (Table 1) shown in FIG. 6 (a) (see also FIG. 8 (i)).

Further, similarly, the multiplexer 36 uses the most significant bit w2 of the address data x input to the selection signal terminal.
The input data a and b are selected by. Multiplexer 3
6 outputs the data a when the bit w2 is "0", that is, when the address data x is "0", "1", "2", or "3", and the bit w2 is "0". 1 ”, that is, the address data x is“ 4 ”,“ 5 ”,
When either "6" or "7", the data b is selected and output. This is i ₂ in the chart (Table 1) shown in FIG. 6 (a).
(See also Fig. 8 (j)).

Then, the bit shifter 37 displays "2i₂"
And the adder 38 outputs "a + i₀Is output, and the adder 3
9 is "i₁+ 2i₂Is output, and the bit shifter 40
"2i ₁+ 4i₂Is output, and the adder 41 outputs “a + i₀
+ 2i₁+ 4i₂, And the bit shifter 42
Is "(a + i₀+ 2i₁+ 4i₂) / 8 ”
“I” is output (see FIGS. 8 (k) to 8 (p)).

The latch 43 stores the output i of the bit shifter 42 at the rising edge r1 of the clock ck (FIG. 8).
(See (q)). Next, at timing T1, the control signal s = 1 (see FIGS. 8 (b), (c), and (d)). With this signal s = 1, the multiplexer 31 selects and outputs the data c, the multiplexer 32 selects and outputs the data d, and the multiplexer 33 continues to output the address data x (FIGS. 8E, 8F). ), (g)).

In the multiplexer 34, the least significant bit w0 of the address data x input to the selection signal terminal is "0".
(Address data x is "0", "2", "4", "6"
In either case), the data c is selected and output, and the bit w
0 is “1” (address data x is “1”, “3”,
When either "5" or "7"), the data d is selected and output. This is the data j ₀ in the chart (Table 1) shown in FIG. 6 (a) (see also FIG. 8 (h)).

Similarly, in the multiplexer 35, the central bit w1 of the address data x input to the selection signal terminal is "0" (the address data x is "0", "1", "4",
When it is "5", the data c is selected and output, and the bit w1 is "1" (address data x is "2",
When any of "3", "6", and "7"), the data d is selected and output. This is j ₁ in the chart (Table 1) shown in FIG. 6 (a) (see also FIG. 8 (i)).

Further, similarly, the multiplexer 36 has the most significant bit w of the address data x input to the selection signal terminal.
2 is “0” (address data x is “0”, “1”,
When it is "2" or "3"), the data c is selected and output, and the bit w2 is "1" (the address data x is "4", "5", "6", or "7"). Or), the data d is selected and output. This is j ₂ in the chart (Table 1) shown in FIG. 6 (a) (see also FIG. 8 (j)).

Then, the bit shifter 37 outputs "2j₂",
The adder 38 uses “c + j₀, And the adder 39 uses “j₁+ 2j
₂, The bit shifter 40 reads "2j₁+ 4j₂], Adder
41 is “c + j₀+ 2j₁+ 4j₂], And Bitsiff
Data 42 is "(c + j₀+ 2j ₁+ 4j₂) / 8 ”
Output "j" respectively (See Fig. 8 (k)-(p) for the above.
See).

At the rising edge r2 of the clock ck, the latch 43 transfers the data i stored until then to the touch 44 and newly stores the output j of the bit shifter 42 (FIGS. 8 (q), (r )).

Immediately after the rising edge r2 of the clock ck, the output u of the latch 43 and the output v of the latch 44 are
U = (c + j ₀ + 2j ₁ + 4j ₂ ) / 8 =
j, and v = (a + i ₀ + 2i ₁ + 4i ₂ ) / 8 = i,
And input to the input terminals 2 of the multiplexers 32 and 31, respectively.

Then, at the next timing T2, the control signal s = 2 (see FIGS. 8 (b), (c) and (d)), and the multiplexer 31 outputs the output v of the latch 44 at this signal s = 2. , I is selected and output, the multiplexer 32 selects and outputs the output u of the latch 43, that is, j, and the multiplexer 33 outputs address data y (FIG. 8 (e),
(See (f) and (g)).

In the multiplexer 34, the least significant bit w0 of the address data y input to the selection signal terminal is "0".
(Address data y is "0", "2", "4", "6"
In either case), data i is selected and output, and bit w
0 is “1” (address data x is “1”, “3”,
When either "5" or "7"), the data j is selected and output. This is the data q ₀ in the chart (Table 2) shown in FIG. 6 (b) (see also FIG. 8 (h)).

Similarly, in the multiplexer 35, the central bit w1 of the address data y input to the selection signal terminal is "0" (the address data y is "0", "1", "4",
When it is "5", the data i is selected and output, and the bit w1 is "1" (address data y is "2",
When any of "3", "6", and "7"), the data j is selected and output. This is q ₁ in the chart (Table 2) shown in FIG. 6 (b) (see also FIG. 8 (i)).

Further, similarly, the multiplexer 36 outputs the most significant bit w of the address data y input to the selection signal terminal.
2 is “0” (address data y is “0”, “1”,
When it is "2" or "3"), the data i is selected and output, and the bit w2 is "1" (the address data y is "4", "5", "6", or "7"). Or), the data j is selected and output. This is q ₂ in the chart (Table 2) shown in FIG. 6 (b) (see also FIG. 8 (j)).

Then, the bit shifter 37 outputs "2q₂",
The adder 38 uses “c + q₀, And the adder 39 displays “q₁+ 2q
₂, And the bit shifter 40 is "2q₁+ 4q₂], Adder
41 is “i + q₀+ 2q₁+ 4q₂], And Bitsiff
42 is “(i + q₀+ 2q ₁+ 4q₂) / 8 ”
Output "q" respectively (See Fig. 8 (k)-(p) for the above.
See).

The latch 43 stores the output q of the bit shifter 42 at the rising edge r3 of the clock ck (see FIG. 8).
(See (q) and (r)). Immediately after the rising edge r3 of the clock ck, the output u of the latch 43 is u = (i + q ₀ +2
q ₁ + 4q ₂ ) / 8 = q. The latch 43 outputs this data q as combined processing data u. This is the output of the synthesis processing circuit A (or B). In this way, the composited data based on the image data in the image memory address space can be obtained at any coordinate position in the virtual coordinate space. The image processing circuit / printing control circuit 21 in FIG. 1 creates print data for printing based on the combined image data in the virtual coordinate space. In the present embodiment, the print image based on this print data is printed in two modes: "no rotation instruction" and "rotation instruction".

FIG. 9A shows the printing state when there is no rotation instruction, and FIG. 9B shows the printing state when there is rotation instruction. When there is this rotation instruction, the image data when there is no rotation instruction is 90% counterclockwise.
Printed in a rotated state.

As shown in the figure, the printing surface of the paper is in a horizontally long state, and the vertical and horizontal directions thereof correspond to the vertical and horizontal directions of the image data. In actual print output, the main scanning of the printing operation is performed in the width direction of the paper (vertical direction in the drawing), and the sub-scanning (paper feeding) of the printing operation is performed in the longitudinal direction of the paper (horizontal direction in the drawing).

Therefore, as shown in FIG. 8A, when there is no rotation instruction, the read main scanning direction of the image data read in accordance with the main scanning direction of the printing operation is the image memory address space when the print data is created. Similarly, the sub-scanning direction is from left to right in the image memory address space. That is, the direction of the main scanning direction of the image data reading is opposite to the row coordinate of the image memory address space, and thus the direction of the virtual row coordinate of the virtual coordinate space. Similarly, the direction of the sub scanning direction is the column of the image memory address space. Coordinates, and hence the orientation of the virtual column coordinates.

When there is a rotation instruction as shown in FIG. 6B, the read main scanning direction of the image data read in accordance with the main scanning direction of the printing operation is the left side of the image memory when the print data is created. To the right, and the sub-scanning direction is from top to bottom. That is, the orientation in the main scanning direction is the same as the orientation in the virtual column coordinates, and the orientation in the sub-scanning direction is also the same as the orientation in the virtual row coordinates.

FIG. 10 shows the correspondence between the pixels of the print image and the virtual coordinates when there is no rotation instruction in the print image. Hereinafter, an example will be described in which the aspect ratio (vertical / horizontal ratio) of the print image is kept constant, that is, the print image is not vertically or horizontally long with respect to the image source.

As described above, when there is no rotation instruction, it is virtual
The main scanning direction for the coordinates is from bottom to top, and the sub-scanning direction
The direction is from right to left. Therefore, the user interface
Image memory address based on the setting by input from
The pixel in the lower left corner of the image data area cut out from space
The virtual coordinate 51 corresponding to
An initial value as a scanning address is set in the mark 51. here
Image data in the main scanning direction from the origin 51 to the sub scanning number.
No. 0 is data a in the main scanning direction₀, B₀, C ₀,
d₀, ..., in the main scanning direction of the next sub-scan number 1
A₁, B₁, C₁, D₁,,,,, the next sub-scan number
Data a in the main scanning direction of No. 2₂, B₂, C ₂, D₂,
...

The line spacing and the column spacing of the virtual coordinate space corresponding to the pixel data arrangement of these print images are automatically determined by the maximum number of print pixels in the print main scanning direction and the print sub scanning direction if the image enlargement ratio is determined. Takes a fixed value.

By the way, as shown in the figure, in the present embodiment, when scanning in the virtual coordinate space, when the main scanning is started when the sub-scanning number is an even number (including 0), the "virtual row initial value" is displayed in the virtual row. , ”And then subtracts the virtual line interval as the main scan progresses. As a result, from the bottom to the top, the main scan is data a ₀ , b ₀ , c ₀ , d ₀ , ... And when the next sub-scan number is an even number, the main scan is data a ₂ ,
b ₂ , c ₂ , d ₂ , ...

On the other hand, when the sub scanning number is an odd number, the main scanning is opened.
At the beginning, "virtual row initial value-virtual row interval / 2" is added to the virtual row.
substitute. And after that, in the same way as the main scanning progresses
Subtract the virtual line spacing. This is the main from bottom to top
Scan is data a₁, B₁, C ₁, D₁,,, next
Data a when the sub-scan number of is odd₃, B₃, C₃, D
₃, ... and so on.

Further, the "virtual column initial value" is assigned to the virtual column at the start of the sub scanning, and thereafter the virtual column interval is added in accordance with the progress of the sub scanning. As a result, sub scanning is performed from left to right. Therefore, the virtual line coordinates of the main-scan print dots having an even sub-scan number and the main-scan print dots having an odd sub-scan number are displaced by "virtual line interval / 2". As a result, printing of each pixel of the print image is performed in a zigzag manner when viewed vertically or horizontally (image data b in the figure).
₂ , b ₃ , c ₂ , c ₃ , d ₂ and d ₄ , c ₅ , d ₆ ,
See sequence of c _7, d _8). Further, as a result, in the present embodiment, the arrangement of the adjacent print pixels is uniform in any direction,
That is, the line connecting the adjacent print pixels is arranged so as to draw an equilateral triangle. As a result, no matter which print pixel is picked up (excluding the pixels at the upper and lower ends and both side ends), the line connecting the print pixels adjacent to it forms a regular hexagon (centering on the image data b _{8 in the} figure). Image data a ₇ , a ₉ ,
See sequence of _{b 6, b 8, b 10} , b 7, b 9). In this way, by arranging the print dots uniformly in a zigzag pattern, it is possible to obtain a print image with good color development.

The image data of these virtual row coordinates (image data after the above-mentioned composition processing) correspond to the even-numbered and odd-numbered heating elements of the print head of the printing unit 22 shown in FIG. 1, respectively. During printing, the even-numbered and odd-numbered heating elements of the print head alternately generate heat depending on whether the print dot and the main scan in which the sub-scan number is even or the main scan in odd. This facilitates the thermal history correction of the print data applied to the heating element.

Next, FIG. 11 shows a correspondence relationship between pixels of the print image and virtual coordinates when the print image has a rotation instruction. As described above, when there is a rotation instruction, the main scanning direction with respect to the virtual coordinates is from left to right and the sub scanning direction is from top to bottom. Therefore, in this case, the virtual coordinate 52 corresponding to the pixel at the upper left corner of the image data area cut out from the image memory address space based on the setting by the input from the user interface is set as the scanning origin, and the virtual coordinate 52 is scanned. Set the initial value as an address. Also in this case, the image data in the main scanning direction is set to the origin 52.
From the sub-scan number 0 to the main scanning direction data a ₀ ,
b ₀ , c ₀ , d ₀ , ..., Data a ₁ , b ₁ , c ₁ , d ₁ , ... In the main scanning direction of the next sub-scanning number ₁ , and the next sub-scanning number 2 Data a ₂ , b ₂ , in the main scanning direction of
It is assumed that they are c ₂ , d ₂ , ... (These are the same symbols as in the case of FIG. 10, but the data a ₀ , b _{0 of} FIG.
..., a ₁ , b _1, ..., A ₂ , b ₂ ... Are different in position and value).

Also in this case, the row spacing and the column spacing in the virtual coordinate space corresponding to the pixel data arrangement of these print images are the maximum number of print pixels in the print main scanning direction and the print sub-scanning direction if the enlargement ratio of the image is determined. Takes a value automatically determined by.

Then, the print image shows "There is a rotation instruction.
In this embodiment, as shown in FIG.
When scanning in the coordinate space, if the subscan number is an even number
Substitute "Virtual column initial value" into the virtual column at the start of main scanning
After that, add virtual column intervals as the main scan progresses
To do. As a result, the main scan is data a from left to right.₀, B
₀, C₀, D₀,,, and the next sub-scan number is even
When the main scan is data a₂, B₂, C₂, D₂,···When
It is done like that.

On the other hand, when the sub scanning number is an odd number, the main scanning is opened.
At the beginning, set "virtual column initial value + virtual column interval / 2" to the virtual column
substitute. After that, in the same way
Then, the virtual column interval is added. This makes the main scan left
From right to data a₁, B₁, C ₁, D₁,,, next
Data a when the sub-scan number of is odd₃, B₃, C₃, D
₃, ... and so on.

Further, the virtual line has a "virtual line" at the start of the sub-scan.
Substituting "line initial value", and then temporarily as the sub-scan progresses.
Add thought intervals. This causes the sub-scan to go from top to bottom.
Be seen. Therefore, if this rotation instruction is given,
Main scan print dots with even scan numbers and sub scan numbers
The virtual column coordinates are more
Will be shifted by "virtual column interval ÷ 2".
Therefore, the printing is performed in a staggered manner for each pixel. And this place
In both cases, whether the printing of each pixel of the printed image is viewed vertically or horizontally
Staggered (image data b in the figure)₂, B₃, C₂,
c₃, D₂And d₂, C₃, D_Four, C_Five, D₆Array of
See). The line connecting adjacent print pixels is an equilateral triangle.
Are arranged so that the upper and lower edges and both side edges are excluded.
Adjacent to any printed pixel, picked up
The line connecting the print pixels forms a regular hexagon (image in the figure)
Data c₈Image data b centered on₇, B₉, C₆,
c ₈, C_Ten, C₇, C₉See the array). In this case
Also, the image data after the synthesis processing of the virtual column coordinates is printed by the printing unit 22.
On the even-numbered and odd-numbered heating elements of the
What is used as corresponding print data is that
This is the same as when there is no instruction to turn.

FIG. 12 shows an operation flowchart of the virtual column generation circuit 13 for generating a virtual column in the virtual coordinate space as described above, and FIG. 13 shows an operation flowchart of the virtual row generation circuit 14 for similarly generating a virtual row. Show. In this process, the virtual column initial value, virtual column interval, and rotation instruction presence / absence information are input to the virtual column generation circuit 13 from the CPU 12, and the timing signal generation circuit 11 starts main scanning.
Information of main scan change, sub scan start, sub scan change, and sub scan odd number is input. Further, the virtual row generation circuit 14 has
Similarly, the virtual row initial value, the virtual row interval, and information regarding the presence / absence of a rotation instruction are input from the CPU 12, and the timing signal generation circuit 11 performs the main scanning start, main scanning change, sub-scanning start, sub-scanning change, and sub-scanning in the same manner as above. Scan odd number information is input.

The virtual column initial value and the virtual row initial value are print start point coordinates of the image data converted from the image memory address space to the virtual coordinate space by the combining process after the sharpness process, and are rotated as described above. If there is no instruction, the point in the lower left corner of the image data to be cut out is specified,
When there is a rotation instruction, the upper left point of the image data is also designated. The virtual column interval and the virtual row interval are calculated and set by the CPU 12 based on the enlargement ratio designated as described above. The parameters of the initial value and the interval value and the number of main scans and the number of sub-scans controlled by the timing signal generation circuit 11 enable printing in an arbitrary range of the image memory 16.

First, the operation of virtual column generation by the virtual column generation circuit 13 will be described with reference to the flowchart of FIG.
In the following processing, although not particularly shown, a virtual row register for storing virtual row coordinates and a virtual column register for storing virtual column coordinates are used to sequentially set the virtual coordinate space.

First, it is determined whether or not there is a rotation instruction (step S1). Then, if a signal indicating that there is no rotation instruction is input from the CPU 12 (NO in S1), the virtual column generation process for the case where there is no rotation instruction is performed as described below.

That is, it is judged whether or not there is a change in the sub-scanning (step S6), and if the sub-scanning change signal is input from the timing signal generating circuit 11 (YES in S6), then the sub-scanning change. Is the start of the sub-scan or the transition to the next sub-scan during execution of the sub-scan (step S7). If the sub-scanning start signal is input from the timing signal generating circuit 11 (S7
Is YES), the sub-scanning is started, that is, the sub-scanning origin is set. Therefore, in this case, the virtual column initial value is set in the virtual column register (step S8). As a result, the column coordinates of the scanning origin 51 (the column coordinates of the sub-scanning number 0) in the case where there is no rotation instruction shown in FIG. 11 are set.

In this case, the row coordinates of the scanning origin 51 by the virtual row generation circuit 14 described later are also set,
The origin 51 is first set based on these set column and row coordinates.
Image data is scanned.

Then, returning to step S1, it is confirmed that there is no rotation instruction (S1 is NO), and it is determined in step S6 that there is no change in sub-scanning (NO in S6). Repeatedly until the sub-scanning No. 0 main scanning ends, the timing signal generating circuit 11 again inputs a signal with sub-scanning change (YES in S6),
Next, it is determined that the sub-scanning is being executed instead of being started (NO in S7), and the virtual column interval is added to the virtual column data of the virtual column register (step S9). As a result, the virtual column coordinates for the next sub-scan are set.

Thus, steps S1 and S are performed during the main scanning.
6 is repeated, and steps S6, S7, S
9, the virtual column data is sequentially incremented by the virtual column interval to generate a virtual column for sub-scanning. As a result, sub-scanning from the left to the right in the case without the rotation instruction shown in FIG. 11 is realized.

On the other hand, the virtual row generation circuit 14 generates a virtual row in the case where there is no rotation instruction described below in parallel with the above processing. This operation will be described based on the flowchart of FIG.

Also in this case, first, it is determined whether or not there is a rotation instruction (step S11), and it is confirmed that no signal indicating no rotation instruction is input from the CPU 12 (NO in S11).
The virtual row generation processing in the case where there is no rotation instruction described below is performed.

First, it is determined whether or not there is a change in the main scanning (step S12), and if a signal of the main scanning change is input from the timing signal generation circuit 11 (S12 is YE).
S) Then, it is determined whether the change in the main scan is the start of the main scan or the scan to the next image data during the execution of the main scan (step S13). Then, if the main scanning start signal is input from the timing signal generation circuit 11 (YES in S13), it is further determined whether or not the main scanning start is the main scanning start in the odd-numbered sub-scanning (step S14). ). When the signal indicating the odd number of sub-scans is not input from the timing signal generation circuit 11, it is recognized that the main scan in the even-numbered sub-scan is started (NO in S14), and the virtual row initial is set in the virtual row register. A value is set (step S19). As a result, the row coordinates of the scanning origin 51 when there is no rotation instruction shown in FIG. 11 are set. This first becomes the main scanning start row coordinate of the sub-scanning number 0, and thereafter becomes the main scanning start row coordinate of an even-numbered sub-scanning number.

Until the timing of scanning the image data next to the main scanning, it is confirmed in step S11 that there is no rotation instruction (NO in S11), and in step S12 that there is no change in main scanning (NO in S12). Repeat discrimination. When a signal indicating that the main scanning has changed is input from the timing signal generating circuit 11 at the scanning timing of the next image data (YES in S12), it is then determined that the main scanning is being executed instead of being started (S13). Is NO), the virtual row interval is subtracted from the virtual row data in the virtual row register (step S16). As a result, the virtual row coordinates of the image data next to the main scan are set.

As described above, during the main scanning, steps S11,
S12, S13, and S16 are sequentially repeated, and the virtual row data is sequentially decremented by the virtual row interval, whereby the main scanning is performed from the bottom to the top of the virtual coordinate space. Main scanning is realized.

If the sub-scanning is an odd number in step S14, "virtual row initial value-virtual row interval / 2" is set in the virtual row register (step S1).
6). As a result, in the main scanning in the odd-numbered sub-scans, the line coordinates are always displaced by "virtual line interval / 2" toward the origin, that is, upward, and the staggered main scanning in the odd-numbered sub-scan shown in FIG. The deviation of shape is realized.

Next, the processing when there is a rotation instruction will be described below. By the determination in step S1 of FIG. 12 described above, the CP
If there is a rotation instruction signal from U12 (S
If 1 is YES), the virtual column generation process in the case where there is a rotation instruction described below is performed.

First, it is determined whether or not there is a change in main scanning (step S2), and if a signal for main scanning change is input from the timing signal generation circuit 11 (YES in S2), then the main scanning is started. Or not (step S
3). Then, if the main scanning start signal is input from the timing signal generation circuit 11 (YES in S3), it is subsequently determined whether or not the main scanning start is the main scanning start in the odd-numbered sub-scanning ( Step S4). Then, when the main scanning is not started in the odd-numbered sub scanning, that is, in the even-numbered sub scanning (NO in S4), the virtual column initial value is set in the virtual row register (step S8). As a result, the scanning origin 52 shown in FIG.
The column coordinates of are set. This first becomes the main scanning start column coordinate of the sub scanning number 0, and thereafter becomes the main scanning start column coordinate of an even sub scanning number.

Then, until the main scanning of sub-scan number 0 ends,
It is confirmed in the step S1 that there is a rotation instruction (YES in S1), and there is a change in main scanning in step S2 (YES in S2).
Then, in step S3, it is confirmed that the main scanning is being executed (S3 is NO), and the virtual column data of the virtual column register is virtualized as in the case of the sub-scanning in the case where there is no rotation instruction as described above. The process of adding the column intervals (step S9) is repeated. As a result, the column coordinates for the next main scan are sequentially set. The repetition of these steps S1, S2, S3, and S9 is similarly performed from the start to the end in the main scanning in which all sub-scanning numbers are even.

As described above, when the rotation instruction is issued, the virtual column data is sequentially incremented by the virtual column interval to sequentially generate the virtual coordinates of the main scanning, and the image data shown in FIG. 12 is performed from left to right. Main scanning processing is realized.

In this way, when the main scanning is completed and the signal for starting the main scanning is input again from the timing signal generating circuit 11 in the step S3 (YES in S3), the sub-scan of the main scanning is started again in the step S4. It is determined whether or not the scan number is an odd number, and if it is an odd number (S4 is YE
S), "virtual column initial value + virtual column interval / 2" is set in the virtual column data of the virtual column register (step S5). As a result, in the main scanning in the odd-numbered sub-scans, the column coordinates are always displaced by "virtual column interval / 2" in the direction away from the origin, that is, to the right, and the main scanning in the odd-numbered sub-scans shown in FIG. The staggered deviation of is realized.

In parallel with the above processing, the virtual row generation circuit 14 generates a virtual row when there is a rotation instruction as described below. This operation will be described again with reference to the flowchart of FIG.

Also in this case, the presence / absence of a rotation instruction is first determined (step S11), the signal input with the rotation instruction from the CPU 12 is confirmed (S11 is YES), and the virtual line in the case of the rotation instruction described below is confirmed. Performs generation processing.

In this case, it is first judged whether or not there is a change in the sub-scan (step S17). Then, if the sub-scanning change signal is input from the timing signal generating circuit 11 (YES in S17), the sub-scanning change is the start of the sub-scanning, or the next sub-scan during the execution of the sub-scanning. It is determined whether or not the movement is for scanning (step S18).
Then, if the sub-scanning start signal is input from the timing signal generating circuit 11 (YES in S18), it is determined that the sub-scanning start, that is, the sub-scanning origin is set, and in this case, The virtual row initial value is set in the virtual row data of the virtual row register (step S19). This allows
The row coordinates (column coordinates of the sub-scanning number 0) of the scanning origin 52 in the case where there is the rotation instruction shown in FIG. 12 are set.

Then, since the column coordinates of the scanning origin 52 are set by the virtual column generating circuit 13 described above, the image data of the origin 52 is scanned first. Then, returning to step S11, it is confirmed that there is a rotation instruction (YES in S11), and there is no change in sub-scanning in step S17 (N in S17).
O) is repeated until the sub-scanning No. 0 main scanning is completed, and when a sub-scanning change signal is input again from the timing signal generating circuit 11 when the sub-scanning No. 0 main scanning is completed. (YES in S17) Next, in step S18 again, it is determined that the sub-scanning is being executed this time instead of being started (NO in S18), and the virtual row interval is added to the virtual row data of the virtual row register. Yes (step S20). As a result, the virtual row coordinates for the next sub-scan are set.

As described above, during the main scanning, steps S11,
S17 is repeated, and steps S17 and S
In step S20, the virtual row data is sequentially incremented by the virtual row interval to generate a virtual row for sub-scanning in the direction away from the origin. As a result, sub-scanning from the top to the bottom in the case where there is the rotation instruction shown in FIG. 12 is realized.

As described above with reference to FIGS. 1 to 13, C
From PU 12 to virtual column generation circuit 13 and virtual row generation circuit 1
4, the presence / absence of a rotation instruction, the virtual column and virtual row initial values, the virtual column and virtual row interval parameters, and the timing signal generation circuit 11 to the virtual column generation circuit 13 and the virtual row generation circuit 14. The information about the number of main scans and the number of sub-scans supplied in this way enables printing in an arbitrary range of the image memory.

As described above, in this embodiment,
Regardless of whether the print image is rotated or not, the regular hexagon drawn by the six print pixels (print dots) centering on the target pixel is one of the three lines formed by connecting two opposite vertices. The lines are formed so as to be parallel to the sub-scanning direction (see FIG. 1).
0, see FIG. 11). In such an array of print dots, three print dots adjacent to each other form an equilateral triangle.

FIG. 14 shows again the state of arrangement of the print dots in the main scanning direction and the sub scanning direction. In the figure, the center of the print dot is represented by the intersection of the "x" marks. In the figure, there are 6 printing dots centered on the printing dot "a", "b", "c", "d", "e", and "f".
And an example of a regular hexagon formed by "to". Here, arbitrary three print dots adjacent to each other, for example, print dots “a”, “to” and “f” in the figure
Taking an example of an equilateral triangle formed by
It is known that a perpendicular line that descends from the apex of a regular triangle (print dot “a”) to the bottom (the line connecting the other two print dots “t” and “f”) bisects the bottom. If the distance between the intersection of this perpendicular line and the bottom and the print dot "to" (or "he") is "D", the length of the bottom (the distance between the print dots "to" and "he") is It is "2D". The distance "D" is the distance for one sub-scan, as already described.

Since the above-mentioned print dots "a", "to" and "f" form an equilateral triangle, the length of each side is equal, and therefore the print dots "a" and "to" are the same. The straight line distance is “2D” like the base. Therefore, the length of the perpendicular line drawn from the print dot “A” to the bottom is √3 · D according to the Pythagorean theorem. From this, it is clear that the interval between the print dots in the main scanning direction (for example, the interval between the print dots “TO” and “C” in the main scanning direction) is twice the perpendicular line, that is, “2√3 · D”. .

From these facts, the print aspect ratio of one pixel, that is, the interval between the closest pixels (refer to the print dots "a" and "t" in the figure) in the sub-scanning direction (vertical direction of the paper). It is clear that the ratio of the main scanning direction (paper lateral direction) interval is “1: √3”.

In the present embodiment, when calculating the enlargement ratio, the aspect ratio of one pixel in the image memory 16 is 1: √3 based on the fact that the print aspect ratio of one pixel is 1: √3. Is set to. Therefore, the scale ratio of the virtual column coordinate axis and the virtual row coordinate axis in the virtual coordinate space corresponding to the image memory 18 is also set to 1: √3.
The enlargement ratio is calculated based on the scale setting of this virtual coordinate space. The calculation of the enlargement ratio will be described below.

First, the case where there is no rotation instruction will be described. When this rotation instruction is not issued, as shown in FIG. 10, the main scanning with respect to the virtual coordinate space is performed in the virtual row direction and the sub-scanning is performed in the virtual column direction. This is shown again in Fig. 15 (a). In the same figure, the scale ratio between the virtual column coordinate axis and the virtual row coordinate axis described above is schematically shown, and the print dot interval described in FIG. 14 is shown in comparison therewith.

Here, when the virtual column interval is a, the virtual row interval is b, and the number of virtual columns is n and the number of virtual rows is m, printing is performed by setting the distance of one sub-scan as D. For the length w in the virtual column direction and the length t in the virtual row direction of the printed image, the following equations are satisfied: W = (n / a) D, t = (m / b) 2√3 · D.

Further, three adjacent print dots form an equilateral triangle, that is, the aspect ratio of the print image is kept constant so that the print image does not become vertically or horizontally long with respect to the original image data (image source). To achieve this, the scale of the virtual coordinate space described above may be kept at 1: √3. That is, since "virtual column unit length": "virtual row unit length" may be set to 1: √3, the following equation: D / a: 2√3 · D / b = 1: √3 Holds.

∴a: b = 1: 2, so that the relationship between a and b can be obtained.
FIG. 2B shows an example of the parameters given as a and b above. This chart has the number 1 on the leftmost vertical.
3 to 3, and the a and b parameters corresponding to these numbers, the image rotation instruction, and the image enlargement ratio are shown on the side. Note that the numbers 1 to 3 are assigned to each set of parameters for convenience of explanation.

As shown in the figure, the number 1 is the enlargement ratio 1
An example of parameter setting of a and b in the case of 00% (full size printing) is shown. That is, when the enlargement ratio is 100%, the virtual column interval a is "64" and the virtual row interval b is "128" (above a: b.
= 1: 2). This expansion rate 100%
If the value of the virtual column interval a at the time is set as the reference value of the enlargement ratio,
Since "(reference virtual column interval ÷ virtual column interval) x 100" represents the enlargement ratio, if an arbitrary enlargement ratio is given, the virtual column interval corresponding to the enlargement ratio can be easily calculated from the above relationship. Virtual line spacing is also easily calculated.

The enlargement ratio of No. 2 in the figure (b) is 50% (1 /
In the case of (reduction to 2), a = 128 and b = 256 indicate examples calculated in this way. The same applies to a = 12 and b = 24 when the enlargement ratio of number 3 is 533% (about 5 times), and other enlargement ratios can be calculated by the above calculation.

Next, the calculation of the enlargement ratio when there is a rotation instruction will be described. If there is a rotation instruction,
As shown in, the main scanning with respect to the virtual coordinate space is performed in the virtual column direction, and the sub-scanning is performed in the virtual row direction. This is shown in FIG. 16 (a) by comparing the schematic scale of the virtual coordinate space with the print dot spacing, as in the above.

Here, the virtual column interval is c, the virtual row interval is d,
Similarly to the above, if the number of virtual columns is n, the number of virtual rows is m, and the distance of one sub-scan is D, the print image has a length w'in the virtual column direction and a length t'in the virtual row direction. Is expressed by the following equation, W '= (n / c) 2√3 · D, t' = (m / d) D.

Also in this case, in order to keep the aspect ratio of the printed image constant, the scale of the virtual coordinate space is made constant, that is, "virtual column unit length": "virtual line unit length" is set to 1 as in the above case. : Set to √3. From this, the following equation, 2√3 · D / c: D / d = 1: √3, holds, and ∴c: d = 1: 2. As a result, the relationship between c and d is obtained.

Further, the enlargement ratio in this case can be obtained by "the size of the printed image without rotation": "the size of the printed image with rotation" = "enlargement ratio". That is, w '/ w = t' / t = 2√3 · a / c = √3 · b / c = √3 · b / 6d = √3 · a / 3d.

The enlargement ratio 4 of the number 4 shown in the chart of FIG.
C = 528 and d = 88 in the case of 2% and c = 30 and d = 5 in the case of the enlargement ratio 739% of the number 5 indicate examples calculated in this way. Also, in the case of other enlargement ratios, it can be easily calculated by the above calculation.

The above-mentioned print image has been described by taking the printing of the frame image (all scanning) as an example, but it can be applied to the printing of the field image (every other scanning).
In the case of printing this field image, as is clear from FIG. 14 (for example, the print dot “b” in the figure is shifted to the next sub-scanning line), the print aspect ratio of one pixel is “2: √3”.
Is.

Correspondingly, if the aspect ratio of one pixel in the image memory is set to 2: √3 and the scales of the virtual column coordinate axis and the virtual row coordinate axis of the virtual coordinate space are also set to 2: √3, the above-described enlargement ratio calculation is performed. When there is no rotation instruction, “virtual column unit length”: “virtual row unit length” = 2: √3, and D / a: 2√3 · D / b = 2: √3 , A: b = 1: 4, the relationship between a and b is obtained. Further, in the case where there is a rotation instruction, similarly, from the relational expression of 2√3 · D / c: D / d = 2: √3, the relation between c and d of c: d = 3: 1 can be obtained. Further, the enlargement ratio in this case is obtained by w ′ / w = t ′ / t = 2√3 · a / c = √3 · b / 2c = √3 · b / 6d = 2√3 · a / 3d be able to.

The diagram of FIG. 17 shows the above-mentioned image memory 1
It is an example of the parameter when the aspect ratio of the pixel is set to 2: √3. Also in this case, the enlargement ratio is 10 without the rotation instruction.
The reference value at 0% and a corresponding to the respective enlargement ratios of 50% and 533% calculated based on the reference value,
The values of b and the values of c and d corresponding to the enlargement ratios of 42% and 739 when the rotation instruction is given are shown.

In FIG. 17, the virtual line spacing is the same as in FIG.
It is doubled as compared with the virtual row interval in FIG. 5 (b) and FIG. 16 (b). This is because the pixel aspect ratio is 1: √3 in FIGS. 15 and 16 and is 2: √3 in FIG.

As described above, by using the virtual coordinate space, in image processing in which one pixel of the image memory may generally have two kinds of aspect ratios, the relationship between the two kinds of aspect ratios of the image data to be processed is two. It is possible to easily realize the configuration of the image processing device having the double relationship.

[0135]

As described above in detail, according to the present invention, by using virtual coordinates, a simple circuit configuration can be realized.
It is possible to obtain a print image at a free enlargement ratio in both cases of rotating the print image by 90 degrees. Further, since the sharpness processing is performed based on the original image data and then the synthesis processing is performed, it is possible to obtain a print image with a sharpness processing effect. Further, by setting the scales of the X-axis and the Y-axis of the virtual coordinates to 1: √3, the print dot position is main-scanned when the sub-scan is even and when the sub-scan is odd, regardless of the enlargement ratio. A printing method that shifts the semi-main scanning interval in the direction can be easily realized. Further, since the image data is converted into the print data via the virtual coordinate space, the print image data can be obtained in a constant processing time regardless of the enlargement ratio. Further, since the processing is performed in the virtual coordinate space, no memory is required for the sharpness processing and the composition processing, which is economical. Further, since it is possible to easily cope with image data in which the relationship of the aspect ratio of two kinds of one pixel is doubled, by setting the scale of the X-axis and the Y-axis of the virtual coordinate to 2: √3, it is possible to easily deal with one pixel. It is possible to easily configure the image processing device in which the relationship between the two types of aspect ratios is double.

[Brief description of drawings]

FIG. 1 is a block diagram of an image printing apparatus according to an embodiment.

FIG. 2 is a diagram showing a relationship between an image memory address space and a virtual coordinate space.

FIG. 3 is a diagram showing the correspondence relationship between an image memory address space and a virtual coordinate space in more detail.

FIG. 4A and FIG. 4B are diagrams illustrating a sharpness process and a synthesizing process performed thereafter.

FIG. 5 is a diagram illustrating composition.

6A and 6B are charts showing values of intermediate data in the combining process.

FIG. 7 is a diagram showing a sequential circuit of a synthesis processing circuit.

FIG. 8 is a timing chart of the operation of the sequential circuit.

9A is a diagram showing a print state when a print image has no rotation instruction, and FIG. 9B is a diagram showing a print state when there is a rotation instruction.

FIG. 10 is a diagram showing a correspondence relationship between pixels of a print image and virtual coordinates when the print image has no rotation instruction.

FIG. 11 is a diagram illustrating a correspondence relationship between pixels of a print image and virtual coordinates when the print image has a rotation instruction.

FIG. 12 is a flowchart of the operation of a virtual column generation circuit that generates a virtual column in a virtual coordinate space.

FIG. 13 is a flowchart of the operation of a virtual row generation circuit that generates a virtual row in a virtual coordinate space.

FIG. 14 is a diagram illustrating an arrangement of print dots in a main scanning direction and a sub scanning direction.

FIG. 15A is a diagram showing the scale of virtual coordinates and the interval of print dots in contrast when there is no rotation instruction, and FIG. 15B is a diagram showing an example of parameters corresponding to the enlargement ratio.

16A is a diagram showing a scale of virtual coordinates in comparison with a print dot interval in the case where there is a rotation instruction, and FIG. 16B is a diagram showing an example of a parameter corresponding to an enlargement ratio.

FIG. 17 shows the aspect ratio of one pixel in the image memory is 2: √
It is a figure which shows the example of the parameter corresponding to the expansion rate at the time of setting it as 3.

FIG. 18 is a block diagram showing a configuration of a conventional image processing apparatus.

[Explanation of symbols]

1 Timing Signal Generation Circuit 2 CPU (Central Processing Unit) 3 Address Generation Circuit 4 Image Memory 5 Image Storage Unit 6 Synthesis Processing Circuit A 7 Synthesis Control Circuit 8 Sharpness Processing Circuit 9 Synthesis Control Circuit B 10 Image Processing / Print Control Circuit 11 Timing Signal generation circuit 12 CPU 13 Virtual column generation circuit 14 Virtual row generation circuit 15 Address generation circuit 16 Image memory 17 Image storage means 18 Sharpness processing circuit 19 Synthesis processing circuit A 20 Synthesis processing circuit B 21 Image processing circuit / print control circuit 22 Printing Parts a, b, c, d, e, f, g, h, i, j, k, l,
m, n, o, p image data (luminance signal Y) Q composite data F, G, J, K sharpened data s control signal v, u intermediate composite data x, y, w address data 31, 32, 33 , 34, 35, 36 Multiplexer 37, 40, 42 Bit shifter 38, 39, 41 Adder 43, 44 Latch 51, 52 Scan origin

─────────────────────────────────────────────────── ─── Continued Front Page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H04N 1/38-1/409 G06T 3/00-3/60 G06F 3/12 B41J 5/30

Claims (7)

(57) [Claims] 1. An image printing apparatus for printing and outputting image data, coordinate calculation means for calculating coordinates in a virtual coordinate space corresponding to an address space of an image memory, image data read from the image memory and the coordinate calculation. a image processing means for creating print data based on the calculation result of the coordinates by means of said virtual coordinate space comprises a virtual column coordinate and a virtual line coordinates,
The coordinate calculation means is a virtual column initial value on the virtual coordinate,
Virtual column spacing, virtual row initial value, virtual row spacing, image memo
Output the image data read from the printer as print data.
Whether to rotate the image when rotating, and the rotation when rotating the image
An image printing device characterized by performing coordinate calculation based on an angle . 2. The coordinate calculation means determines the position of a print image on the image memory based on at least the virtual column initial value and the virtual row initial value.
The image printing device described. 3. The image printing apparatus according to claim 1, wherein the coordinate calculation unit determines the enlargement ratio of the print image based on the virtual column spacing and the virtual row spacing. Wherein said coordinate calculating means, the sub-scanning direction of the even-numbered main scanning and sub-scanning direction the virtual coordinate space of the odd-numbered main scanning direction an initial value of the main scanning direction of the virtual coordinate in the main scanning The image printing apparatus according to claim 1, wherein the image printing apparatus is set to be shifted by 1/2. Wherein said image processing means, according to claim 1, wherein the printed output to print the pixel data of the image memory in longitudinal or transverse direction of the printing paper in accordance with the presence or absence of the image rotation Image printing device. Wherein said image processing means, outputs the processed luminance signal by performing edge enhancement processing to the output of the image memory
Based on the virtual column address and virtual row address
The image printing apparatus according to claim 1, wherein the print data is created by synthesizing processed luminance signals . 7. The image processing means is one of the image memories.
Representing the aspect ratio (vertical ratio) of a pixel by the ratio of the square root of a one-digit integer, and setting the ratio of the virtual column interval and the virtual row interval by the image rotation to be a one-digit integer ratio. The image printing apparatus according to claim 1, wherein