JPH09160886A - Method for controlling traffic of multiprocessor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a traffic control method for a multiprocessor whereby the bus band width of processing data is not reduced. SOLUTION: The method is provided with a process 1 or 8 where a processor PM1 or PM3 produces processing data with a previously fixed cycle, the processes 3 and 5 or 12 where the processors PM2 and PM4 require the reading of processing data to the processors PM1 and PM3 with a bus B2 with a previously fixed order and the processes 2 and 9 or 11 where the processor PM1 or PM3 which completes the production of processing data and also receives the request of the processor PM2 or PM4, transmits processing data without control information to the bus B2 and the processor PM2 or PM4 which requires reading receives processing data with the bus B2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiprocessor traffic control method for processing data by a plurality of processors in a signal processing system, and more particularly to a synchronization method between the processors.

[0002]

2. Description of the Related Art In a multiprocessor in which independently operating processors are connected to each other by a communication path to execute one integrated process as a whole, processors PM1 to PMn are connected via a bus B1 as shown in FIG. However, each is exchanging data. In order for each processor to cooperate well, it is necessary to transfer the data necessary for the processor to proceed, and to control the order in which each processor executes the processing so that the correct processing result is obtained. Synchronization between processors is required.

As a conventional multiprocessor traffic control method, there is a synchronization mechanism based on the act of competing for shared variables, a hardware synchronization mechanism such as test and set, and a software synchronization mechanism such as a semaphore. . As another method, there is a method called message passing, in which control information designating a sender and a receiver of data is transferred together with the data.

[0004]

However, in the conventional multiprocessor traffic control method as described above,
Emphasis is placed on versatility so that shared resources of various granularities can be handled in various situations. Therefore, even in a system such as a signal processing system in which the transmission / reception destination of traffic is almost fixed, the control information and the like are used. This limits the amount of data to be originally processed due to control information, etc., and reduces the processing performance of the processor and the bandwidth of the communication path connecting the processors. For example, many complex Fourier transforms are processed in real time. It has been difficult to satisfy the demand for a large-scale signal processing system that is required to do so.

Therefore, there is a demand for a traffic control method of a multiprocessor having a simpler and more efficient synchronization mechanism that does not reduce the processing performance of the processor and the bus bandwidth of the processed data.

[0006]

In a traffic control method for a multiprocessor according to the present invention, a processor on the production side for transmitting information and a processor on the consumption side for receiving information are mutually coupled via a bus, In a multiprocessor traffic control method that performs cooperative operation, a process in which a processor on the production side produces processing data at a predetermined cycle, and a processor on the consumption side sends a bus to the processor on the production side in a fixed order in advance. A step of requesting the reading of the processed data via the process, and a step of completing the production of the processed data and receiving the request of the consuming processor, the processor of the producing side sends the processed data without the control information to the bus. , And the consuming processor that has requested the reading receives the processed data via the bus. The processor on the consuming side pre-fixes the order of read requests for processing data, requests the processor on the producing side for reading, and the processor on the producing side receiving the request sends the processed data to the processor on the consuming side receiving the request. Received by the processor. The consuming processor that receives the processed data is determined without the control information. Therefore, it is not necessary to send the control information such as the reception destination together with the processed data, and the bus bandwidth of the processed data is expanded accordingly.

[0007]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 FIG. FIG. 1 is a flowchart of a traffic control method for a multiprocessor according to a first embodiment of the present invention.
In the present embodiment, the processors are PM1 to PM4.
4 processors are used. Further, the processor PM2 has traffic T12 and traffic T32.
It is assumed that the processor PM3 is required to control traffic in the order of traffic T32 and traffic T34 in this order. Further, in the initial state, it is assumed that the message M42 is in the receiving state due to the state in which the flag of PM2 is set.

[0008] Here, the traffic refers to traffic that moves within the network while undergoing processing, and the "flow of processing data" corresponds to it here. Traffic control means controlling the transmission order or reception order of traffic input or output by a certain processor in a sequence on the time axis. Since all the processors involved in a certain traffic execute their own processing in synchronization with the traffic, controlling the traffic is synchronized between these processors.

FIG. 3 is a diagram showing a configuration and a data flow according to the first embodiment of the present invention. Processor PM1
Is a processor that is a source (information producer) of the traffic T12, and periodically repeats the production of the information that becomes the traffic T12. Similarly, the processor PM3 is a processor that is a source of the traffic T32 and the traffic T34, and periodically repeats the production of the information that becomes the traffic T32 and the information that becomes the traffic T34.

The processor PM2 is a destination (information consumption side) of the traffic T12 and the traffic T32, and periodically repeats the consumption of the information of the traffic T12 and the information of the traffic T32. Similarly, processor PM4 uses traffic T34
, Which is a destination of, and repeatedly consumes the information of the traffic T34. Since traffic is generated by reading from the destination side, the processor on the destination side of the traffic becomes the bus transaction requester,
The source processor becomes the bus transaction responder.

Next, the procedure of each processor will be described with reference to FIG. The processor PM1 produces 1 of traffic T12 information consumed by the processor PM2. The processor PM1 enters a waiting state until the production of information 1 is completed and the read request 3 of the traffic T12 receives the read request R21 transmitted from the processor PM2. When the production 1 of the traffic T12 information is completed and the read request R21 is received, the processor PM1 starts the traffic T12 read response 2 and transmits the produced traffic T12 information. When the transmission of the traffic T12 is completed, the process returns to the production 1 of the traffic T12 information again, and the above procedure is repeated.

The processor PM2 uses the traffic T12.
In the read request 3, the read request R21 is transmitted to the processor PM1 and the standby state is entered. Traffic T12
When the traffic T12 is transmitted from the processor PM1 by the read response 2, the processor PM2 receives the traffic T12, starts consumption 4 of the traffic T12 information, and processes the traffic T12 information. The processor PM2 enters the waiting state until the consumption 4 of the traffic T12 information is completed and the message M42 reception state is completed. When the traffic T12 information is consumed and the message M42 is received, the processor PM2 requests the processor PM3 to read the traffic T32.
Then, the read request R23 is transmitted to enter the waiting state.
Traffic T32 read response 9 causes processor P
When the traffic T32 is transmitted from M3, the processor PM2 receives the traffic T32. When the reception of the traffic T32 is completed, the processor PM2
Sends a message 6 to the processor PM4 to the effect that traffic T32 has been received, and sends a message M24. After sending the message M24, the processor PM2 starts consuming the traffic T32 information 7 and processes the traffic T32 information. When the consumption 7 of the traffic T32 information is completed, the traffic T12 read request 3 is made again.
Return to and repeat the above procedure.

The processor PM3 produces 8 traffic T32 information consumed by the processor PM2. The processor PM3 completes the production 8 of the traffic T32 information and, due to the read request 5 of the traffic T32, the read request R23 transmitted from the processor PM2.
Enter the waiting state until receiving. When the production 8 of the traffic T32 information is completed and the read request R23 is received, the processor PM3 starts the traffic T32 read response 9 and transmits the produced traffic T32.
When the traffic T32 read response 9 is completed, the processor PM3 starts producing 10 the traffic T34 information. The processor PM3 enters the waiting state until the production 10 of the traffic T34 information is completed and the read request R43 transmitted from the processor PM4 by the read request 12 of the traffic T34 is received. Complete production 10 of traffic T34 information and request read R4
3, the processor PM3 receives the traffic T3.
Start the read response 11 of 4 and produce traffic T
34 is transmitted. Traffic T34 read response 11
When the process ends, the processor PM3 returns to the traffic T
Return to 32 information production 8 and repeat the above procedure.

The processor PM4 waits until the message M24 is received. Message M24
In the receiving state, the processor PM4
3, the read request 12 of the traffic T34 is started, the read request R43 is transmitted, and the process enters the waiting state. According to the read response 11 of the traffic T34, the processor P
When the traffic T34 is transmitted from M3, the processor PM4 receives the traffic T34. When the reception of the traffic T34 is completed, the processor PM4 performs a message transmission 13 of the completion of the reception of the traffic T34 to the processor PM2, and the message M42.
Send Traffic T after sending message M42
Start consuming 14 information 14 to process traffic T34 information. When the consumption 14 of the traffic T34 information is completed and the message M24 becomes the reception state, the processor PM4 returns to the traffic T34 read request 12 again and repeats the above procedure.

FIGS. 4, 5 and 6 are control procedure diagrams including a bus transaction according to the first embodiment of the present invention. 4 and 5 are control procedure diagrams centering on the processor PM2, and FIG. 6 is a control procedure diagram centering on the processor PM4. Here, the traffic read request, the read response, and the reception completion message will be described by taking the traffic T12 read request 3, the traffic T12 read response 2, and the message transmission 6 as an example.

When the traffic T12 read request 3 is issued, the processor PM2 issues an occupancy request 31 for the bus B2,
It transmits to the bus arbiter BA which is a bus arbitrator between processors. Upon receiving the bus occupation permission 32 from the bus arbiter BA, the processor PM2 transmits the read address 33 to the processor PM1 in order to specify the address in which the traffic T12 information is stored. Upon receiving the read address 33, the processor PM1 sends a split response 34 to the processor PM2. Here, the split response 34 means that when the processor PM2 that has received the bus occupation permission issues a request to the processor PM1 selected by the processor PM2, if the processor PM1 cannot respond to the request for various reasons. It sends a wait command to PM2. Further, when transmitting the split response 34, the processor PM1 also designates and transmits the read response address information used in the read response. This read response address information is
Specify a special address so that it will not be confused with other data in the waiting state. When the processor PM2 receives the split response 34, once the bus release 35 causes the bus B
2 is released, and the processor PM2 enters a waiting state for processing data transmission. This traffic T12 read request 3
In, the processing data 25 is not transferred. The above read request procedure is performed in the same manner for the traffic T32 read request 5 and the traffic T34 read request 12.

When the processor PM1 is ready to send the traffic T12 information, it starts a traffic T12 read response 2 and sends a bus occupancy request 21 to the bus arbiter BA. Upon receiving the bus occupation permission 22 from the bus arbiter BA, the processor PM1 transmits the read response address 23 to the bus B2. Processor PM2
When receiving the read response address 23 via the bus B2, sends an address response 24 indicating the reception to the processor PM1. The processor PM1 having received the address response 24 receives the processed data 25, that is, the traffic T.
12 Start transmitting information. When the amount of processed data is large, the data is transmitted in multiple times. The processor PM2 sends a data response 26 indicating the reception to the processor PM1. When the transfer of the processing data 25 is completed, the processor PM2 releases the bus B2 by the bus release 27.
The above read response procedure is performed in the same manner for the traffic T32 read response 9 and the traffic T34 read response 11.

The processor PM2 uses the traffic T32.
When the reception of the read response 9 is completed and the message M24 is transmitted, the bus occupation request 61 is transmitted to the bus arbiter BA. Upon receiving the bus occupation permission 62 from the bus arbiter BA, the processor PM2 designates the message writing address 63 to the processor PM4. The processor PM4 sends to the processor PM2 an address response 64 indicating that it has received this. Upon receiving the address response, the processor PM2 sends the message data 65, that is, the message M24 to the processor PM4. The message data 65 is to set a flag or the like indicating that the processor that has received the message data can make a read request. It is also possible to send data such as the destination of the message. Processor PM4 receives message M
By receiving 24, the processor PM2 recognizes that it has received the traffic T32 and that the traffic T34 read request 12 is enabled. The processor PM4 sends a data response 66 indicating the reception to the processor PM2. When receiving the data response 66,
The PM2 releases the bus B2 by the bus release 67. The procedure for transmitting the reception completion message described above is performed in the same manner for the message transmission 13.

Each processor independently performs these operations, but the read request order of the processors PM2 and PM4 is fixed in advance, and cooperative operation is performed so that a correct processing result can be obtained as a whole.

In the multiprocessor traffic control method configured as described above, the source side processor processor PM1 and processor PM3 are the traffic T12, traffic T32 and traffic T3.
Produces 4 and the destination processor PM
2 and the processor PM4 transmit the read request R21, the read request R23, and the read request R43, the source-side processor processors PM1 and PM3 send the traffic T12, the traffic T32, and the traffic T34 to the destination-side processor PM2 and the processor PM4. Since the transmission is fixed so that the transmission / reception order of each processor is determined, the cooperative operation can be performed without transmission of control information or the like that reduces the bus bandwidth.

Further, the destination side processor PM2 or the processor PM4, which reads the different traffic T32 or traffic T34 from the source side processor PM3, respectively, receives the message M24 when the reading is completed.
Alternatively, the order of the read requests can be controlled by transmitting and receiving the messages M42 to and from each other, so that mutual operations can be performed.

Further, when the traffic is read, it is divided into a read request and a read response, and the bus B2 is released each time they are completed. Therefore, the bus B2 is not occupied even in the waiting state. It is also possible that another processor uses the bus B2. Therefore, the bus bandwidth is not wasted.

Embodiment 2 FIG. FIG. 7 is a diagram showing a configuration and a data flow according to the second embodiment of the present invention. FIG.
In FIG. 3, the same reference numerals as those in FIG. 3 perform the same operations as in the first embodiment. In the present embodiment,
Processors are PM1, PM2A, PM3A, and PM4
It is assumed that four processors A are used. Further, the processor PM2A has traffic T12 and traffic T
The traffic is controlled in the order of 32, and the processor PM3
It is assumed that A is required to control traffic in the order of traffic T32 and traffic T34. Furthermore, in the initial state, it is assumed that the PM 2A is in the message M42 receiving state due to a state in which the flag is set and the like.

The processor PM2A performs almost the same operation as the processor PM2, but sends a message M23 indicating that the traffic T32 has been received to the processor PM3A.
Further, the processor PM4A performs almost the same operation as the processor PM4, but sends the message M43 of the reception completion of the traffic T34 to the processor PM3A. Further, the processor PM3A performs almost the same operation as the processor PM3, but the message M23 and the message M4 are performed.
The operation of receiving 3 is newly added.

FIG. 8 is a procedure diagram of a traffic control method for a multiprocessor according to the second embodiment of the present invention.
8, traffic T12 information production 1, traffic T12 read response 2, traffic T12 read request 3, traffic T12 information consumption 4, traffic T32 information production 8, traffic T32 information, which are assigned the same numbers as in FIG. Consumption 7, traffic T
The production 10 of 34 information and the consumption 14 of traffic T34 information perform the same operation as in the first embodiment.

Next, the procedure of each processor will be described with reference to FIG. The processor PM1 produces 1 of traffic T12 information consumed by the processor PM2A. The processor PM1 completes the production 1 of the information and by the read request 3 of the traffic T12,
A waiting state is entered until the read request R21 transmitted from the processor PM2A is received. When the production 1 of the traffic T12 information is completed and the read request R21 is received, the processor PM1 starts the traffic T12 read response 2 and transmits the produced traffic T12 information. When the transmission of the traffic T12 is completed, the process returns to the production 1 of the traffic T12 information again, and the above procedure is repeated.

The processor PM2A uses the traffic T1.
2 In the read request 3, the read request R21 is transmitted to the processor PM1 to enter the waiting state. Traffic T1
When the traffic T12 is transmitted from the processor PM1 by the 2 read response 2, the processor PM2A receives the traffic T12, starts consumption 4 of the traffic T12 information, and processes the traffic T12 information. When the consumption 4 of the traffic T12 information is completed, the traffic T32 read request 5A is sent to the processor PM3A.
Then, the read request R23 is transmitted to enter the waiting state. When the traffic T32 is transmitted from the processor PM3A by the traffic T32 read response 9A,
The processor PM2A receives the traffic T32. When the reception of the traffic T32 is completed, the processor PM2A sends the traffic T3 to the processor PM3A.
2 The message transmission 6A indicating that the reception is completed is performed, and the message M23 is transmitted. After sending the message M23, the processor PM2A starts consuming the traffic T32 information 7 and processes the traffic T32 information. When the traffic T32 information consumption 7 is completed, the traffic T
12 Return to read request 3 and repeat the above procedure.

The processor PM3A is connected to the processor PM2.
Produce 8 traffic T32 information that A consumes. The processor PM3A completes the production 8 of the traffic T32 information, and according to the read request 5 of the traffic T32, the read request R transmitted from the processor PM2A.
23, and enters a waiting state until the receiving state of the traffic T34 reception completion message M43 transmitted from the processor PM4A is entered. When the production 8 of the traffic T32 information is completed and the read request R23 and the message M43 are received, the processor PM3A starts the traffic T32 read response 9A and transmits the produced traffic T32. When the traffic T32 read response 9A is completed, the processor PM3A starts producing 10 the traffic T34 information. Processor PM3A
Completes the production 10 of the traffic T34 information, and the read request 12 of the traffic T34 causes the processor P
The read request R43 sent from the M4A is transmitted to the processor P.
It waits until it is received from M4 and is in the reception state of the traffic T32 reception completion message M23 from the processor PM2A. Complete production 10 of traffic T34 information, and read request R43 and message M
Upon receiving 23, the processor PM3A initiates the traffic T34 read response 11A and sends the produced traffic T34. Traffic T34 read response 1
When 1A is completed, the processor PM3A returns to the production 8 of the traffic T32 information again, and repeats the above procedure.

The processor PM4A uses the traffic T3.
In the read request 12A of No. 4, the read request R43 is transmitted to the processor PM3A and the standby state is entered. By the traffic T34 read response 11A, the processor PM3
When the traffic T34 is transmitted from A, the processor PM4A receives the traffic T34. When the reception of the traffic T34 is completed, the processor PM4A
Performs the traffic T34 reception end message transmission 13A to the processor PM3A and transmits the message M43. After sending the message M43, consumption 14 of the traffic T34 information is started to process the traffic T34 information. When the consumption 14 of the traffic T34 information is completed, the processor PM4A returns to the traffic T34 read request 12A again and repeats the above procedure.

In the multiprocessor traffic control method configured as described above, the read completion message M23 and message M43 are sent to the processor PM3.
Since A is concentrated, the processor PM3A only needs to be analyzed when a failure occurs.

Embodiment 3 In the above-described embodiment, the bus arbiter BA receives the bus requests and the like of the respective processors in a centralized manner, but the management may be performed by distributing the bus arbiter BA to the respective processors.

Further, in the above-described embodiment, the processor PM2 is in the message M42 receiving state in the initial state, but the present invention is not limited to this, and the processor in which the message is receiving state is fixed. do not have to. In this case, the read can be requested from the processor in the message receiving state.

Further, in the above-mentioned embodiment, the arrival of the message is recognized by the flag or the like, but the present invention is not limited to this, and the arrival of the message is made by polling for periodically confirming the address. May be recognized.

[0034]

As described above, according to the present invention, the processor on the consumer side, which has requested the reading, can receive the process data sent out by the processor on the producer side even without the control information. The bus bandwidth of data is expanded and a large amount of processed data can be transmitted. Therefore, it can be applied to a system having a large amount of processing data such as a large-scale signal processing system.

[Brief description of the drawings]

FIG. 1 is a flowchart of a traffic control method for a multiprocessor according to a first embodiment of the present invention.

FIG. 2 is a schematic diagram of a signal processing system.

FIG. 3 is a diagram showing a configuration and a data flow according to the first embodiment of the present invention.

FIG. 4 is a control procedure diagram centering on PM2 including a bus transaction according to the first embodiment of the present invention (No. 1).

FIG. 5 is a control procedure diagram centering on PM2 including a bus transaction according to the first embodiment of the present invention (No. 2).

FIG. 6 is a control procedure diagram centering on PM4 including a bus transaction according to the first embodiment of the present invention.

FIG. 7 is a diagram showing a configuration and a data flow according to a second embodiment of the present invention.

FIG. 8 is a flowchart of a traffic control method for a multiprocessor according to the second embodiment of the present invention.

[Explanation of symbols]

PM1, PM2, PM3, PM4, PM2A, PM3
A, PM4A Processor B1, B2 Bus BA Bus Arbiter T12, T32, T34 Traffic M24, M42 Message R21, R23, R43 Read request

Claims (4)

[Claims] 1. A processor on the production side for transmitting information,
In a multiprocessor traffic control method in which a consumer processor that receives the information is mutually coupled via a bus to perform a cooperative operation, a processor on the producer side produces processing data at a predetermined cycle. A step in which the processor on the consumption side requests the processor on the production side to read the processing data via the bus in a fixed order in advance; The processor on the production side, which has received the request from the processor on the side, sends the processing data without control information to the bus, and the processor on the consumer side, which has requested the reading, transmits the processing data via the bus. And a step of receiving the received traffic. 2. The processor on the producing side causes the processor on the consuming side to release the bus occupied for reading the processed data until the production of the processed data is completed. The traffic control method for a multiprocessor according to claim 1, wherein: 3. A plurality of the processors on the consumption side, which receive the processing data from the same processor on the production side, respectively, wherein the processors on the consumption side which receive the processing data from the same processor on the production side, Message data indicating that reception has been completed is transmitted to a predetermined processor on the consumption side, and the processor on the consumption side that has received the message data then transmits the processing data to the same processor on the production side. 3. The multiprocessor traffic control method according to claim 1, wherein a read request is made. 4. In a plurality of the processors on the consumption side, each of which receives the processing data from the same processor on the production side, the processor on the consumption side which receives the processing data from the same processor on the production side, Sending message data indicating that the reception is completed to the same processor on the production side, and the same processor on the production side does not respond to the read request of the next processor on the consumption side until the message data is received. The traffic control method for a multiprocessor according to claim 1 or 2, characterized in that: