JPH09148436A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device the load element of which has a stable resistance value and which has stable characteristics by preventing hydrogen, mobile ions, etc., from reaching the load element. SOLUTION: Since an Si3 N4 film 42 and Al wiring layers 48 and 52 in a scribe area 45 prevent hydrogen, mobile ions, etc., from reaching a polycrystalline Si layer 38 and an SiO2 film 35 is provided below the wiring layer 48 in the scribe area 45, an Si substrate 31 is not etched when a tungsten layer 47 which is formed for burying a contact area 44 is etched back and no step disconnection occurs in the wiring layers 48 and 52, because the level difference in the scribe area 45 becomes smaller.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a contact region with respect to a semiconductor substrate is filled with a conductive layer and a load element is provided, and a manufacturing method thereof.

[0002]

2. Description of the Related Art Fine S with a minimum line width of about 0.35 μm
The demand for RAM products is predominantly high-speed operation type rather than low power consumption type. Therefore, as a load element of the flip-flop that constitutes the memory cell,
It is not necessary to use a thin film transistor having a large off-current ratio, and low-cost resistance elements are being used again.

On the other hand, when hydrogen, movable ions, or the like that have entered from the outside of the SRAM during or after manufacture reach the resistance element, the resistance value of the resistance element fluctuates, and stable memory retention characteristics cannot be obtained. Therefore, S is formed on the upper layer of the resistance element.
i ₃ to form the N ₄ film, the end face of the interlayer insulating film that faces the scribe region covered with the Al wiring layer, these Si ₃ N
It has been considered to use the _four films and the Al wiring layer as stoppers for hydrogen, mobile ions, etc. (for example, JP-A-63-12).
8733).

[0004]

However, in a fine SRAM having a minimum line width of about 0.35 μm, the contact region between the Al wiring and the semiconductor substrate is filled with a tungsten plug by the blanket CVD method. With such a structure, , Al covering the end face of the interlayer insulating film facing the scribe region
It is difficult to use the wiring layer as a stopper for hydrogen or mobile ions.

That is, in order to manufacture a high resistance load type SRAM, as shown in FIG.
2 and a SiO ₂ film 13, which is a field oxide film, are formed, and further, a diffusion layer 14, a transistor (not shown), etc. are formed. Then, a SiO ₂ film 15, which is an interlayer insulating film, is deposited, and a resistance element or the like is formed from the polycrystalline Si layer 16.

After that, the SiO ₂ film 1 which is an interlayer insulating film is formed.
7. Si ₃ N ₄ film 18 and Si which is the interlayer insulating film
The O ₂ film 21 is sequentially deposited. Then, the contact region 22 reaching the diffusion layer 14 is covered with the SiO ₂ films 21, 17, 1
5 and the Si ₃ N ₄ film 18 and the like, as well as the SiO ₂ films 21, 17, 15 and S in the scribe region 23.
The i ₃ N ₄ film 18 and the like are removed.

Next, as shown in FIG. 11, TiN on the upper layer side
After forming the barrier metal layer 24 composed of the film and the lower Ti film, the tungsten layer 25 is formed by the blanket CVD method.
Deposit. Then, as shown in FIG. 12, the tungsten layer 25 and the barrier metal layer 24 are etched back,
The contact region 22 is filled with these tungsten layers 25 and the like.

However, as is apparent from FIG. 11, the contact region 22 having a small diameter is filled with the tungsten layer 25 deposited by the blanket CVD method, but the width is 1
The scribe region 23 as wide as about 00 μm is not filled with the tungsten layer 25. On the other hand, the etching selection ratio between the tungsten layer 25 and the like and the Si substrate 11 is small.

Therefore, as shown in FIG. 12, the Si substrate 11 in the scribe region 23 is also etched by etching back the tungsten layer 25 and the like. Moreover,
It is difficult to control the etching depth, and the etching depth may be 0.5 μm or more.

As a result, the step difference in the scribe region 23 becomes large, and there is a possibility that the Al wiring layer to be deposited thereafter in the scribe region 23 will have a step breakage. It was difficult to use it as a stopper.

Si substrate 11 in scribe area 23
In order to prevent such etching, the scribe region 23 may be filled with the tungsten layer 25, but as described above, it is not realistic to completely fill the scribe region 23 having a wide width of about 100 μm with the tungsten layer 25. .

Further, SiO in the scribe region 23
_The Si substrate 11 will not be etched unless the ₂ films 21, 17, 15 and the Si ₃ N ₄ film 18 are removed, but if this etching is not performed, the scribe region 2
Not only the end faces of the SiO ₂ films 21, 17, 15 and the Si ₃ N ₄ film 18 facing 3 can not be covered with the Al wiring layer, but also cracks called chipping occur in the chip during the dancing after the wafer process. To do.

[0013]

According to another aspect of the present invention, there is provided a semiconductor device having a contact region formed in an interlayer insulating film on a semiconductor substrate for electrically connecting a first metal wiring layer and the semiconductor substrate. In a semiconductor device in which a load element is provided while being filled with a conductive layer, a semiconductor nitride film is provided in a layer above the load element, and in the scribe region in the interlayer insulating film including the semiconductor nitride film. A second metal wiring layer in the same layer as the first metal wiring layer covers the facing end surface, and an insulating film is provided between the semiconductor substrate and the second metal wiring layer in the scribe region. And a third metal wiring layer, which is an upper layer than the first and second metal wiring layers, connects the semiconductor substrate and the second metal wiring layer in the scribe region, and an end surface of the insulating film. It is characterized in that the covers.

A semiconductor device according to a second aspect is the semiconductor device according to the first aspect, wherein the load element is a resistance element.

According to a third aspect of the present invention, in the semiconductor device according to the first aspect, the load element is a thin film transistor.

A semiconductor device according to a fourth aspect is the semiconductor device according to the first aspect, characterized in that the conductive layer is a refractory metal layer.

According to a fifth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein a contact region for electrically connecting the first metal wiring layer and the semiconductor substrate is formed in an interlayer insulating film on the semiconductor substrate and has a conductive layer. In a method for manufacturing a semiconductor device in which a load element is provided while being filled with, a step of forming a pad layer having a different etching characteristic from the interlayer insulating film on the insulating film in the scribe region, and a layer above the load element. Forming a semiconductor nitride film, forming the contact region in the interlayer insulating film including the semiconductor nitride film, and using the pad layer as a stopper to scribe the inter-layer insulating film including the semiconductor nitride film. Removing a portion on the region, depositing the conductive layer after forming the contact region, depositing the deposited conductive layer and the passivation layer. Etching back the contact layer with the conductive layer and removing the conductive layer and the pad layer from the scribe region; and the step of contacting the conductive layer filling the contact region. A first metal wiring layer and a second metal wiring layer which is the same layer as the first metal wiring layer and covers an end face of the interlayer insulating film including the semiconductor nitride film which faces the scribe region. A step of removing a portion of the insulating film in the scribe region that is not covered with the second metal wiring layer to expose the semiconductor substrate; and a step of exposing the semiconductor substrate from the first and second metal wiring layers. Is also an upper layer and connects the semiconductor substrate exposed in the scribe region to the second metal wiring layer, and forms a third metal wiring layer covering the end face of the insulating film. It is characterized by comprising and.

The method of manufacturing a semiconductor device according to claim 6 is the method of manufacturing a semiconductor device according to claim 5, characterized in that a refractory metal layer is used as the conductive layer.

According to another aspect of the semiconductor device of the present invention, the end face of the interlayer insulating film facing the scribe region is covered with the second metal wiring layer, and the first metal wiring layer is the same layer as the first metal wiring layer.
The contact region for electrically connecting the metal wiring layer and the semiconductor substrate is filled with a conductive layer, but an insulating film is provided between the semiconductor substrate and the second metal wiring layer in the scribe region. ing.

Therefore, even when the conductive layer for filling the contact region is deposited, the insulating film is present between the semiconductor substrate and the conductive layer in the scribe region.
Therefore, even if the etching selection ratio between the conductive layer and the semiconductor substrate is small during the etch back for filling the contact region with the conductive layer, the semiconductor substrate can be prevented from being etched during the etch back.

On the other hand, since no conductive layer is provided below the third metal wiring layer, even if the insulating film in the scribe region is removed to connect the third metal wiring layer to the semiconductor substrate, the conductive layer is removed. The semiconductor substrate is not etched due to the etch back. Therefore, the step difference in the scribe region is small, and step disconnection does not occur in the second and third metal wiring layers.

Moreover, since the second metal wiring layer is connected to the semiconductor substrate through the third metal wiring layer, the second metal wiring layer has the same potential as the semiconductor substrate. Further, the third metal wiring layer covers the end surface of the insulating film between the semiconductor substrate and the second metal wiring layer in the scribe region. Therefore, the second and third metal wiring layers and the semiconductor nitride film serve as stoppers for hydrogen, mobile ions, etc., and prevent these hydrogen, mobile ions, etc., from reaching the load element.

In the method of manufacturing a semiconductor device according to claims 5 and 6, a pad layer having etching characteristics different from those of the interlayer insulating film is formed on the insulating film in the scribe region, and the pad layer is used as a stopper to form the interlayer on the scribe region. Since the insulating film is removed, the insulating film remains in the scribe region under the pad layer even after this removal.

Therefore, even when the conductive layer for filling the contact region is deposited, the insulating film is present between the semiconductor substrate and the conductive layer in the scribe region.
As a result, it is possible to prevent the semiconductor substrate from being etched during the etch back even if the etching selectivity of the conductive layer and the pad layer to the semiconductor substrate is small during the etch back for filling the contact region with the conductive layer. .
Therefore, the step difference in the scribe area is reduced so that the second
Also, it is possible to prevent disconnection of the third metal wiring layer.

Moreover, since the second metal wiring layer is connected to the semiconductor substrate via the third metal wiring layer, the second metal wiring layer has the same potential as the semiconductor substrate. Further, in the third metal wiring layer, the semiconductor substrate in the scribe region and the second
Covering the end surface of the insulating film between the metal wiring layer and the metal wiring layer. Therefore, the second and third metal wiring layers and the semiconductor nitride film serve as stoppers for hydrogen, mobile ions, etc., and prevent these hydrogen, mobile ions, etc., from reaching the load element.

[0026]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A specific example of the present invention applied to a high resistance load type SRAM will be described below with reference to FIGS. FIG. 1 shows an SRAM according to this example. In order to manufacture this SRAM, as shown in FIG. 2, the well 32 is formed in the Si substrate 31, and the SiO ₂ film 33 having a film thickness of 350 nm which is a field oxide film is formed by the LOCOS method.

Although not shown, a polycrystalline Si layer having a thickness of 120 nm and a tungsten silicide layer having a thickness of 120 nm are sequentially deposited to form a tungsten polycide layer. This tungsten polycide layer is processed into the pattern of the gate electrode of the transistor for peripheral use and the transistor for peripheral circuits.

After that, a diffusion layer 34 is formed, and an SiO ₂ film 35 having a film thickness of 100 nm which is an interlayer insulating film is deposited. Then, a polycrystalline Si layer having a thickness of 60 nm and a tungsten silicide layer having a thickness of 60 nm are sequentially deposited to form a tungsten polycide layer 36, and the pattern of the pad layer covering the ground line and the scribe region of the memory cell is formed into the pattern. The tungsten polycide layer 36 is processed.

After that, the SiO ₂ film 37 which is an interlayer insulating film is formed.
Is deposited to form a resistance element of a memory cell or the like with the polycrystalline Si layer 38 having a film thickness of 50 nm. Then, the SiO ₂ film 41 which is an interlayer insulating film and has a film thickness of 100 nm, the Si ₃ N ₄ film 42 which is a stopper for hydrogen and mobile ions and has a film thickness of 20 nm, and the interlayer insulating film which has a film thickness of 500 n.
The BPSG layer 43 having a thickness of m is sequentially deposited, and the BPSG layer 43 is reflowed by heat treatment at 900 ° C. to planarize the surface.

Next, as shown in FIG. 3, a contact region 44 reaching the diffusion layer 34 is opened in the BPSG layer 43, the Si ₃ N ₄ film 42, the SiO ₂ films 41, 37, 35 and the like, and the scribe region 45 is formed. BPSG layer 43, Si
_{The 3} N ₄ film 42 and the SiO ₂ films 41 and 37 are removed. At this time, in the scribe region 45, since the tungsten polycide layer 36 serves as an etching stopper, Si
The O ₂ film 35 remains and the Si substrate 31 is not exposed.

Next, as shown in FIG. 4, the film thicknesses are both 30 n.
After forming the barrier metal layer 46 composed of the upper TiN film of m and the lower Ti film, the tungsten layer 47 of 750 nm in thickness is deposited by the blanket CVD method.

Next, as shown in FIG. 5, the tungsten layer 4 is formed.
7 and the barrier metal layer 46 are etched back to fill the contact region 44 with these tungsten layers 47 and the like. At this time, in the scribe region 45 which is not filled with the tungsten layer 47 deposited by the blanket CVD method, the tungsten polycide layer 36 is also etched by the etch back of the tungsten layer 47 and the like.

However, this tungsten polycide layer 3
SiO ₂ film 35 and tungsten layer 4 remaining under
It is possible to increase the etching selection ratio with respect to 7 and the like, and the SiO ₂ film 35 has a large film thickness of 100 nm.
The SiO ₂ film 35 remains and the Si substrate 31 is not etched. In the scribe region 45, the tungsten layer 4
7 and the barrier metal layer 46 remain on the side wall.

Next, as shown in FIG. 6, the film thickness is 300 nm.
In the first Al wiring layer 48 which is
A wiring electrically connected to the diffusion layer 34 via B,
PSG layer 43, Si ₃ N ₄ film 42, SiO ₂ film 41, 3
7 and a wiring for covering the end face of the tungsten polycide layer 36 facing the scribe region 45. Then, as shown in FIG. 7, an SOG film 51 which is an interlayer insulating film is formed, and the SOG film 51 is flattened by etching back or the like.

Next, as shown in FIG.
No. 5 SOG film 51 and S not covered with Al wiring layer 48
By removing the iO ₂ film 35, Al in the scribe region 45 is removed.
The wiring layer 48 and the Si substrate 31 are exposed.

Next, as shown in FIG. 9, the film thickness is 500 nm.
In the second Al wiring layer 52, which is
A wiring for connecting the Al wiring layer 48 and the Si substrate 31 in the scribe region 45 is formed across the Al wiring layer 48 of No. 5. Therefore, the SiO ₂ film 3 facing the scribe region 45
The end faces such as 5 are also covered with the Al wiring layer 52.

After that, in order to improve the characteristics such as the contact resistance of the Al wiring layers 48 and 52, 450 in a hydrogen atmosphere.
Although the heat treatment is performed at a temperature of 60 ° C., the Si ₃ N ₄ film 42 and the Al wiring layers 48 and 52 in the scribe region 45 serve as stoppers for hydrogen, movable ions, etc.
Hydrogen and mobile ions do not reach the layer 38. Then, as shown in FIG. 1, Si ₃ deposited by plasma CVD method
The high resistance load type SRAM is completed by forming the N ₄ film overcoat film 53 and the like.

When hydrogen or mobile ions reach the active layer of a thin film transistor (TFT) or the like, the threshold voltage or on-current of the TFT fluctuates, which is not so remarkable as the resistance element. The value also fluctuates. Therefore,
Not only the high resistance load type SRAM as in the above specific example but also a TFT using a TFT as a load element of a flip-flop
The present invention can be applied to a load type SRAM.

Although the tungsten layer 47 is used as the plug for filling the contact region 44 in the above-described specific example, another conductive layer such as a polycrystalline Si layer may be used as the plug. The invention of the present application can be naturally applied to a semiconductor device other than the SRAM as long as it is a semiconductor device in which a contact region with respect to the semiconductor substrate is filled with a conductive layer and a load element is provided.

[0040]

In the semiconductor device and the method of manufacturing the same according to the present invention, the second and third metal wiring layers and the semiconductor nitride film serve as stoppers for hydrogen, mobile ions, etc., and these hydrogen, mobile ions, etc. Can be prevented from reaching the load element, so that it is possible to provide a semiconductor device in which the resistance value of the load element is stable and the characteristics are stable.

[Brief description of the drawings]

FIG. 1 is a side sectional view of a specific example of the present invention.

FIG. 2 is a side sectional view showing a first step for manufacturing a specific example.

FIG. 3 is a side sectional view showing a step following FIG. 2;

FIG. 4 is a side sectional view showing a step following FIG. 3;

FIG. 5 is a side sectional view showing a step following FIG. 4;

FIG. 6 is a side sectional view showing a step following FIG. 5;

FIG. 7 is a side sectional view showing a step following FIG. 6;

8 is a side sectional view showing a step that follows FIG. 7. FIG.

9 is a side sectional view showing a step that follows FIG.

FIG. 10 is a side sectional view showing a first step for manufacturing a conventional example of the present invention.

FIG. 11 is a side sectional view showing a step following FIG. 10;

12 is a side sectional view showing a step that follows FIG. 11. FIG.

[Explanation of symbols]

31 Si substrate 35 SiO ₂ film 36 Tungsten polycide layer 37 SiO ₂ film 38 Polycrystalline Si layer 41 SiO ₂ film 42 Si ₃ N ₄ film 43 BPSG layer 44 Contact region 45 Scribing region 47 Tungsten layer 48 Al wiring layer 52 Al wiring layer

Claims (6)

[Claims] 1. A contact region formed in an interlayer insulating film on a semiconductor substrate for electrically connecting a first metal wiring layer and the semiconductor substrate is filled with a conductive layer and a load element is provided. In the semiconductor device, a semiconductor nitride film is provided in an upper layer than the load element, and an end face of the interlayer insulating film including the semiconductor nitride film facing a scribe region is the same as the first metal wiring layer. And a second metal wiring layer covering the semiconductor substrate and the second metal wiring layer in the scribe region.
An insulating film is provided between the semiconductor substrate and the second metal in the scribe region, the third metal wiring layer being an upper layer than the first and second metal wiring layers. A semiconductor device which is connected to a wiring layer and covers an end face of the insulating film. 2. The semiconductor device according to claim 1, wherein the load element is a resistance element. 3. The semiconductor device according to claim 1, wherein the load element is a thin film transistor. 4. The semiconductor device according to claim 1, wherein the conductive layer is a refractory metal layer. 5. A contact region formed in an interlayer insulating film on a semiconductor substrate for electrically connecting the first metal wiring layer and the semiconductor substrate is filled with a conductive layer and a load element is provided. In the method of manufacturing a semiconductor device, a step of forming a pad layer having a different etching characteristic from the interlayer insulating film on an insulating film in a scribe region, and a step of forming a semiconductor nitride film above the load element, Forming the contact region in the interlayer insulating film including the semiconductor nitride film, and removing a portion of the interlayer insulating film including the semiconductor nitride film on the scribe region while using the pad layer as a stopper; A step of depositing the conductive layer after forming the contact region, and etching back the deposited conductive layer and the pad layer, Filling the contact region with the conductive layer and removing the conductive layer and the pad layer from the scribe region; the first metal wiring layer in contact with the conductive layer filling the contact region; Forming a second metal wiring layer, which is the same layer as the first metal wiring layer and covers the end face facing the scribe region, in the interlayer insulating film including the semiconductor nitride film; and the insulating in the scribe region. Removing a portion of the film not covered by the second metal wiring layer to expose the semiconductor substrate; and exposing the semiconductor substrate above the first and second metal wiring layers in the scribe region. The semiconductor substrate and the second
And a step of forming a third metal wiring layer that covers the end surface of the insulating film and is connected to the metal wiring layer of. 6. The method of manufacturing a semiconductor device according to claim 5, wherein a refractory metal layer is used as the conductive layer.